Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 16 (4x4) 16-Bit 16 MHz I/O number 10

MSP430F2013-EP

www.ti.com

SLAS774A –JULY 2011– REVISED OCTOBER 2011

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Brownout Detector

• Serial Onboard Programming, No External

• Low Supply Voltage Range 1.8 V to 3.6 V

Programming Voltage Needed, Programmable

• Ultra-Low Power Consumption

Code Protection by Security Fuse

– Active Mode: 220 µA at 1 MHz, 2.2 V

• On-Chip Emulation Logic With Spy-Bi-Wire

– Standby Mode: 0.5 µA

Interface

– Off Mode (RAM Retention): 0.1 µA

• 2KB + 256B Flash Memory; 128B RAM

• Five Power-Saving Modes

• Available in a 16-Pin QFN Package

• Ultra-Fast Wake-Up From Standby Mode in

• For Complete Module Descriptions, See the

Less Than 1 µs

MSP430x2xx Family User's Guide (SLAU144)

• 16-Bit RISC Architecture, 62.5-ns Instruction

Cycle Time

SUPPORTS DEFENSE, AEROSPACE,

• Basic Clock Module Configurations:

AND MEDICAL APPLICATIONS

– Internal Frequencies up to 16 MHz With

• Controlled Baseline

Four Calibrated Frequencies to ±1%

• One Assembly/Test Site

– Internal Very Low-Power Low-Frequency

• One Fabrication Site

Oscillator

• Available in Extended (–40°C/125°C)

– 32-kHz Crystal

(1)

Temperature Range

(3)

– External Digital Clock Source

• Extended Product Life Cycle

• 16-Bit Timer_A With Two Capture/Compare

• Extended Product-Change Notification

Registers

• Product Traceability

• 16-Bit Sigma-Delta A/D Converter

With Differential PGA Inputs and Internal

Reference

(2)

• Universal Serial Interface (USI) Supporting SPI

and I2C

(1) Crystal oscillator cannot be operated beyond 105°C.

(2) ADC performance characterized up to 105°C only. (3) Custom temperature ranges available

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430F2013 is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O pins.

In addition, the MSP430F2013 has a built-in communication capability using synchronous protocols (SPI or I2C)

and a 16-bit sigma-delta A/D converter.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand alone RF sensor front end is another

area of application.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (54 pages)

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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • • (1) (2) Low Supply Voltage Range 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Table 1. ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER VID NUMBER -40°C to 125°C QFN (RSA) MSP430F2013QRSATEP V62/11613-01XE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Functional Block Diagram VCC VSS P1.x & JTAG 8 XIN P2.x & XIN/XOUT 2 XOUT Basic Clock System+ ACLK SD16_A SMCLK MCLK 16MHz CPU incl.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Table 2. Terminal Functions TERMINAL NAME DESCRIPTION NO. I/O P1.0/TACLK/ACLK/A0+ 1 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal output SD16_A positive analog input A0 P1.1/TA0/A0-/A4+ 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output SD16_A negative analog input A0 SD16_A positive analog input A4 P1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 5.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Memory Organization Table 8.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430F2xx Family User's Guide.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com USI The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C. SD16_A The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, internal VCC sense and temperature sensors are also available.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V ±2 mA Diode current at any device terminal Storage temperature (3) Tstg (1) (2) (3) Unprogrammed device -55°C to 150°C Programmed device -40°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Legend : System Frequency −MHz 16 MHz Supply voltage range, during flash memory programming 12 MHz Supply voltage range, during program execution 6 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage −V Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Safe Operating Area Estimated Life (Years) 100.00 10.00 1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TYP MAX 2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 ILPM3,LFXT1 TEST CONDITIONS TA (1) (2) (3) (4) (5) 16 TYP MAX 2.2 V 65 86 Low-power mode 0 (LPM0) current (3) 3V 85 108 2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Outputs (Ports P1 and P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA VOH (1) (2) MAX VCC - 0.25 VCC VCC - 0.6 VCC I(OHmax) = -1.5 mA (1) 3V VCC - 0.25 VCC I(OHmax) = -6 mA (2) 3V VCC - 0.6 VCC 2.2 V VSS VSS + 0.25 2.2 V VSS VSS + 0.6 I(OLmax) = 1.5 mA (1) 3V VSS VSS + 0.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Typical Characteristics - Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P1.7 TA = 25°C 25.0 TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 25°C 3V 0.990 1 1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs TEMPERATURE CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 1.03 1.02 1.02 TA = 125°C VCC = 1.8 V 1.00 Frequency − MHz Frequency − MHz 1.01 VCC = 3.0 V VCC = 2.2 V 0.99 1.01 TA = 105°C TA = 85°C 1.00 TA = 25°C 0.99 TA = −40°C 0.98 0.97 −50 0.98 VCC = 3.6 V −25 0 25 50 75 TA − Temperature − °C Figure 12.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) (1) over recommended ranges of supply voltage and up to operating free-air temperature TA = 105°C PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 2.2 V/3 V (1) (2) (3) 1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com USI, Universal Serial Interface (1) over recommended ranges of supply voltage and up to operating free-air temperature TA = 105°C PARAMETER fUSI TEST CONDITIONS External: SCLK, Duty cycle = 50% ±10%, SPI slave mode USI clock frequency USI module in I2C mode, I(OLmax) = 1.5 mA VOL,I2C Low-level output voltage on SDA and SCL (1) VCC MIN TYP MAX 2.2 V 10 3V 16 2.2 V/3 V VSS UNIT MHz VSS + 0.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com SD16_A, Power Supply and Recommended Operating Conditions (1) over recommended ranges of supply voltage and up to operating free-air temperature TA = 105°C PARAMETER AVCC Analog supply voltage range TEST CONDITIONS TA SD16LP = 0, fSD16 = 1 MHz, SD16OSR = 256 Analog supply current including internal reference (1) SD16 input clock frequency TYP 2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Typical Characteristics, SD16_A SINAD Performance Over OSR SINAD PERFORMANCE vs OSR (fSD16 = 1 MHz, SD16REFON = 1,SD16GAINx = 1) 90.0 85.0 SINAD − dB 80.0 75.0 70.0 65.0 RSA PW, or N 60.0 55.0 10.00 100.00 1000.00 OSR Figure 17.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com SD16_A, Built-In Voltage Reference (1) over recommended ranges of supply voltage and up to operating free-air temperature TA = 105°C PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 3V 1.14 1.20 1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com SD16_A, Temperature Sensor (1) (2) over recommended ranges of supply voltage and up to operating free-air temperature TA = 105°C PARAMETER TEST CONDITIONS VCC MIN TYP MAX 1.32 1.46 mV/°C TCSensor Sensor temperature coefficient 1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length (1) 2.2 V/3 V 0.025 15 µs tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (2)) 2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION Port P1 (P1.0) Pin Schematics INCH=0 Pad Logic A0+ SD16AE.0 P1REN.0 P1DIR.0 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.0 DVSS P1.0/TACLK/ACLK/A0+ Bus Keeper P1SEL.0 EN P1IN.0 EN Module X IN D P1IE.0 P1IRQ.0 EN Q P1IFG.0 P1SEL.0 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.1) Pin Schematics INCH=4 Pad Logic A4+ INCH=0 0 A0− AV SS 1 SD16AE.1 P1REN.1 P1DIR.1 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.1 DVSS P1.1/TA 0/A0−/A4+ Bus Keeper P1SEL.1 EN P1IN.1 EN Module X IN D P1IE.1 P1IRQ.1 P1IFG.1 P1SEL.1 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.2) Pin Schematics INCH=1 Pad Logic A1+ INCH=4 0 A4− AV SS 1 SD16AE.2 P1REN.2 P1DIR.2 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.2 DVSS P1.2/TA 1/A1+/A4− Bus Keeper P1SEL.2 EN P1IN.2 EN Module X IN D P1IE.2 P1IRQ.2 EN Q P1IFG.2 P1SEL.2 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.3) Pin Schematics Pad Logic VREF INCH=1 0 A1− AV SS 1 SD16AE.3 P1REN.3 P1DIR.3 0 0 1 0 1 P1.3/VREF/A1− Bus Keeper P1SEL.3 EN P1IN.3 P1IE.3 P1IRQ.3 EN Q P1IFG.3 P1SEL.3 P1IES.3 38 1 Direction 0: Input 1: Output 1 P1OUT.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Table 13. Port P1 (P1.0 to P1.3) Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 P1.0/TACLK/ACLK/A0+ 0 1 0 N/A 1 0 N/A ACLK 1 1 0 N/A A0+ (4) X X 1 0 0/1 0 0 N/A Timer_A2.CCI0A input/output 0 1 0 N/A Timer_A2.TA0 1 1 0 N/A X X 1 0 X X 1 4 0/1 0 0 N/A Timer_A2.CCI1A 0 1 0 N/A Timer_A2.TA1 1 1 0 N/A A1+ (4) X X 1 1 A4- (4) (5) X X 1 4 (4) (5) P1.2 (3) input/output P1.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.4) Pin Schematics INCH=2 Pad Logic A2+ SD16AE.4 P1REN.4 P1DIR.4 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.4 DVSS DVCC P1.4/SMCLK/A2+/TCK Bus Keeper P1SEL.4 EN P1IN.4 EN Module X IN D P1IE.4 P1IRQ.4 EN Q P1IFG.4 P1SEL.4 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.5) Pin Schematics Pad Logic INCH=2 0 A2− AV SS 1 SD16AE.5 P1REN.5 P1SEL.5 USIPE5 P1DIR.5 0 USI Module Direction 1 P1OUT.5 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.5/TA 0/SCLK/A2−/TMS Bus Keeper EN P1IN.5 EN Module X IN D P1IE.5 P1IRQ.5 EN Q P1IFG.5 P1SEL.5 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.6) Pin Schematics Pad Logic INCH=3 A3+ SD16AE.6 P1REN.6 P1SEL.6 USIPE6 P1DIR.6 0 USI Module Direction 1 P1OUT.6 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.6/TA1/SDO/SCL/A3+/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.6 EN Module X IN D P1IE.6 P1IRQ.6 EN Q P1IFG.6 P1SEL.6 P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P1 (P1.7) Pin Schematics Pad Logic INCH=3 0 A3− AV SS 1 SD16AE.x P1REN.x P1SEL.x USIPE7 P1DIR.x 0 USI Module Direction 1 P1OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1.7/SDI/SDA/A3−/TDO/TDI USI Module Output (I2C Mode) Bus Keeper EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Table 14. Port P1 (P1.4 to P1.7) Pin Functions PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x SD16AE.x INCHx JTAG Mode 0/1 0 N/A 0 N/A 0 N/A 0 1 N/A 0 N/A 0 SMCLK 1 1 N/A 0 N/A 0 A2+ (4) X X N/A 1 2 0 TCK (5) X X N/A X X 1 0/1 0 0 0 N/A 0 N/A 0 1 0 0 N/A 0 Timer_A2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P2 (P2.6) Pin Schematics LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 P2SEL.7 Pad Logic P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/TA1 Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 EN P2IRQ.6 Q P2IFG.6 Set Interrupt Edge Select P2SEL.6 P2IES.6 Table 15. Port P2 (P2.6) Pin Functions PIN NAME (P2.
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MSP430F2013-EP SLAS774A – JULY 2011 – REVISED OCTOBER 2011 www.ti.com Port P2 (P2.7) Pin Schematics LFXT1 Oscillator BCSCTL3.LFXT1Sx = 11 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN/TA1 Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 EN P2IRQ.7 Q P2IFG.7 Set Interrupt Edge Select P2SEL.7 P2IES.7 Table 16. Port P2 (P2.7) Pin Functions PIN NAME (P2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F2013QRSATEP Package Package Pins Type Drawing QFN RSA 16 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2013QRSATEP QFN RSA 16 250 210.0 185.0 35.
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