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MSP430x2xx Family

User's Guide

Literature Number: SLAU144J

December 2004–Revised July 2013

Summary of content (644 pages)

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MSP430x2xx Family User's Guide Literature Number: SLAU144J December 2004 – Revised July 2013
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Contents ...................................................................................................................................... Introduction ...................................................................................................................... 1.1 Architecture ................................................................................................................. 1.2 Flexible Clock System ...............................................................................
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www.ti.com 3.4.4 3.4.5 3.4.6 4 CPUX .............................................................................................................................. 115 4.1 4.2 4.3 4.4 4.5 4.6 5 CPU Introduction ......................................................................................................... Interrupts .................................................................................................................. CPU Registers ................................................
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www.ti.com 6.3 7 Flash Memory Controller 7.1 7.2 7.3 7.4 8 8.3 298 299 299 299 300 300 301 301 301 302 303 303 304 305 306 306 307 .................................................................................................. 308 Memory Introduction ............................................................................................. Memory Segmentation ........................................................................................... SegmentA ..................................
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www.ti.com 9.3 10 Watchdog Timer+ (WDT+) 10.1 10.2 10.3 11 12 13 9.2.2 SVS Comparator Operation ................................................................................... 9.2.3 Changing the VLDx Bits ........................................................................................ 9.2.4 SVS Operating Range .......................................................................................... SVS Registers ...........................................................................
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www.ti.com 13.3 14 Universal Serial Interface (USI) 14.1 14.2 14.3 15 15.4 396 399 399 399 400 402 405 406 407 408 408 409 409 ........................................................ 410 USCI Overview ........................................................................................................... USCI Introduction: UART Mode ........................................................................................ USCI Operation: UART Mode .................................................
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www.ti.com 15.4.13 IFG2, Interrupt Flag Register 2 ............................................................................. 433 15.4.14 UC1IE, USCI_A1 Interrupt Enable Register .............................................................. 434 15.4.15 UC1IFG, USCI_A1 Interrupt Flag Register ............................................................... 434 16 Universal Serial Communication Interface, SPI Mode 16.1 16.2 16.3 16.4 17 Universal Serial Communication Interface, I2C Mode 17.1 17.2 17.
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www.ti.com 17.4.12 IFG2, Interrupt Flag Register 2 ............................................................................. 472 17.4.13 UC1IE, USCI_B1 Interrupt Enable Register .............................................................. 472 17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register ............................................................... 473 18 USART Peripheral Interface, UART Mode 18.1 18.2 18.3 19 USART Peripheral Interface, SPI Mode 19.1 19.2 19.3 20 OA 20.1 8 ............
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www.ti.com 20.2 20.3 21 Comparator_A+ 21.1 21.2 21.3 22 22.3 23.1 23.2 524 525 525 525 526 526 527 527 528 528 530 531 532 532 ............................................................................................................................ 533 ADC10 Introduction ...................................................................................................... ADC10 Operation ........................................................................................................
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www.ti.com 23.3 24 24.3 24.4 10 565 565 570 571 572 574 575 577 578 578 579 579 580 .................................................................................................................. 581 TLV Introduction .......................................................................................................... Supported Tags .......................................................................................................... 24.2.1 DCO Calibration TLV Structure ...................
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www.ti.com 26.3.5 SD16AE, SD16_A Analog Input Enable Register ......................................................... 615 26.3.6 SD16IV, SD16_A Interrupt Vector Register ................................................................ 615 27 SD24_A ........................................................................................................................... 616 27.1 27.2 27.3 SD24_A Introduction .............................................................................................
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www.ti.com List of Figures MSP430 Architecture 1-2. Memory Map ............................................................................................................... 25 1-3. Bits, Bytes, and Words in a Byte-Organized Memory ................................................................ 26 2-1. Power-On Reset and Power-Up Clear Schematic .................................................................... 29 2-2. Brownout Timing ............................................................
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www.ti.com 4-16. Indexed Mode in Upper Memory ....................................................................................... 128 4-17. Overflow and Underflow for Indexed Mode ........................................................................... 129 4-18. Symbolic Mode Running in Lower 64KB .............................................................................. 132 4-19. Symbolic Mode Running in Upper Memory 4-20. 4-21. 4-22. 4-23. 4-24. 4-25. 4-26. 4-27. 4-28. 4-29. 4-30.
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www.ti.com 5-6. Typical DCOx Range and RSELx Steps .............................................................................. 278 5-7. Modulator Patterns ....................................................................................................... 279 5-8. Oscillator-Fault Logic .................................................................................................... 280 5-9. Switch MCLK from DCOCLK to LFXT1CLK ................................................................
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www.ti.com 13-8. Up/Down Mode Flag Setting............................................................................................ 380 13-9. Output Unit in Up/Down Mode ......................................................................................... 381 13-10. Capture Signal (SCS = 1) ............................................................................................... 381 13-11. Capture Cycle .....................................................................................
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www.ti.com 18-7. MSP430 Baud Rate Generator......................................................................................... 481 18-8. BITCLK Baud Rate Timing 18-9. Receive Error ............................................................................................................. 485 ............................................................................................. ...........................................................................................
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www.ti.com 23-3. Extended Sample Mode................................................................................................. 564 23-4. Pulse Sample Mode ..................................................................................................... 564 23-5. Analog Input Equivalent Circuit 23-6. Single-Channel, Single-Conversion Mode ............................................................................ 566 23-7. Sequence-of-Channels Mode .....................................
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www.ti.com List of Tables 1-1. MSP430x2xx Family Enhancements.................................................................................... 27 2-1. Interrupt Sources, Flags, and Vectors .................................................................................. 37 2-2. Operating Modes For Basic Clock System............................................................................. 39 2-3. Connection of Unused Pins .......................................................................
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www.ti.com 7-1. Erase Modes.............................................................................................................. 312 7-2. Write Modes .............................................................................................................. 315 7-3. Flash Access While BUSY = 1 ......................................................................................... 320 7-4. Flash Memory Registers ...........................................................................
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www.ti.com 22-1. Conversion Mode Summary ............................................................................................ 539 22-2. Maximum DTC Cycle Time ............................................................................................. 549 22-3. ADC10 Registers......................................................................................................... 552 23-1. Conversion Mode Summary ..............................................................................
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Preface SLAU144J – December 2004 – Revised July 2013 Read This First About This Manual This manual discusses modules and peripherals of the MSP430x2xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family.
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Register Bit Conventions MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCLK SP SR src TOS WDT www.ti.
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Chapter 1 SLAU144J – December 2004 – Revised July 2013 Introduction This chapter describes the architecture of the MSP430. Topic 1.1 1.2 1.3 1.4 1.5 ........................................................................................................................... Architecture ...................................................................................................... Flexible Clock System ........................................................................................
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Architecture 1.1 www.ti.com Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB) (see Figure 11). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x2xx family include: • Ultralow-power architecture extends battery life – 0.
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Embedded Emulation www.ti.com 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: • Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an application are supported. • Development is in-system subject to the same characteristics as the final application.
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Address Space www.ti.com 1.4.2 RAM RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data. 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0.
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MSP430x2xx Family Enhancements www.ti.com 1.5 MSP430x2xx Family Enhancements Table 1-1 highlights enhancements made to the MSP430x2xx family. The enhancements are discussed fully in the following chapters, or in the case of improved device parameters, shown in the device-specific data sheet. Table 1-1. MSP430x2xx Family Enhancements Subject Enhancement Reset • Brownout reset is included on all MSP430x2xx devices. • PORIFG and RSTIFG flags have been added to IFG1 to indicate the cause of a reset.
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Chapter 2 SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x2xx system resets, interrupts, and operating modes. Topic 2.1 2.2 2.3 2.4 2.5 28 ........................................................................................................................... System Reset and Initialization ........................................................................... Interrupts ................................................
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System Reset and Initialization www.ti.com 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2-1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
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System Reset and Initialization www.ti.com VCC Vhys(B_IT−) V(B_IT+) V(B_IT−) VCC(start) Set Signal for POR circuitry t (BOR) Figure 2-2. Brownout Timing As the V(B_IT-) level is significantly above the Vmin level of the POR circuit, the BOR provides a reset for power failures where VCC does not fall below Vmin. See device-specific data sheet for parameters. 2.1.
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Interrupts www.ti.com 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2-3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously.
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Interrupts www.ti.com ACCV S ACCVIFG POR FCTL3.2 S ACCVIE PORIFG IFG1.2 IE1.5 Clear PUC Flash Module RST/NMI S RSTIFG POR IFG1.3 PUC Clear KEYV SVS_POR BOR POR PUC System Reset Generator POR S NMIIFG NMIRS IFG1.4 WDTTMSEL WDTNMIES WDTNMI Clear WDTQn EQU PUC POR PUC NMIIE S IE1.4 Clear WDTIFG IR Q IFG1.0 Clear PUC WDT Counter OSCFault POR S OFIFG IFG1.1 IRQA WDTTMSEL OFIE WDTIE IE1.1 Clear PUC IE1.
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Interrupts www.ti.com 2.2.1.1 Reset/NMI Pin At power-up, the RST/NMI pin is configured in the reset mode. The function of the RST/NMI pins is selected in the watchdog control register WDTCTL. If the RST/NMI pin is set to the reset function, the CPU is held in the reset state as long as the RST/NMI pin is held low. After the input changes to a high state, the CPU starts program execution at the word address stored in the reset vector, 0FFFEh, and the RSTIFG flag is set.
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Interrupts 2.2.1.4 www.ti.com Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2-5.
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Interrupts www.ti.com 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)maskable interrupts to be requested. 2.2.3.
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Interrupts 2.2.3.2 www.ti.com Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles (CPU) or 3 cycles (CPUx) to execute the following actions and is illustrated in Figure 2-7. 1. The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine. 2.
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Interrupts www.ti.com 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h, as described in Table 2-1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine. See the device-specific data sheet for the complete interrupt vector list. It is recommended to provide an interrupt service routine for each interrupt vector that is assigned to a module.
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Operating Modes 2.3 www.ti.com Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2-9. The operating modes take into account three different needs: • Ultralow-power • Speed and data throughput • Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2-8. 300 ICC/µA at 1 MHz 315 270 225 200 VCC = 3 V 180 VCC = 2.2 V 135 90 45 55 32 0 AM LPM0 17 11 0.9 0.
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Operating Modes www.ti.
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Principles for Low-Power Applications www.ti.com 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: • Enter interrupt service routine: – The PC and SR are stored on the stack – The CPUOFF, SCG1, and OSCOFF bits are automatically reset • Options for returning from the interrupt service routine: – The original SR is popped from the stack, restoring the previous operating mode.
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Connection of Unused Pins www.ti.com 2.5 Connection of Unused Pins The correct termination of all unused pins is listed in Table 2-3. Table 2-3. Connection of Unused Pins (1) Pin Potential AVCC DVCC AVSS DVSS Comment VREF+ Open VeREF+ DVSS VREF-/VeREF- DVSS XIN DVCC For dedicated XIN pins only. XIN pins with shared GPIO functions should be programmed to GPIO and follow Px.0 to Px.7 recomendations. XOUT Open For dedicated XOUT pins only.
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Chapter 3 SLAU144J – December 2004 – Revised July 2013 CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic 3.1 3.2 3.3 3.4 42 CPU ........................................................................................................................... CPU Introduction ............................................................................................... CPU Registers ..........................................................................................
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CPU Introduction www.ti.com 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing, and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: • RISC architecture with 27 instructions and 7 addressing modes. • Orthogonal architecture with every instruction usable with every addressing mode.
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CPU Registers www.ti.
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CPU Registers www.ti.com The PC can be addressed with all instructions and addressing modes. A few examples: MOV MOV MOV #LABEL,PC LABEL,PC @R14,PC ; Branch to address LABEL ; Branch to address contained in LABEL ; Branch indirect to address in R14 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme.
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CPU Registers www.ti.com Figure 3-6. Status Register Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved V SCG1 SCG0 OSC OFF CPU OFF GIE N Z C rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table 3-1 describes the status register bits. Table 3-1. Description of Status Register Bits Bit Description V Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range. Set when: ADD(.B),ADDC(.
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Addressing Modes www.ti.com The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. 3.2.4.1 Constant Generator - Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions.
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Addressing Modes www.ti.com Table 3-3. Source/Destination Operand Addressing Modes As/Ad Addressing Mode Syntax Description 00/0 Register mode Rn 01/1 Indexed mode X(Rn) (Rn + X) points to the operand. X is stored in the next word. 01/1 Symbolic mode ADDR (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC) is used. 01/1 Absolute mode &ADDR The word following the instruction contains the absolute address. X is stored in the next word.
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Addressing Modes www.ti.com 3.3.1 Register Mode The register mode is described in Table 3-4. Table 3-4. Register Mode Description Assembler Code MOV Length: Operation: Comment: Example: R10,R11 Content of ROM MOV R10,R11 One or two words Move the content of R10 to R11. R10 is not affected.
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Addressing Modes www.ti.com 3.3.2 Indexed Mode The indexed mode is described in Table 3-5. Table 3-5. Indexed Mode Description Assembler Code Content of ROM MOV 2(R5),6(R6) MOV X(R5),Y(R6) X=2 Y=6 Length: Operation: Comment: Example: Two or three words Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected.
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Addressing Modes www.ti.com 3.3.3 Symbolic Mode The symbolic mode is described in Table 3-6. Table 3-6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(PC),Y(PC) X = EDE – PC Y = TONI – PC Length: Operation: Comment: Example: MOV Two or three words Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y).
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Addressing Modes www.ti.com 3.3.4 Absolute Mode The absolute mode is described in Table 3-7. Table 3-7. Absolute Mode Description Assembler Code Content of ROM MOV &EDE,&TONI MOV X(0),Y(0) X = EDE Y = TONI Length: Operation: Comment: Example: MOV Two or three words Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses.
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Addressing Modes www.ti.com 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3-8. Table 3-8. Indirect Mode Description Length: Operation: Comment: Example: Assembler Code Content of ROM MOV @R10,0(R11) MOV @R10,0(R11) One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Valid only for source operand. The substitute for destination operand is 0(Rd). MOV.
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Addressing Modes www.ti.com 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3-9. Table 3-9. Indirect Autoincrement Mode Description Length: Operation: Comment: Example: Assembler Code Content of ROM MOV @R10+,0(R11) MOV @R10+,0(R11) One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11).
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Addressing Modes www.ti.com 3.3.7 Immediate Mode The immediate mode is described in Table 3-10. Table 3-10. Immediate Mode Description Assembler Code Content of ROM MOV #45h,TONI MOV @PC+,X(PC) 45 X = TONI – PC Length: Operation: Comment: Example: Two or three words It is one word less if a constant of CG1 or CG2 can be used. Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI.
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Instruction Set 3.4 www.ti.com Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction.
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Instruction Set www.ti.com 3.4.1 Double-Operand (Format I) Instructions Figure 3-9 illustrates the double-operand instruction format. 15 14 13 12 11 10 Op-code 9 8 S-Reg 7 6 Ad B/W 5 4 3 2 As 1 0 D-Reg Figure 3-9. Double Operand Instruction Format Table 3-11 lists and describes the double operand instructions. Table 3-11. Double Operand Instructions Status Bits Mnemonic S-Reg, D-Reg Operation MOV(.B) src,dst src → dst - - - - ADD(.
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Instruction Set www.ti.com 3.4.2 Single-Operand (Format II) Instructions Figure 3-10 illustrates the single-operand instruction format. 15 14 13 12 11 10 9 8 7 Op-code 6 5 B/W 4 3 2 Ad 1 0 D/S-Reg Figure 3-10. Single Operand Instruction Format Table 3-12 lists and describes the single operand instructions. Table 3-12. Single Operand Instructions Mnemonic S-Reg, D-Reg Operation RRC(.B) dst RRA(.B) dst PUSH(.B) SWPB CALL Status Bits V N Z C C → MSB →.......
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Instruction Set www.ti.com 3.4.3 Jumps Figure 3-11 shows the conditional-jump instruction format. 15 14 13 Op-code 12 11 10 9 8 C 7 6 5 4 3 2 1 0 10-Bit PC Offset Figure 3-11. Jump Instruction Format Table 3-13 lists and describes the jump instructions Table 3-13.
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Instruction Set www.ti.com 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. 3.4.4.1 Interrupt and Reset Cycles Table 3-14 lists the CPU cycles for interrupt overhead and reset. Table 3-14. Interrupt and Reset Cycles Action 3.4.4.2 No.
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Instruction Set www.ti.com 3.4.4.4 Format-I (Double Operand) Instruction Cycles and Lengths Table 3-16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3-16. Format 1 Instruction Cycles and Lengths Addressing Mode No.
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Instruction Set www.ti.com 3.4.5 Instruction Set Description The instruction map is shown in Figure 3-12 and the complete instruction set is summarized in Table 3-17. 000 0xxx 4xxx 8xxx Cxxx 1xxx 14xx 18xx 1Cxx 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx 040 080 0C0 100 RRC RRC.B SWPB RRA 140 180 RRA.B SXT 1C0 200 240 PUSH PUSH.B 280 2C0 CALL 300 340 380 3C0 V N Z C RETI JNE/JNZ JEQ/JZ JNC JC JN JGE JL JMP MOV, MOV.
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Instruction Set www.ti.com Table 3-17. MSP430 Instruction Set (continued) Mnemonic DECD(.B) (1) dst V N Z C Double-decrement destination Description dst - 2 → dst * * * * - DINT (1) Disable interrupts 0 → GIE - - - EINT (1) Enable interrupts 1 → GIE - - - - dst Increment destination dst +1 → dst * * * * dst Double-increment destination dst+2 → dst * * * * .not.dst → dst INC(.B) (1) INCD(.
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Instruction Set www.ti.com 3.4.6 Instruction Set Details 3.4.6.1 ADC *ADC[.W] Add carry to destination *ADC.B Add carry to destination Syntax ADC dst or ADC.B dst Operation dst + C → dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. Status Bit N: Set if result is negative, reset if positive ADC.
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Instruction Set www.ti.com 3.4.6.2 ADD ADD[.W] Add source to destination ADD.B Add source to destination Syntax ADD src,dst or ADD.W src,dst ADD.B src,dst Operation src + dst → dst Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost.
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Instruction Set 3.4.6.3 www.ti.com ADDC ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC src,dst or ADDC.B src,dst Operation src + dst + C → dst Description The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive ADDC.
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Instruction Set www.ti.com 3.4.6.4 AND AND[.W] Source AND destination AND.B Source AND destination Syntax AND src,dst or AND.B src,dst Operation src .AND. dst → dst Description The source operand and the destination operand are logically ANDed. The result is placed into the destination. Status Bits N: Set if result MSB is set, reset if not set AND.W src,dst Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
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Instruction Set 3.4.6.5 www.ti.com BIC BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax BIC src,dst or BIC.B src,dst Operation .NOT.src .AND. dst → dst Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The six MSBs of the RAM word LEO are cleared.
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Instruction Set www.ti.com 3.4.6.6 BIS BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax BIS src,dst or BIS.B src,dst Operation src .OR. dst → dst Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The six LSBs of the RAM word TOM are set. BIS Example BIS.
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Instruction Set 3.4.6.7 www.ti.com BIT BIT[.W] Test bits in destination BIT.B Test bits in destination Syntax BIT src,dst Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. Status Bits N: Set if MSB of result is set, reset otherwise or BIT.W src,dst Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
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Instruction Set www.ti.com 3.4.6.8 BR, BRANCH *BR, BRANCH Branch to .......... destination Syntax BR dst Operation dst → PC Emulation MOV dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status Bits Status bits are not affected. Example Examples for all addressing modes are given.
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Instruction Set 3.4.6.9 www.ti.com CALL CALL Subroutine Syntax CALL dst Operation dst → tmp dst is evaluated and stored SP - 2 → SP PC → @SP PC updated to TOS tmp → PC dst saved to PC Description A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.10 CLR *CLR[.W] Clear destination *CLR.B Clear destination Syntax CLR dst or CLR.B dst Operation 0 → dst Emulation MOV #0,dst MOV.B #0,dst Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. CLR Example ; 0 -> TONI Register R5 is cleared. CLR Example TONI CLR.W dst R5 RAM byte TONI is cleared. CLR.
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Instruction Set www.ti.com 3.4.6.11 CLRC *CLRC Clear carry bit Syntax CLRC Operation 0→C Emulation BIC #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12.
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Instruction Set www.ti.com 3.4.6.12 CLRN *CLRN Clear negative bit Syntax CLRN Operation 0→N or (.NOT.src .AND. dst → dst) Emulation BIC Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. Status Bits N: Reset to 0 #4,SR Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set www.ti.com 3.4.6.13 CLRZ *CLRZ Clear zero bit Syntax CLRZ Operation 0→Z or (.NOT.src .AND. dst → dst) Emulation BIC #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. Status Bits N: Not affected Z: Reset to 0 C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set www.ti.com 3.4.6.14 CMP CMP[.W] Compare source and destination CMP.B Compare source and destination Syntax CMP src,dst or CMP.B src,dst Operation dst + .NOT.src + 1 CMP.W src,dst or (dst - src) Description The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected.
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Instruction Set www.ti.com 3.4.6.15 DADC *DADC[.W] Add carry decimally to destination *DADC.B Add carry decimally to destination Syntax DADC dst or DADC.B dst Operation dst + C → dst (decimally) Emulation DADD #0,dst DADD.B #0,dst Description The carry bit (C) is added decimally to the destination. Status Bits N: Set if MSB is 1 DADC.
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Instruction Set www.ti.com 3.4.6.16 DADD DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD src,dst or DADD.B src,dst Operation src + dst + C → dst (decimally) Description The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C)are added decimally to the destination operand. The source operand is not affected.
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Instruction Set www.ti.com 3.4.6.17 DEC *DEC[.W] Decrement destination *DEC.B Decrement destination Syntax DEC dst or DEC.B dst Operation dst - 1 → dst Emulation SUB #1,dst SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive DEC.W dst Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
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Instruction Set www.ti.com 3.4.6.18 DECD *DECD[.W] Double-decrement destination *DECD.B Double-decrement destination Syntax DECD dst or DECD.B dst Operation dst - 2 → dst Emulation SUB #2,dst Emulation SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive DECD.
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Instruction Set www.ti.com 3.4.6.19 DINT *DINT Disable (general) interrupts Syntax DINT Operation 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst → dst) Emulation BIC #8,SR Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is reset. OSCOFF and CPUOFF are not affected.
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Instruction Set www.ti.com 3.4.6.20 EINT *EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR → SR / .src .OR. dst → dst) Emulation BIS #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. Status Bits Status bits are not affected. Mode Bits GIE is set. OSCOFF and CPUOFF are not affected. Example The general interrupt enable (GIE) bit in the status register is set.
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Instruction Set www.ti.com 3.4.6.21 INC *INC[.W] Increment destination *INC.B Increment destination Syntax INC dst or INC.B dst Operation dst + 1 → dst Emulation ADD #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive INC.
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Instruction Set www.ti.com 3.4.6.22 INCD *INCD[.W] Double-increment destination *INCD.B Double-increment destination Syntax INCD dst or INCD.B dst Operation dst + 2 → dst Emulation ADD #2,dst ADD.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive INCD.
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Instruction Set www.ti.com 3.4.6.23 INV *INV[.W] Invert destination *INV.B Invert destination Syntax INV dst INV.B dst Operation .NOT.dst → dst Emulation XOR #0FFFFh,dst XOR.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
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Instruction Set www.ti.com 3.4.6.24 JC, JHS JC Jump if carry set JHS Jump if higher or same Syntax JC label JHS label Operation If C = 1: PC + 2 offset → PC If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed.
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Instruction Set www.ti.com 3.4.6.25 JEQ, JZ JEQ, JZ Jump if equal, jump if zero Syntax JEQ label JZ label Operation If Z = 1: PC + 2 offset → PC If Z = 0: execute following instruction Description The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.26 JGE JGE Jump if greater or equal Syntax JGE label Operation If (N .XOR. V) = 0 then jump to label: PC + 2 P offset → PC If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed.
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Instruction Set www.ti.com 3.4.6.27 JL JL Jump if less Syntax JL label Operation If (N .XOR. V) = 1 then jump to label: PC + 2 offset → PC If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed.
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Instruction Set www.ti.com 3.4.6.28 JMP JMP Jump unconditionally Syntax JMP label Operation PC + 2 × offset → PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint This one-word instruction replaces the BRANCH instruction in the range of –511 to +512 words relative to the current program counter.
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Instruction Set www.ti.com 3.4.6.29 JN JN Jump if negative Syntax JN label Operation if N = 1: PC + 2 ×offset → PC if N = 0: execute following instruction Description The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.30 JNC, JLO JNC Jump if carry not set JLO Jump if lower Syntax JNC label JLO label Operation if C = 0: PC + 2 offset → PC if C = 1: execute following instruction Description The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed.
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Instruction Set www.ti.com 3.4.6.31 JNE, JNZ JNE Jump if not equal JNZ Jump if not zero Syntax JNE label JNZ label Operation If Z = 0: PC + 2 a offset → PC If Z = 1: execute following instruction Description The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.32 MOV MOV[.W] Move source to destination MOV.B Move source to destination Syntax MOV src,dst or MOV.B src,dst Operation src → dst Description The source operand is moved to the destination. MOV.W src,dst The source operand is not affected. The previous contents of the destination are lost. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF,and GIE are not affected. Example The contents of table EDE (word data) are copied to table TOM.
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Instruction Set www.ti.com 3.4.6.33 NOP *NOP No operation Syntax NOP Operation None Emulation MOV #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.34 POP *POP[.W] Pop word from stack to destination *POP.B Pop byte from stack to destination Syntax POP dst POP.B dst Operation @SP → temp SP + 2 → SP temp → dst Emulation MOV @SP+,dst or MOV.W @SP+,dst MOV.B @SP+,dst Description The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.35 PUSH PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH src or PUSH.B src Operation SP - 2 → SP PUSH.W src src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example The contents of the status register and R8 are saved on the stack.
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Instruction Set www.ti.com 3.4.6.36 RET *RET Return from subroutine Syntax RET Operation @SP → PC SP + 2 → SP Emulation MOV @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status Bits Status bits are not affected.
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Instruction Set www.ti.com 3.4.6.37 RETI RETI Return from interrupt Syntax RETI Operation TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. Description The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow.
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Instruction Set www.ti.com 3.4.6.38 RLA *RLA[.W] Rotate left arithmetically *RLA.B Rotate left arithmetically Syntax RLA dst or RLA.W dst RLA.B dst Operation C <- MSB <- MSB-1 .... LSB+1 <- LSB <- 0 Emulation ADD dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 3-15. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2.
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Instruction Set www.ti.com 3.4.6.39 RLC *RLC[.W] Rotate left through carry *RLC.B Rotate left through carry Syntax RLC dst or RLC.W dst RLC.B dst Operation C <- MSB <- MSB-1 .... LSB+1 <- LSB <- C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3-16. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). Word 15 0 7 0 C Byte Figure 3-16.
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Instruction Set www.ti.com 3.4.6.40 RRA RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA dst or RRA.B dst Operation MSB → MSB, MSB → MSB-1, ... LSB+1 → LSB, LSB → C Description The destination operand is shifted right one position as shown in Figure 3-17. The MSB is shifted into the MSB, the MSB is shifted into the MSB-1, and the LSB+1 is shifted into the LSB. Word RRA.W dst 15 0 7 0 C Byte Figure 3-17.
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Instruction Set www.ti.com 3.4.6.41 RRC RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC dst RRC dst Operation C → MSB → MSB-1 .... LSB+1 → LSB → C Description The destination operand is shifted right one position as shown in Figure 3-18. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). Word or RRC.W dst 15 0 7 0 C Byte Figure 3-18.
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Instruction Set www.ti.com 3.4.6.42 SBC *SBC[.W] Subtract source and borrow/.NOT. carry from destination *SBC.B Subtract source and borrow/.NOT. carry from destination Syntax SBC dst or SBC.B dst Operation dst + 0FFFFh + C → dst SBC.W dst dst + 0FFh + C → dst Emulation SUBC #0,dst SUBC.B #0,dst Description The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost.
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Instruction Set www.ti.com 3.4.6.43 SETC *SETC Set carry bit Syntax SETC Operation 1→C Emulation BIS #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set www.ti.com 3.4.6.44 SETN *SETN Set negative bit Syntax SETN Operation 1→N Emulation BIS #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set www.ti.com 3.4.6.45 SETZ *SETZ Set zero bit Syntax SETZ Operation 1→Z Emulation BIS #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits 108 CPU OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set www.ti.com 3.4.6.46 SUB SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax SUB src,dst or SUB.B src,dst Operation dst + .NOT.src + 1 → dst SUB.W src,dst or [(dst - src → dst)] Description The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost.
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Instruction Set www.ti.com 3.4.6.47 SUBC, SBB SUBC[.W], SBB[.W] Subtract source and borrow/.NOT. carry from destination SUBC.B, SBB.B Subtract source and borrow/.NOT. carry from destination Syntax SUBC SBB SUBC.B Operation dst + .NOT.src + C → dst src,dst src,dst src,dst or or or SUBC.W SBB.W SBB.
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Instruction Set www.ti.com 3.4.6.48 SWPB SWPB Swap bytes Syntax SWPB dst Operation Bits 15 to 8 ↔ bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3-19. Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 15 8 7 0 Figure 3-19. Destination Operand - Byte Swap Example MOV SWPB Example The value in R5 is multiplied by 256. The result is stored in R5,R4.
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Instruction Set www.ti.com 3.4.6.49 SXT SXT Extend Sign Syntax SXT dst Operation Bit 7 → Bit 8 ......... Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3-20. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT. Zero) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 15 8 7 0 Figure 3-20.
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Instruction Set www.ti.com 3.4.6.50 TST *TST[.W] Test destination *TST.B Test destination Syntax TST dst or TST.B dst Operation dst + 0FFFFh + 1 TST.W dst dst + 0FFh + 1 Emulation CMP #0,dst CMP.B #0,dst Description The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected.
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Instruction Set www.ti.com 3.4.6.51 XOR XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax XOR src,dst or XOR.B src,dst Operation src .XOR. dst → dst Description The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. Status Bits N: Set if result MSB is set, reset if not set XOR.
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Chapter 4 SLAU144J – December 2004 – Revised July 2013 CPUX This chapter describes the extended MSP430X 16-bit RISC CPU with 1-MB memory access, its addressing modes, and instruction set. The MSP430X CPU is implemented in all MSP430 devices that exceed 64-KB of address space. Topic ........................................................................................................................... 4.1 4.2 4.3 4.4 4.5 4.6 CPU Introduction ............................................................
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CPU Introduction 4.1 www.ti.com CPU Introduction The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The MSP430X CPU can address a 1-MB address range without paging. In addition, the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU, while maintaining the same or better code density than the MSP430 CPU.
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CPU Introduction www.ti.
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Interrupts 4.2 www.ti.com Interrupts The MSP430X uses the same interrupt structure as the MSP430: • Vectored interrupts with no polling necessary • Interrupt vectors are located downward from address 0FFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets, Interrupts, and Operating modes, Section 2 Interrupts. The interrupt vectors contain 16-bit addresses that point into the lower 64-KB memory.
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CPU Registers www.ti.com 4.3 CPU Registers The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated functions. Registers R4 through R15 are working registers for general use. 4.3.1 Program Counter (PC) The 20-bit PC (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly.
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CPU Registers www.ti.com Figure 4-6 shows the stack usage. Figure 4-7 shows the stack usage when 20-bit address words are pushed. 19 1 Stack Pointer Bits 19 to 1 MOV.W MOV.W PUSH POP 2(SP),R6 R7,0(SP) #0123h R8 ; ; ; ; 0 0 Copy Item I2 to R6 Overwrite TOS with R7 Put 0123h on stack R8 = 0123h Figure 4-5. Stack Pointer Address I1 0xxxh 0xxxh - 2 I2 0xxxh - 4 I3 SP PUSH #0123h POP R8 I1 I1 I2 I2 I3 I3 SP 0123h 0xxxh - 6 SP 0xxxh - 8 Figure 4-6. Stack Usage SPold Item n-1 Item.
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CPU Registers www.ti.com 4.3.3 Status Register (SR) The 16-bit SR (SR/R2), used as a source or destination register, can only be used in register mode addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 4-9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable operation can result. 15 9 Reserved 8 V 7 0 SCG1 OSC CPU SCG0 GIE OFF OFF N Z C rw-0 Figure 4-9. SR Bits Table 4-1 describes the SR bits.
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CPU Registers www.ti.com 4.3.4 Constant Generator Registers (CG1 and CG2) Six commonly-used constants are generated with the constant generator registers R2 (CG1) and R3 (CG2), without requiring an additional 16-bit word of program code. The constants are selected with the source register addressing modes (As), as described in Table 4-2. Table 4-2.
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CPU Registers www.ti.com 4.3.5 General-Purpose Registers (R4 to R15) The 12 CPU registers (R4 to R15) contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction. The SXT instruction extends the sign through the complete 20-bit register. The following figures show the handling of byte, word, and address-word data.
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CPU Registers www.ti.com Word-Register Operation High Byte Low Byte Memory 19 16 15 Unused 87 0 Register Operation Register 0 Figure 4-12. Word-Register Operation Figure 4-13 and Figure 4-14 show 20-bit address-word handling (.A suffix). The handling is shown for a source register and a destination memory address-word and for a source memory address-word and a destination register.
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Addressing Modes www.ti.com Address-Word - Register Operation High Byte Low Byte 19 16 15 0 87 Memory +2 Unused Memory Register Operation Register Figure 4-14. Address-Word – Register Operation 4.4 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand use 16-bit or 20-bit addresses (see Table 4-3). The MSP430 and MSP430X instructions are usable throughout the entire 1MB memory range. Table 4-3.
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Addressing Modes www.ti.com 4.4.1 Register Mode Operation: Length: Comment: Byte operation: Word operation: Address-word operation: SXT exception: Example: The operand is the 8-, 16-, or 20-bit content of the used CPU register. One, two, or three words Valid for source and destination Byte operation reads only the eight least significant bits (LSBs) of the source register Rsrc and writes the result to the eight LSBs of the destination register Rdst. The bits Rdst.19:8 are cleared.
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Addressing Modes www.ti.com 4.4.2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register. The Indexed mode has three addressing possibilities: • Indexed mode in lower 64-KB memory • MSP430 instruction with Indexed mode addressing memory above the lower 64-KB memory • MSP430X instruction with Indexed mode 4.4.2.
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Addressing Modes www.ti.com Before: After: Address Space 4.4.2.
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Addressing Modes www.ti.com Rn.19:0 Rn.19:0 10000 0,FFFF Lower 64 KB Rn.19:0 Rn.19:0 ±32 KB ±32 KB FFFFF 0000C Figure 4-17. Overflow and Underflow for Indexed Mode Length: Operation: Comment: Example: Source: Destination: Two or three words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh.
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Addressing Modes www.ti.com Before: After: Address Space 4.4.2.
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Addressing Modes www.ti.com The extension word contains the MSBs of the source index and of the destination index and the A/L bit for 20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01.
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Addressing Modes www.ti.com Lower 64 KB PC.19:16 = 0 19 16 15 FFFFF 0 Program counter PC 0 10000 0FFFF PC.19:0 Lower 64 KB S 00000 16-bit byte index 16-bit signed PC index 16-bit signed add 0 Memory address Figure 4-18. Symbolic Mode Running in Lower 64KB Operation: Length: Comment: Example: Source: Destination: 132 CPUX The signed 16-bit index in the next word after the instruction is added temporarily to the PC.
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Addressing Modes www.ti.com Before: After: Address Space 4.4.3.
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Addressing Modes www.ti.com PC.19:0 PC.19:0 ±32 KB ±32 KB FFFFF PC.19:0 Lower 64 KB 10000 0FFFF PC.19:0 0000C Figure 4-20. Overflow and Underflow for Symbolic Mode Length: Operation: Comment: Example: ADD.W EDE,&TONI ; Source: This instruction adds the 16-bit data contained in source word EDE and destination word TONI and places the 16-bit result into the destination word TONI. For this example, the instruction is located at address 2F034h.
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Addressing Modes www.ti.com Before: After: Address Space 4.4.3.
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Addressing Modes www.ti.com Before: Address Space After: Address Space 2103Ah xxxxh 2103Ah xxxxh 21038h 6740h 21038h 6740h 21036h 4766h 21036h 4766h 21034h 50D0h 21034h 50D0h 21032h 18C5h 21032h 18C5h 7777Ah xxxxh 7777Ah xxxxh 77778h xx45h 21038h +56740h 77778h 77778h xx77h 3579Eh xxxxh 3579Eh xxxxh 3579Ch xx32h 21036h +14766h 3579Ch 3579Ch xx32h PC PC 32h +45h 77h src dst Sum 4.4.
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Addressing Modes www.ti.com Before: Address Space Address Space xxxxh xxxxh 2103Ah 21038h 7778h 21038h 7778h 2103Ah 4.4.4.
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Addressing Modes www.ti.com Before: After: Address Space Address Space 2103Ah xxxxh 2103Ah xxxxh 21038h 7778h 21038h 7778h 21036h 579Ch 21036h 579Ch 21034h 52D2h 21034h 52D2h 21032h 1987h 21032h 1987h 7777Ah 0001h 7777Ah 0007h 77778h 2345h 77778h 7777h 3579Eh 0006h 3579Eh 0006h 3579Ch 5432h 3579Ch 5432h PC PC 65432h +12345h 77777h src dst Sum 4.4.5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand.
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Addressing Modes www.ti.com Before: After: Address Space Register Address Space Register 21038h xxxxh R5 3579Ch 21038h xxxxh PC R5 3579Ch 21036h 2100h R6 45678h 21036h 2100h R6 45678h 21034h 55A6h 21034h 55A6h 4777Ah xxxxh 4777Ah xxxxh 47778h 2345h 47778h 7777h 3579Eh xxxxh 3579Eh xxxxh 3579Ch 5432h 3579Ch 5432h PC 45678h +02100h 47778h R5 5432h +2345h 7777h src dst Sum R5 4.4.
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Addressing Modes www.ti.com Before: After: Address Space Register Address Space Register 21038h xxxxh R5 3579Ch 21038h xxxxh PC R5 3579Dh 21036h 0000h R6 00778h 21036h 0000h R6 00778h 21034h 55F6h 21034h 55F6h 0077Ah xxxxh 0077Ah xxxxh 00778h xx45h 00778h xx77h 3579Dh xxh 3579Dh xxh 3579Ch 32h 3579Ch xx32h PC 00778h +0000h 00778h R5 32h +45h 77h src dst Sum R5 4.4.
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Addressing Modes www.ti.com Before: After: Address Space 4.4.7.2 Address Space 2103Ah xxxxh 2103Ah xxxxh 21038h 0778h 21038h 0778h 21036h 3456h 21036h 3456h 21034h 50B2h 21034h 50B2h 0077Ah xxxxh 0077Ah xxxxh 00778h 2345h 00778h 579Bh PC PC 3456h +2345h 579Bh src dst Sum MSP430X Instructions With Immediate Mode If an MSP430X instruction is used with Immediate addressing mode, the constant is a 20-bit value.
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MSP430 and MSP430X Instructions 4.5 www.ti.com MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are used throughout the 1MB memory range unless their 16-bit capability is exceeded. The MSP430X instructions are used when the addressing of the operands, or the data length exceeds the 16-bit capability of the MSP430 instructions.
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MSP430 and MSP430X Instructions www.ti.com Table 4-4. MSP430 Double-Operand Instructions (1) 4.5.1.2 Status Bits (1) Mnemonic S-Reg, DReg V N Z C MOV(.B) src,dst src → dst - - - - Operation ADD(.B) src,dst src + dst → dst * * * * ADDC(.B) src,dst src + dst + C → dst * * * * SUB(.B) src,dst dst + .not.src + 1 → dst * * * * SUBC(.B) src,dst dst + .not.src + C → dst * * * * CMP(.B) src,dst dst → src * * * * DADD(.
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MSP430 and MSP430X Instructions 4.5.1.3 www.ti.com Jump Instructions Figure 4-23 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit PC. This allows jumps in a range of –511 to +512 words relative to the PC in the full 20-bit address space. Jumps do not affect the status bits. Table 4-6 lists and describes the eight jump instructions.
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MSP430 and MSP430X Instructions www.ti.com Table 4-7. Emulated Instructions (continued) Instruction 4.5.1.5 Explanation Status Bits Emulation V N (1) Z C INV(.B) dst Invert dst XOR(.B) #–1,dst * * * * NOP No operation MOV R3,R3 – – – – POP dst Pop operand from stack MOV @SP+,dst – – – – RET Return from subroutine MOV @SP+,PC – – – – RLA(.B) dst Shift left dst arithmetically ADD(.B) dst,dst * * * * RLC(.B) dst Shift left dst logically through Carry ADDC(.
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MSP430 and MSP430X Instructions www.ti.com Table 4-9. MSP430 Format II Instruction Cycles and Length (continued) No. of Cycles Addressing Mode RRA, RRC SWPB, SXT #N PUSH N/A X(Rn) 4 EDE 4 &EDE 4 3 (1) 4 (2) 4 (2) 4 (2) CALL Length of Instruction Example 4 (2) 2 CALL #LABEL 4 (2) 2 CALL 2(R7) 4 (2) 2 PUSH EDE 4 (2) 2 SXT &EDE 4.5.1.5.
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MSP430 and MSP430X Instructions www.ti.com Table 4-10. MSP430 Format I Instructions Cycles and Length (continued) Addressing Mode Src No. of Cycles Length of Instruction Rm 3 2 AND EDE,R6 PC 3 2 BR EDE TONI 6 (1) 3 CMP EDE,TONI x(Rm) 6 (1) 3 MOV EDE,0(SP) &TONI (1) Dst EDE &EDE 6 Example 3 MOV EDE,&TONI Rm 3 2 MOV &EDE,R8 PC 3 2 BR &EDE TONI 6 (1) 3 MOV &EDE,TONI x(Rm) 6 (1) 3 MOV &EDE,0(SP) &TONI 6 (1) 3 MOV &EDE,&TONI 4.5.
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MSP430 and MSP430X Instructions www.ti.com Table 4-11. Description of the Extension Word Bits for Register Mode (continued) 148 Bit Description A/L Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address word 1 0 16-bit word 1 1 8-bit byte 5:4 Reserved 3:0 Repetition count CPUX #=0 These four bits set the repetition count n.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.2 Non-Register Mode Extension Word The extension word for non-register modes is shown in Figure 4-25 and described in Table 4-12. An example is shown in Figure 4-27. 15 0 0 0 12 11 1 1 10 7 Source bits 19:16 6 5 4 A/L 0 0 3 0 Destination bits 19:16 Figure 4-25. Extension Word for Non-Register Modes Table 4-12. Description of Extension Word Bits for Non-Register Modes Bit Description 15:11 Extension word op-code.
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MSP430 and MSP430X Instructions www.ti.com 15 14 13 12 11 0 0 0 1 1 Op-code XORX.A 10 9 00 8 7 6 5 ZC # A/L 3 2 1 Rsvd (n-1)/Rn As Rdst Ad B/W Rsrc 4 0 R9,R8 1: Repetition count in bits 3:0 0: Use Carry 0 0 0 1 1 0 14(XOR) 01:Address word 0 9 XORX instruction 0 0 0 0 0 1 0 8(R8) Destination R8 Source R9 Destination register mode Source register mode Figure 4-26.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.3 Extended Double-Operand (Format I) Instructions All 12 double-operand instructions have extended versions as listed in Table 4-13. Table 4-13. Extended Double-Operand Instructions Mnemonic Operands Operation Status Bits (1) V N Z C src → dst – – – – src + dst → dst * * * * src,dst src + dst + C → dst * * * * src,dst dst + .not.src + 1 → dst * * * * SUBCX(.B,.A) src,dst dst + .not.src + C → dst * * * * CMPX(.B,.
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MSP430 and MSP430X Instructions www.ti.com The four possible addressing combinations for the extension word for Format I instructions are shown in Figure 4-28. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn 0 B/W 0 0 dst A/L 0 0 src Op-code 0 0 0 1 1 src.19:16 Op-code Ad B/W src 3 0 0 0 0 0 dst As src.15:0 0 0 0 1 1 0 0 0 src Op-code 0 A/L 0 Ad B/W dst.19:16 0 As dst dst.15:0 0 0 0 1 1 src.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.4 Extended Single-Operand (Format II) Instructions Extended MSP430X Format II instructions are listed in Table 4-14. Table 4-14. Extended Single-Operand Instructions Mnemonic Operands Status Bits Operation n (1) V N Z C – – – – 1 to 16 – – – – Pop n 16-bit registers from stack 1 to 16 – – – – Push n 20-bit registers to stack 1 to 16 – – – – #n,Rsrc Push n 16-bit registers to stack 1 to 16 – – – – PUSHX(.B,.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.4.1 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown in Figure 4-31 through Figure 4-34. 15 8 7 Op-code 4 3 n-1 0 Rdst - n+1 Figure 4-31. PUSHM/POPM Instruction Format 15 12 C 11 10 9 4 n-1 3 Op-code 0 Rdst Figure 4-32.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.5 Extended Emulated Instructions The extended instructions together with the constant generator form the extended emulated instructions. Table 4-15 lists the emulated instructions. Table 4-15. Extended Emulated Instructions Instruction Explanation Emulation ADCX(.B,.A) dst Add carry to dst ADDCX(.B,.A) #0,dst BRA Branch indirect dst MOVA Return from subroutine MOVA Clear Rdst MOV CLRX(.B,.A) dst Clear dst MOVX(.B,.A) #0,dst DADCX(.B,.
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MSP430 and MSP430X Instructions 4.5.2.6 www.ti.com MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction as listed in Table 4-16. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.7 MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used, not the instruction itself. The number of clock cycles refers to MCLK. 4.5.2.7.1 MSP430X Format II (Single-Operand) Instruction Cycles and Lengths Table 4-17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended singleoperand instructions. Table 4-17.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.7.2 MSP430X Format I (Double-Operand) Instruction Cycles and Lengths Table 4-18 lists the length and CPU cycles for all addressing modes of the MSP430X extended Format I instructions. Table 4-18. MSP430X Format I Instruction Cycles and Length Addressing Mode No. of Cycles Destination .B/.W .A .B/.W/.A Rn Rm (1) 2 2 2 BITX.B R5,R8 PC 3 3 2 ADDX R9,PC (3) @Rn 3 ANDX.A R5,4(R6) 5 (2) 7 (3) 3 XORX R8,EDE &EDE 5 (2) 7 (3) 3 BITX.
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MSP430 and MSP430X Instructions www.ti.com 4.5.2.7.3 MSP430X Address Instruction Cycles and Lengths Table 4-19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions. Table 4-19.
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Instruction Set Description 4.6 www.ti.com Instruction Set Description Table 4-20 shows all available instructions: Table 4-20. Instruction Map of MSP430X 000 040 080 0xxx 10xx 14xx 18xx 1Cxx 160 0C0 100 140 180 1C0 200 RRC RRC.B SWPB RRA RRA.B SXT PUSH 280 2C0 300 340 RETI CALL A 380 3C0 PUSH. B CALL PUSHM.A, POPM.A, PUSHM.W, POPM.
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Instruction Set Description www.ti.com 4.6.1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown in the following tables. Instruction Group Instruction 15 MOVA Instruction Identifier src or data.19:16 12 11 8 7 dst 4 3 0 src 0 0 0 0 dst MOVA @Rsrc,Rdst 0 src 0 0 0 1 dst MOVA @Rsrc+,Rdst 0 &abs.19:16 0 0 1 0 dst MOVA &abs20,Rdst 0 0 src 0 1 1 dst MOVA x(Rsrc),Rdst 0 0 src 1 1 0 &abs.
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Instruction Set Description Instruction www.ti.com Instruction Identifier 15 dst 12 11 8 7 6 5 4 3 RETI 0 0 0 1 0 0 1 1 0 0 0 0 0 0 CALLA 0 0 0 1 0 0 1 1 0 1 0 0 dst CALLA Rdst 0 0 0 1 0 0 1 1 0 1 0 1 dst CALLA x(Rdst) 0 0 0 x.15:0 0 0 0 1 0 0 1 1 0 1 1 0 dst CALLA @Rdst 0 0 0 1 0 0 1 1 0 1 1 1 dst CALLA @Rdst+ 0 0 0 1 0 0 1 1 1 0 0 0 &abs.19:16 CALLA &abs20 0 0 1 x.19:16 &abs.
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Instruction Set Description www.ti.com 4.6.2 MSP430 Instructions The MSP430 instructions are described in the following sections. See Section 4.6.3 for MSP430X extended instructions and Section 4.6.4 for MSP430X address instructions.
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Instruction Set Description 4.6.2.1 www.ti.com ADC * ADC[.W] * ADC.B Syntax Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst Operation Emulation dst + C → dst ADDC #0,dst ADDC.B #0,dst Description Status Bits Mode Bits Example ADD ADC Example ADD.B ADC.B 164 CPUX The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
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Instruction Set Description www.ti.com 4.6.2.2 ADD ADD[.W] ADD.B Syntax Add source word to destination word Add source byte to destination byte ADD src,dst or ADD.W src,dst ADD.B src,dst Operation Description Status Bits Mode Bits Example ADD.W Example ADD.W JC ... Example ADD.B JNC ... src + dst → dst The source operand is added to the destination operand. The previous content of the destination is lost.
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Instruction Set Description 4.6.2.3 www.ti.com ADDC ADDC[.W] ADDC.B Syntax Add source word and carry to destination word Add source byte and carry to destination byte ADDC src,dst or ADDC.W src,dst ADDC.B src,dst Operation Description Status Bits Mode Bits Example ADDC.W Example ADDC.W JC ... Example ADDC.B JNC ... 166 CPUX src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous content of the destination is lost.
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Instruction Set Description www.ti.com 4.6.2.4 AND AND[.W] AND.B Syntax Logical AND of source word with destination word Logical AND of source byte with destination byte AND src,dst or AND.W src,dst AND.B src,dst Operation Description Status Bits Mode Bits Example MOV AND JZ ... src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
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Instruction Set Description 4.6.2.5 www.ti.com BIC BIC[.W] BIC.B Syntax Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC src,dst or BIC.W src,dst BIC.B src,dst Operation Description Status Bits Mode Bits Example BIC Example BIC.W Example BIC.B 168 CPUX (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
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Instruction Set Description www.ti.com 4.6.2.6 BIS BIS[.W] BIS.B Syntax Set bits set in source word in destination word Set bits set in source byte in destination byte BIS src,dst or BIS.W src,dst BIS.B src,dst Operation Description Status Bits Mode Bits Example BIS Example BIS.W Example BIS.B src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected.
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Instruction Set Description 4.6.2.7 www.ti.com BIT BIT[.W] BIT.B Syntax Test bits set in source word in destination word Test bits set in source byte in destination byte BIT src,dst or BIT.W src,dst BIT.B src,dst Operation Description Status Bits Mode Bits Example BIT JNZ ... Example BIT.W JC ... Example BIT.B JNC ... 170 CPUX src .and. dst The source operand and the destination operand are logically ANDed. The result affects only the status bits in SR. Register mode: the register bits Rdst.
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Instruction Set Description www.ti.com 4.6.2.8 BR, BRANCH * BR, BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination in lower 64K address space BR dst dst → PC MOV dst,PC An unconditional branch is taken to an address anywhere in the lower 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given.
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Instruction Set Description 4.6.2.9 www.ti.com CALL CALL Syntax Operation Description Status Bits Mode Bits Examples CALL CALL Call a subroutine in lower 64KB CALL dst dst → PC 16-bit dst is evaluated and stored SP – 2 → SP PC → @SP updated PC with return address to TOS tmp → PC saved 16-bit dst to PC A subroutine call is made from an address in the lower 64KB to a subroutine address in the lower 64KB. All seven source addressing modes can be used. The call instruction is a word instruction.
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Instruction Set Description www.ti.com 4.6.2.10 CLR * CLR[.W] * CLR.B Syntax Clear destination Clear destination CLR dst or CLR.W dst CLR.B dst Operation 0 → dst Emulation MOV #0,dst MOV.B #0,dst Description Status Bits Example CLR Example CLR Example CLR.B The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. TONI ; 0 -> TONI Register R5 is cleared. R5 RAM byte TONI is cleared.
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Instruction Set Description www.ti.com 4.6.2.11 CLRC * CLRC Syntax Operation Clear carry bit Emulation Description Status Bits BIC #1,SR Mode Bits Example CLRC DADD DADC 174 CPUX CLRC 0→C The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12.
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Instruction Set Description www.ti.com 4.6.2.12 CLRN * CLRN Syntax Operation Clear negative bit Emulation Description BIC #4,SR Status Bits Mode Bits Example SUBR SUBRET CLRN 0→N or (.NOT.src .AND. dst → dst) The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction.
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Instruction Set Description www.ti.com 4.6.2.13 CLRZ * CLRZ Syntax Operation Clear zero bit Emulation Description BIC #2,SR Status Bits Mode Bits Example CLRZ 0→Z or (.NOT.src .AND. dst → dst) The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set Description www.ti.com 4.6.2.14 CMP CMP[.W] CMP.B Syntax Compare source word and destination word Compare source byte and destination byte CMP src,dst or CMP.W src,dst CMP.B src,dst Operation (.not.src) + 1 + dst or dst – src Emulation Description BIC #2,SR Status Bits Mode Bits Example CMP JEQ ... Example CMP.W JL ... Example CMP.B JEQ ... The source operand is subtracted from the destination operand.
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Instruction Set Description www.ti.com 4.6.2.15 DADC * DADC[.W] * DADC.B Syntax Add carry decimally to destination Add carry decimally to destination DADC dst or DADC.W dst DADC.B dst Operation Emulation dst + C → dst (decimally) Description Status Bits The N: Z: C: Mode Bits Example DADD #0,dst DADD.B #0,dst carry bit (C) is added decimally to the destination.
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Instruction Set Description www.ti.com 4.6.2.16 DADD * DADD[.W] * DADD.B Syntax Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src,dst or DADD.W src,dst DADD.B src,dst Operation Description Status Bits Mode Bits Example DADD Example CLRC DADD.W DADD.W JC ... Example CLRC DADD.B src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B) or four (.
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Instruction Set Description www.ti.com 4.6.2.17 DEC * DEC[.W] * DEC.B Syntax Decrement destination Decrement destination DEC dst or DEC.W dst DEC.B dst Operation Emulation dst – 1 → dst SUB #1,dst SUB.B #1,dst Description Status Bits Mode Bits Example The N: Z: C: V: destination operand is decremented by one. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.2.18 DECD * DECD[.W] * DECD.B Syntax Double-decrement destination Double-decrement destination DECD dst or DECD.W dst DECD.B dst Operation Emulation dst – 2 → dst SUB #2,dst SUB.B #2,dst Description Status Bits Mode Bits Example The N: Z: C: V: destination operand is decremented by two. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.2.19 DINT * DINT Syntax Operation Disable (general) interrupts Emulation Description BIC #8,SR DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT. src .AND. dst → dst) Status Bits Mode Bits Example DINT NOP MOV MOV EINT All interrupts are disabled. The constant 08h is inverted and logically ANDed with the SR. The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected.
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Instruction Set Description www.ti.com 4.6.2.20 EINT * EINT Syntax Operation Enable (general) interrupts Emulation Description BIS #8,SR EINT 1 → GIE or (0008h .OR. SR → SR / .src .OR. dst → dst) Status Bits Mode Bits Example All interrupts are enabled. The constant #08h and the SR are logically ORed. The result is placed into the SR. Status bits are not affected. GIE is set. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the SR is set.
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Instruction Set Description www.ti.com 4.6.2.21 INC * INC[.W] * INC.B Syntax Increment destination Increment destination INC dst or INC.W dst INC.B dst Operation Emulation Description Status Bits Mode Bits Example INC.B CMP.B JEQ 184 CPUX dst + 1 → dst ADD #1,dst The destination operand is incremented by one. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.2.22 INCD * INCD[.W] * INCD.B Syntax Double-increment destination Double-increment destination INCD dst or INCD.W dst INCD.B dst Operation Emulation dst + 2 → dst ADD #2,dst ADD.B #2,dst Description Status Bits Mode Bits Example The destination operand is incremented by two. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.2.23 INV * INV[.W] * INV.B Syntax Invert destination Invert destination INV dst or INV.W dst INV.B dst Operation Emulation .not.dst → dst XOR #0FFFFh,dst XOR.B #0FFh,dst Description Status Bits Mode Bits Example MOV INV INC Example MOV.B INV.B INC.B 186 CPUX The destination operand is inverted. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.2.24 JC, JHS JC JHS Syntax Jump if carry Jump if higher or same (unsigned) JC label JHS label Operation If C = 1: PC + (2 × Offset) → PC If C = 0: execute the following instruction Description The carry bit C in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range.
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Instruction Set Description www.ti.com 4.6.2.25 JEQ, JZ JEQ JZ Syntax Jump if equal Jump if zero JEQ label JZ label Operation If Z = 1: PC + (2 × Offset) → PC If Z = 0: execute following instruction Description The zero bit Z in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range.
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Instruction Set Description www.ti.com 4.6.2.26 JGE JGE Syntax Operation Jump if greater or equal (signed) Description The negative bit N and the overflow bit V in the SR are tested. If both bits are set or both are reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range -511 to +512 words relative to the PC in full Memory range. If only one bit is set, the instruction after the jump is executed.
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Instruction Set Description www.ti.com 4.6.2.27 JL JL Syntax Operation Jump if less (signed) Description The negative bit N and the overflow bit V in the SR are tested. If only one is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in full memory range. If both bits N and V are set or both are reset, the instruction after the jump is executed.
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Instruction Set Description www.ti.com 4.6.2.28 JMP JMP Syntax Operation Description Status Bits Mode Bits Example MOV.B JMP Example ADD RETI JMP JMP RETI Jump unconditionally JMP label PC + (2 × Offset) → PC The signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means an unconditional jump in the range –511 to +512 words relative to the PC in the full memory.
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Instruction Set Description www.ti.com 4.6.2.29 JN JN Syntax Operation Description Status Bits Mode Bits Example TST.B JN ... Example SUB JN ... Example SUBA JN ... 192 CPUX Jump if negative JN label If N = 1: PC + (2 × Offset) → PC If N = 0: execute following instruction The negative bit N in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program PC.
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Instruction Set Description www.ti.com 4.6.2.30 JNC, JLO JNC JLO Syntax Jump if no carry Jump if lower (unsigned) JNC label JLO label Operation If C = 0: PC + (2 × Offset) → PC If C = 1: execute following instruction Description The carry bit C in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range.
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Instruction Set Description www.ti.com 4.6.2.31 JNZ, JNE JNZ JNE Syntax Jump if not zero Jump if not equal JNZ label JNE label Operation If Z = 0: PC + (2 × Offset) → PC If Z = 1: execute following instruction Description The zero bit Z in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range.
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Instruction Set Description www.ti.com 4.6.2.32 MOV MOV[.W] MOV.B Syntax Move source word to destination word Move source byte to destination byte MOV src,dst or MOV.W src,dst MOV.B src,dst Operation Description Status Bits Mode Bits Example MOV Example Loop Example Loop src → dst The source operand is copied to the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set Description www.ti.com 4.6.2.33 NOP * NOP Syntax Operation Emulation Description Status Bits 196 CPUX No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected.
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Instruction Set Description www.ti.com 4.6.2.34 POP * POP[.W] * POP.B Syntax Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst Operation @SP → temp SP + 2 → SP temp → dst Emulation MOV @SP+,dst or MOV.W @SP+,dst MOV.B @SP+,dst Description The stack location pointed to by the SP (TOS) is moved to the destination. The SP is incremented by two afterwards. Status bits are not affected. The contents of R7 and the SR are restored from the stack.
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Instruction Set Description www.ti.com 4.6.2.35 PUSH PUSH[.W] PUSH.B Syntax Save a word on the stack Save a byte on the stack PUSH dst or PUSH.W dst PUSH.B dst Operation Description Status Bits Mode Bits Example PUSH PUSH Example PUSH.B PUSH.B 198 CPUX SP – 2 → SP dst → @SP The 20-bit SP SP is decremented by two. The operand is then copied to the RAM word addressed by the SP. A pushed byte is stored in the low byte; the high byte is not affected. Status bits are not affected.
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Instruction Set Description www.ti.com 4.6.2.36 RET RET Syntax Operation Description Status Bits Mode Bits Example SUBR Return from subroutine RET @SP →PC.15:0 Saved PC to PC.15:0. PC.19:16 ← 0 SP + 2 → SP The 16-bit return address (lower 64KB), pushed onto the stack by a CALL instruction is restored to the PC. The program continues at the address following the subroutine call. The four MSBs of the PC.19:16 are cleared. Status bits are not affected. PC.
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Instruction Set Description www.ti.com 4.6.2.37 RETI RETI Syntax Operation Description Status Bits Mode Bits Example INTRPT 200 CPUX Return from interrupt RETI @SP → SR.15:0 SP + 2 → SP @SP → PC.15:0 SP + 2 → SP Restore saved SR with PC.19:16 Restore saved PC.15:0 Housekeeping The SR is restored to the value at the beginning of the interrupt service routine. This includes the four MSBs of the PC.19:16. The SP is incremented by two afterward. The 20-bit PC is restored from PC.
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Instruction Set Description www.ti.com 4.6.2.38 RLA * RLA[.W] * RLA.B Syntax Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst Operation Emulation C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 Description The destination operand is shifted left one position as shown in Figure 4-37. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2.
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Instruction Set Description www.ti.com 4.6.2.39 RLC * RLC[.W] * RLC.B Syntax Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C Operation Emulation Description ADDC dst,dst The destination operand is shifted left one position as shown in Figure 4-38. The carry bit (C) is shifted into the LSB, and the MSB is shifted into the carry bit (C). Word 15 0 7 0 C Byte Figure 4-38.
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Instruction Set Description www.ti.com 4.6.2.40 RRA RRA[.W] RRA.B Syntax Operation Description Rotate right arithmetically destination word Rotate right arithmetically destination byte RRA.B dst or RRA.W dst MSB → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one bit position as shown in Figure 4-39. The MSB retains its value (sign). RRA operates equal to a signed division by 2. The MSB is retained and shifted into the MSB–1.
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Instruction Set Description www.ti.com 4.6.2.41 RRC RRC[.W] RRC.B Syntax Rotate right through carry destination word Rotate right through carry destination byte RRC dst or RRC.W dst RRC.B dst C → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right by one bit position as shown in Figure 4-40. The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C.
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Instruction Set Description www.ti.com 4.6.2.42 SBC * SBC[.W] * SBC.B Syntax Subtract borrow (.NOT. carry) from destination Subtract borrow (.NOT. carry) from destination SBC dst or SBC.W dst SBC.B dst Operation dst + 0FFFFh + C → dst dst + 0FFh + C → dst Emulation SUBC #0,dst SUBC.
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Instruction Set Description www.ti.com 4.6.2.43 SETC * SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB 206 CPUX Set carry bit SETC 1→C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally. Assume that R5 = 03987h and R6 = 04137h.
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Instruction Set Description www.ti.com 4.6.2.44 SETN * SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1→N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set Description www.ti.com 4.6.2.45 SETZ * SETZ Syntax Operation Emulation Description Status Bits Mode Bits 208 CPUX Set zero bit SETZ 1→N BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set Description www.ti.com 4.6.2.46 SUB SUB[.W] SUB.B Syntax Subtract source word from destination word Subtract source byte from destination byte SUB src,dst or SUB.W src,dst SUB.B src,dst Operation Description Status Bits Mode Bits Example SUB Example SUB JZ ... Example SUB.B (.not.src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + 1 to the destination.
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Instruction Set Description www.ti.com 4.6.2.47 SUBC SUBC[.W] SUBC.B Syntax Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBC src,dst or SUBC.W src,dst SUBC.B src,dst Operation Description Status Bits Mode Bits Example SUBC.W Example SUB SUBC SUBC Example SUBC.B 210 CPUX (.not.src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand.
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Instruction Set Description www.ti.com 4.6.2.48 SWPB SWPB Syntax Operation Description Swap bytes SWPB dst dst.15:8 ↔ dst.7:0 The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in register mode. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected.
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Instruction Set Description www.ti.com 4.6.2.49 SXT SXT Syntax Operation Description Status Bits Mode Bits Example MOV.B SXT ADD Example MOV.B SXT ADDA 212 CPUX Extend sign SXT dst dst.7 → dst.15:8, dst.7 → dst.19:8 (register mode) Register mode: the sign of the low byte of the operand is extended into the bits Rdst.19:8. Rdst.7 = 0: Rdst.19:8 = 000h afterwards Rdst.7 = 1: Rdst.19:8 = FFFh afterwards Other modes: the sign of the low byte of the operand is extended into the high byte. dst.
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Instruction Set Description www.ti.com 4.6.2.50 TST * TST[.W] * TST.B Syntax Test destination Test destination TST dst or TST.W dst TST.B dst Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP #0,dst CMP.B #0,dst Description Status Bits Mode Bits Example R7POS R7NEG R7ZERO Example R7POS R7NEG R7ZERO The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected.
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Instruction Set Description www.ti.com 4.6.2.51 XOR XOR[.W] XOR.B Syntax Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR src,dst or XOR.W src,dst XOR.B src,dst Operation Description Status Bits Mode Bits Example XOR Example XOR Example XOR.B INV.B 214 CPUX src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected.
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Instruction Set Description www.ti.com 4.6.3 MSP430X Extended Instructions The MSP430X extended instructions give the MSP430X CPU full access to its 20-bit address space. MSP430X instructions require an additional word of op-code called the extension word. All addresses, indexes, and immediate numbers have 20-bit values when preceded by the extension word. The MSP430X extended instructions are described in the following sections.
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Instruction Set Description 4.6.3.1 www.ti.com ADCX * ADCX.A * ADCX.[W] * ADCX.B Syntax Add carry to destination address-word Add carry to destination word Add carry to destination byte ADCX.A dst ADCX dst or ADCX.B dst Operation Emulation ADCX.W dst dst + C → dst ADDCX.A #0,dst ADDCX #0,dst ADDCX.B #0,dst Description Status Bits Mode Bits Example INCX.A ADCX.A 216 CPUX The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
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Instruction Set Description www.ti.com 4.6.3.2 ADDX ADDX.A ADDX.[W] ADDX.B Syntax Add source address-word to destination address-word Add source word to destination word Add source byte to destination byte ADDX.A src,dst ADDX src,dst or ADDX.W src,dst ADDX.B src,dst Operation Description Status Bits Mode Bits Example ADDX.A Example ADDX.W JC ... Example ADDX.B JNC ... src + dst → dst The source operand is added to the destination operand. The previous contents of the destination are lost.
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Instruction Set Description 4.6.3.3 www.ti.com ADDCX ADDCX.A ADDCX.[W] ADDCX.B Syntax Add source address-word and carry to destination address-word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX.A src,dst ADDCX src,dst or ADDCX.W src,dst ADDCX.B src,dst Operation Description Status Bits Mode Bits Example src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous contents of the destination are lost.
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Instruction Set Description www.ti.com 4.6.3.4 ANDX ANDX.A ANDX.[W] ANDX.B Syntax Logical AND of source address-word with destination address-word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX.A src,dst ANDX src,dst or ANDX.W src,dst ANDX.B src,dst Operation Description Status Bits Mode Bits Example MOVA ANDX.A JZ ... src .and. dst → dst The source operand and the destination operand are logically ANDed.
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Instruction Set Description 4.6.3.5 www.ti.com BICX BICX.A BICX.[W] BICX.B Syntax Clear bits set in source address-word in destination address-word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX.A src,dst BICX src,dst or BICX.W src,dst BICX.B src,dst Operation Description Status Bits Mode Bits Example BICX.A Example BICX.W Example BICX.B 220 CPUX (.not. src) .and.
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Instruction Set Description www.ti.com 4.6.3.6 BISX BISX.A BISX.[W] BISX.B Syntax Set bits set in source address-word in destination address-word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX.A src,dst BISX src,dst or BISX.W src,dst BISX.B src,dst Operation Description Status Bits Mode Bits Example BISX.A Example BISX.W Example BISX.B src .or. dst → dst The source operand and the destination operand are logically ORed.
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Instruction Set Description 4.6.3.7 www.ti.com BITX BITX.A BITX.[W] BITX.B Syntax Test bits set in source address-word in destination address-word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX.A src,dst BITX src,dst or BITX.W src,dst BITX.B src,dst Operation Description Status Bits Mode Bits Example BITX.A JNZ ... Example BITX.W JC ... Example BITX.B JNC ... 222 CPUX src .and.
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Instruction Set Description www.ti.com 4.6.3.8 CLRX * CLRX.A * CLRX.[W] * CLRX.B Syntax Clear destination address-word Clear destination word Clear destination byte CLRX.A dst CLRX dst or CLRX.B dst Operation Emulation CLRX.W dst 0 → dst MOVX.A #0,dst MOVX #0,dst MOVX.B #0,dst Description Status Bits Example CLRX.A The destination operand is cleared. Status bits are not affected. RAM address-word TONI is cleared.
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Instruction Set Description 4.6.3.9 www.ti.com CMPX CMPX.A CMPX.[W] CMPX.B Syntax Compare source address-word and destination address-word Compare source word and destination word Compare source byte and destination byte CMPX.A src,dst CMPX src,dst or CMPX.W src,dst CMPX.B src,dst Operation Description Status Bits Mode Bits Example CMPX.A JEQ ... Example CMPX.W JL ... Example CMPX.B JEQ ... (.not.
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Instruction Set Description www.ti.com 4.6.3.10 DADCX * DADCX.A * DADCX.[W] * DADCX.B Syntax Add carry decimally to destination address-word Add carry decimally to destination word Add carry decimally to destination byte DADCX.A dst DADCX dst or DADCX.B dst Operation Emulation DADCX.W dst dst + C → dst (decimally) DADDX.A #0,dst DADDX #0,dst DADDX.B #0,dst Description Status Bits Mode Bits Example The carry bit (C) is added decimally to the destination.
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Instruction Set Description www.ti.com 4.6.3.11 DADDX DADDX.A DADDX.[W] DADDX.B Syntax Add source address-word and carry decimally to destination address-word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX.A src,dst DADDX src,dst or DADDX.W src,dst DADDX.B src,dst Operation Description Status Bits Mode Bits Example src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B), four (.
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Instruction Set Description www.ti.com 4.6.3.12 DECX * DECX.A * DECX.[W] * DECX.B Syntax Decrement destination address-word Decrement destination word Decrement destination byte DECX.A dst DECX dst or DECX.B dst Operation Emulation DECX.W dst dst – 1 → dst SUBX.A #1,dst SUBX #1,dst SUBX.B #1,dst Description Status Bits Mode Bits Example DECX.A The destination operand is decremented by one. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.3.13 DECDX * DECDX.A * DECDX.[W] * DECDX.B Syntax Double-decrement destination address-word Double-decrement destination word Double-decrement destination byte DECDX.A dst DECDX dst or DECDX.B dst Operation Emulation DECDX.W dst dst – 2 → dst SUBX.A #2,dst SUBX #2,dst SUBX.B #2,dst Description Status Bits Mode Bits Example The destination operand is decremented by two. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.3.14 INCX * INCX.A * INCX.[W] * INCX.B Syntax Increment destination address-word Increment destination word Increment destination byte INCX.A dst INCX dst or INCX.B dst Operation Emulation INCX.W dst dst + 1 → dst ADDX.A #1,dst ADDX #1,dst ADDX.B #1,dst Description Status Bits Mode Bits Example INCX.A The destination operand is incremented by one. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.3.15 INCDX * INCDX.A * INCDX.[W] * INCDX.B Syntax Double-increment destination address-word Double-increment destination word Double-increment destination byte INCDX.A dst INCDX dst or INCDX.B dst Operation Emulation INCDX.W dst dst + 2 → dst ADDX.A #2,dst ADDX #2,dst ADDX.B #2,dst Description Status Bits Mode Bits Example The destination operand is incremented by two. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.3.16 INVX * INVX.A * INVX.[W] * INVX.B Syntax Invert destination Invert destination Invert destination INVX.A dst INVX dst or INVX.B dst Operation Emulation INVX.W dst .NOT.dst → dst XORX.A #0FFFFFh,dst XORX #0FFFFh,dst XORX.B #0FFh,dst Description Status Bits Mode Bits Example INVX.A INCX.A Example INVX.B INCX.B The destination operand is inverted. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.3.17 MOVX MOVX.A MOVX.[W] MOVX.B Syntax Move source address-word to destination address-word Move source word to destination word Move source byte to destination byte MOVX.A src,dst MOVX src,dst or MOVX.W src,dst MOVX.B src,dst src → dst The source operand is copied to the destination. The source operand is not affected. Both operands may be located in the full address space.
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Instruction Set Description www.ti.com The next four replacements are possible only if 16-bit indexes are sufficient for the addressing: MOVX.A MOVX.A MOVX.A MOVX.
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Instruction Set Description www.ti.com 4.6.3.18 POPM POPM.A POPM.[W] Syntax Operation Description Status Bits Mode Bits Example POPM.A Example POPM.W 234 CPUX Restore n CPU registers (20-bit data) from the stack Restore n CPU registers (16-bit data) from the stack 1 ≤ n ≤ 16 POPM.W #n,Rdst or POPM #n,Rdst 1 ≤ n ≤ 16 POPM.A: Restore the register values from stack to the specified CPU registers. The SP is incremented by four for each register restored from stack.
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Instruction Set Description www.ti.com 4.6.3.19 PUSHM PUSHM.A PUSHM.[W] Syntax Operation Description Status Bits Mode Bits Example PUSHM.A Example PUSHM.W Save n CPU registers (20-bit data) on the stack Save n CPU registers (16-bit words) on the stack 1 ≤ n ≤ 16 PUSHM.W #n,Rdst or PUSHM #n,Rdst 1 ≤ n ≤ 16 PUSHM.A: Save the 20-bit CPU register values on the stack. The SP is decremented by four for each register stored on the stack. The MSBs are stored first (higher address). PUSHM.
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Instruction Set Description www.ti.com 4.6.3.20 POPX * POPX.A * POPX.[W] * POPX.B Syntax Restore single address-word from the stack Restore single word from the stack Restore single byte from the stack POPX.A dst POPX dst or POPX.B dst Operation Restore the 8-/16-/20-bit value from the stack to the destination. 20-bit addresses are possible. The SP is incremented by two (byte and word operands) and by four (address-word operand). Emulation Description MOVX(.B,.
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Instruction Set Description www.ti.com 4.6.3.21 PUSHX PUSHX.A PUSHX.[W] PUSHX.B Syntax Save single address-word to the stack Save single word to the stack Save single byte to the stack PUSHX.A src PUSHX src or PUSHX.B src Operation Description Status Bits Mode Bits Example PUSHX.B Example PUSHX.A PUSHX.W src Save the 8-/16-/20-bit value of the source operand on the TOS. 20-bit addresses are possible.
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Instruction Set Description www.ti.com 4.6.3.22 RLAM RLAM.A RLAM.[W] Syntax Rotate left arithmetically the 20-bit CPU register content Rotate left arithmetically the 16-bit CPU register content 1≤n≤4 1≤n≤4 RLAM.A #n,Rdst RLAM.W #n,Rdst or RLAM #n,Rdst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 The destination operand is shifted arithmetically left one, two, three, or four positions as shown in Figure 4-43. RLAM works as a multiplication (signed and unsigned) with 2, 4, 8, or 16. The word instruction RLAM.
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Instruction Set Description www.ti.com 4.6.3.23 RLAX * RLAX.A * RLAX.[W] * RLAX.B Syntax Rotate left arithmetically address-word Rotate left arithmetically word Rotate left arithmetically byte RLAX.A dst RLAX dst or RLAX.B dst RLAX.W dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 Operation Emulation ADDX.A dst,dst ADDX dst,dst ADDX.B dst,dst Description The destination operand is shifted left one position as shown in Figure 4-44. The MSB is shifted into the carry bit (C) and the LSB is filled with 0.
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Instruction Set Description www.ti.com 4.6.3.24 RLCX * RLCX.A * RLCX.[W] * RLCX.B Syntax Rotate left through carry address-word Rotate left through carry word Rotate left through carry byte RLCX.A dst RLCX dst or RLCX.B dst Operation Emulation RLCX.W dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C ADDCX.A dst,dst ADDCX dst,dst ADDCX.B dst,dst Description Status Bits Mode Bits Example RLCX.A Example RLCX.B The destination operand is shifted left one position as shown in Figure 4-45.
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Instruction Set Description www.ti.com 4.6.3.25 RRAM RRAM.A RRAM.[W] Syntax Rotate right arithmetically the 20-bit CPU register content Rotate right arithmetically the 16-bit CPU register content RRAM.A #n,Rdst RRAM.W #n,Rdst or RRAM #n,Rdst 1≤n≤4 1≤n≤4 MSB → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one, two, three, or four bit positions as shown in Figure 4-46. The MSB retains its value (sign). RRAM operates equal to a signed division by 2/4/8/16.
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Instruction Set Description www.ti.com 4.6.3.26 RRAX RRAX.A RRAX.[W] RRAX.B Syntax Rotate right arithmetically the 20-bit operand Rotate right arithmetically the 16-bit operand Rotate right arithmetically the 8-bit operand RRAX.A Rdst RRAX.W Rdst RRAX Rdst RRAX.B Rdst RRAX.A dst RRAX dst or RRAX.B dst Operation Description Status Bits Mode Bits Example RPT RRAX.A 242 CPUX RRAX.W dst MSB → MSB → MSB–1 ...
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Instruction Set Description www.ti.com Example The signed 8-bit value in EDE is multiplied by 0.5. RRAX.B C &EDE 19 8 7 0 0 0 MSB LSB 19 C C ; EDE/2 -> EDE 16 0000 15 0 MSB LSB 19 0 MSB LSB Figure 4-47. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode C C C 7 0 MSB LSB 15 0 MSB LSB 31 20 0 0 19 0 MSB LSB Figure 4-48. Rotate Right Arithmetically RRAX(.B,.
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Instruction Set Description www.ti.com 4.6.3.27 RRCM RRCM.A RRCM.[W] Syntax Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content 1≤n≤4 1≤n≤4 RRCM.A #n,Rdst RRCM.W #n,Rdst or RRCM #n,Rdst C → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4-49. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. The word instruction RRCM.
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Instruction Set Description www.ti.com 4.6.3.28 RRCX RRCX.A RRCX.[W] RRCX.B Syntax Rotate right through carry the 20-bit operand Rotate right through carry the 16-bit operand Rotate right through carry the 8-bit operand RRCX.A Rdst RRCX.W Rdst RRCX Rdst RRCX.B Rdst RRCX.A dst RRCX dst or RRCX.B dst Operation Description Status Bits Mode Bits Example SETC RRCX.A RRCX.W dst C → MSB → MSB–1 ...
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Instruction Set Description Example www.ti.com The word in R6 is shifted right by 12 positions. RPT RRCX.W #12 R6 ; R6 = R6 » 12. R6.19:16 = 0 8 19 C 0--------------------0 19 C C 16 0 0 0 0 7 0 MSB LSB 15 0 MSB LSB 19 0 MSB LSB Figure 4-50. Rotate Right Through Carry RRCX(.B,.A) – Register Mode C C C 7 0 MSB LSB 15 0 MSB LSB 31 20 0 0 19 0 MSB LSB Figure 4-51. Rotate Right Through Carry RRCX(.B,.
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Instruction Set Description www.ti.com 4.6.3.29 RRUM RRUM.A RRUM.[W] Syntax Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content RRUM.A #n,Rdst RRUM.W #n,Rdst or RRUM #n,Rdst 1≤n≤4 1≤n≤4 0 → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4-52. Zero is shifted into the MSB, the LSB is shifted into the carry bit.
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Instruction Set Description www.ti.com 4.6.3.30 RRUX RRUX.A RRUX.[W] RRUX.B Syntax Shift right unsigned the 20-bit CPU register content Shift right unsigned the 16-bit CPU register content Shift right unsigned the 8-bit CPU register content RRUX.A Rdst RRUX.W Rdst RRUX Rdst RRUX.B Rdst C=0 → MSB → MSB–1 ... LSB+1 → LSB → C RRUX is valid for register mode only: the destination operand is shifted right by one bit position as shown in Figure 4-53. The word instruction RRUX.W clears the bits Rdst.19:16.
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Instruction Set Description www.ti.com 4.6.3.31 SBCX * SBCX.A * SBCX.[W] * SBCX.B Syntax Subtract borrow (.NOT. carry) from destination address-word Subtract borrow (.NOT. carry) from destination word Subtract borrow (.NOT. carry) from destination byte SBCX.A dst SBCX dst or SBCX.B dst SBCX.W dst Operation dst + 0FFFFFh + C → dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst Emulation SBCX.A #0,dst SBCX #0,dst SBCX.B #0,dst Description Status Bits Mode Bits Example SUBX.B SBCX.
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Instruction Set Description www.ti.com 4.6.3.32 SUBX SUBX.A SUBX.[W] SUBX.B Syntax Subtract source address-word from destination address-word Subtract source word from destination word Subtract source byte from destination byte SUBX.A src,dst SUBX src,dst or SUBX.W src,dst SUBX.B src,dst Operation Description Status Bits Mode Bits Example SUBX.A Example SUBX.W JZ ... Example SUBX.B (.not. src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand.
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Instruction Set Description www.ti.com 4.6.3.33 SUBCX SUBCX.A SUBCX.[W] SUBCX.B Syntax Subtract source address-word with carry from destination address-word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX.A src,dst SUBCX src,dst or SUBCX.W src,dst SUBCX.B src,dst Operation Description Status Bits Mode Bits Example (.not. src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand.
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Instruction Set Description www.ti.com 4.6.3.34 SWPBX SWPBX.A SWPBX.[W] Syntax Swap bytes of lower word Swap bytes of word SWPBX.A dst SWPBX dst or Operation Description Status Bits Mode Bits Example MOVX.A SWPBX.A Example SWPBX.W dst dst.15:8 ↔ dst.7:0 Register mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used, Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared. Other modes: When the .
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Instruction Set Description www.ti.com Before SWPBX 19 16 15 8 X 7 High Byte 0 Low Byte After SWPBX 19 16 15 8 0 7 Low Byte 0 High Byte Figure 4-56. Swap Bytes SWPBX[.W] Register Mode Before SWPBX 15 8 7 High Byte 0 Low Byte After SWPBX 15 8 Low Byte 7 0 High Byte Figure 4-57. Swap Bytes SWPBX[.
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Instruction Set Description www.ti.com 4.6.3.35 SXTX SXTX.A SXTX.[W] Syntax Extend sign of lower byte to address-word Extend sign of lower byte to word SXTX.A dst SXTX dst or SXTX.W dst dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register mode) Register mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits Rdst.19:8. Other modes: SXTX.A: the sign of the low byte of the operand (dst.7) is extended into dst.19:8. The bits dst.31:20 are cleared. SXTX[.
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Instruction Set Description www.ti.com 4.6.3.36 TSTX * TSTX.A * TSTX.[W] * TSTX.B Syntax Test destination address-word Test destination word Test destination byte TSTX.A dst TSTX dst or TSTX.B dst TSTX.W dst Operation dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMPX.A #0,dst CMPX #0,dst CMPX.B #0,dst Description Status Bits Mode Bits Example LEOPOS LEONEG LEOZERO The destination operand is compared with zero. The status bits are set according to the result.
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Instruction Set Description www.ti.com 4.6.3.37 XORX XORX.A XORX.[W] XORX.B Syntax Exclusive OR source address-word with destination address-word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX.A src,dst XORX src,dst or XORX.W src,dst XORX.B src,dst Operation Description Status Bits Mode Bits Example XORX.A Example XORX.W Example XORX.B INV.B 256 CPUX src .xor. dst → dst The source and destination operands are exclusively ORed.
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Instruction Set Description www.ti.com 4.6.4 MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code, which improves code density and execution time.
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Instruction Set Description 4.6.4.1 www.ti.com ADDA ADDA Syntax Add 20-bit source to a 20-bit destination register ADDA Rsrc,Rdst ADDA #imm20,Rdst Operation Description Status Bits Mode Bits Example ADDA JC ... 258 CPUX src + Rdst → Rdst The 20-bit source operand is added to the 20-bit destination CPU register. The previous contents of the destination are lost. The source operand is not affected. N: Set if result is negative (Rdst.19 = 1), reset if positive (Rdst.
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Instruction Set Description www.ti.com 4.6.4.2 BRA * BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples BRA BRA Branch to destination BRA dst dst → PC MOVA dst,PC An unconditional branch is taken to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The branch instruction is an address-word instruction.
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Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Branch to the 20-bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next address in the table pointed to by R5. Indirect, indirect R5. BRA @R5+ ; MOVA @R5+,PC.
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Instruction Set Description www.ti.com 4.6.4.3 CALLA CALLA Syntax Operation Description Status Bits Mode Bits Examples CALLA CALLA Call a subroutine CALLA dst dst → tmp 20-bit dst is evaluated and stored SP – 2 → SP PC.19:16 → @SP updated PC with return address to TOS (MSBs) SP – 2 → SP PC.15:0 → @SP updated PC to TOS (LSBs) tmp → PC saved 20-bit dst to PC A subroutine call is made to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used.
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Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Call a subroutine at the 20-bit address contained in the words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. Indirect, indirect R5. CALLA @R5+ ; Start address at @R5.
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Instruction Set Description www.ti.com 4.6.4.4 CLRA * CLRA Syntax Operation Emulation Description Status Bits Example CLRA Clear 20-bit destination register CLRA Rdst 0 → Rdst MOVA #0,Rdst The destination register is cleared. Status bits are not affected. The 20-bit value in R10 is cleared.
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Instruction Set Description 4.6.4.5 www.ti.com CMPA CMPA Syntax Compare the 20-bit source with a 20-bit destination register CMPA Rsrc,Rdst CMPA #imm20,Rdst Operation Description Status Bits Mode Bits Example CMPA JEQ ... Example CMPA JGE ... 264 CPUX (.not. src) + 1 + Rdst or Rdst – src The 20-bit source operand is subtracted from the 20-bit destination CPU register. This is made by adding the 1s complement of the source + 1 to the destination register. The result affects only the status bits.
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Instruction Set Description www.ti.com 4.6.4.6 DECDA * DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example DECDA Double-decrement 20-bit destination register DECDA Rdst Rdst – 2 → Rdst SUBA #2,Rdst The destination register is decremented by two. The original contents are lost.
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Instruction Set Description 4.6.4.7 INCDA * INCDA Syntax Operation Emulation Description Status Bits Mode Bits Example INCDA 266 www.ti.com CPUX Double-increment 20-bit destination register INCDA Rdst Rdst + 2 → Rdst ADDA #2,Rdst The destination register is incremented by two. The original contents are lost.
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Instruction Set Description www.ti.com 4.6.4.8 MOVA MOVA Syntax Move the 20-bit source to the 20-bit destination MOVA Rsrc,Rdst MOVA MOVA MOVA MOVA MOVA MOVA MOVA MOVA Operation Description Status Bits Mode Bits Examples MOVA #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 src → Rdst Rsrc → dst The 20-bit source operand is moved to the 20-bit destination. The source operand is not affected. The previous content of the destination is lost.
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Instruction Set Description www.ti.com Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9+,R8 ; @R9 -> R8. R9 + 4. 2 words transferred. Copy 20-bit value in R8 to destination addressed by (R9 + 100h). Destination operand in addresses @(R9 + 100h) LSBs and @(R9 + 102h) MSBs. MOVA R8,100h(R9) ; Index: +- 32 K.
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Instruction Set Description www.ti.com 4.6.4.9 RETA * RETA Syntax Operation Return from subroutine Emulation Description MOVA @SP+,PC Status Bits Mode Bits Example SUBR RETA @SP → PC.15:0 LSBs (15:0) of saved PC to PC.15:0 SP + 2 → SP @SP → PC.19:16 MSBs (19:16) of saved PC to PC.19:16 SP + 2 → SP The 20-bit return address information, pushed onto the stack by a CALLA instruction, is restored to the PC. The program continues at the address following the subroutine call. The SR bits SR.
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Instruction Set Description www.ti.com 4.6.4.10 TSTA * TSTA Syntax Operation Test 20-bit destination register Emulation Description CMPA #0,Rdst Status Bits Mode Bits Example R7POS R7NEG R7ZERO 270 CPUX TSTA Rdst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 The destination register is compared with zero. The status bits are set according to the result. The destination register is not affected.
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Instruction Set Description www.ti.com 4.6.4.11 SUBA SUBA Syntax Subtract 20-bit source from 20-bit destination register SUBA Rsrc,Rdst SUBA #imm20,Rdst Operation Description Status Bits Mode Bits Example SUBA JC ... (.not.src) + 1 + Rdst → Rdst or Rdst – src → Rdst The 20-bit source operand is subtracted from the 20-bit destination register. This is made by adding the 1s complement of the source + 1 to the destination. The result is written to the destination register, the source is not affected.
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Chapter 5 SLAU144J – December 2004 – Revised July 2013 Basic Clock Module+ The basic clock module+ provides the clocks for MSP430x2xx devices. This chapter describes the operation of the basic clock module+ of the MSP430x2xx device family. Topic 5.1 5.2 5.3 272 ........................................................................................................................... Page Basic Clock Module+ Introduction .....................................................................
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Basic Clock Module+ Introduction www.ti.com 5.1 Basic Clock Module+ Introduction The basic clock module+ supports low system cost and ultralow power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The basic clock module+ can be configured to operate without any external components, with one external resistor, with one or two external crystals, or with resonators, under full software control.
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Basic Clock Module+ Introduction www.ti.com Internal VLOCLK LP/LF † Oscillator DIVAx 10 Min. Pulse LFXT1CLK Filter Divider /1/2/4/8 else ACLK Auxillary Clock LFXT1Sx OSCOFF XTS XIN 0V XT† LF LFOff XT1Off 0V XOUT SELMx LFXT1 Oscillator DIVMx CPUOFF XCAPx 00 01 Min.
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Basic Clock Module+ Operation www.ti.com DIVAx Internal VLOCLK 10 Divider else /1/2/4/8 LP/LF ACLK Auxillary Clock OSCOFF LFXT1Sx SELMx DIVMx CPUOFF 00 Min. Pulse Filter Divider 10 /1/2/4/8 0 1 11 XT2Sx XT2OFF 01 XT2IN MCLK Main System Clock XT XT2OUT MODx XT2 Oscillator Modulator VCC SCG0 RSELx DCOx SELS DIVSx SCG1 off DC Generator n 0 n+1 1 DCO Min. Puls Filter DCOCLK 0 Divider 1 /1/2/4/8 0 1 SMCLK Sub System Clock Figure 5-2.
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Basic Clock Module+ Operation www.ti.com 5.2.
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Basic Clock Module+ Operation www.ti.com XTS ACLK_request OSCOFF MCLK_request CPUOFF SELM0 XSELM1 LFOff LFXT1Off XT1Off XT2 XT2 is an Internal Signal XT2 = 0: Devices without XT2 oscillator XT2 = 1: Devices with XT2 oscillator SMCLK_request SCG1 SELS Figure 5-3. Off Signals for the LFXT1 Oscillator NOTE: LFXT1 Oscillator Characteristics Low-frequency crystals often require hundreds of milliseconds to start up, depending on the crystal.
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Basic Clock Module+ Operation www.ti.com MCLK_request CPUOFF XSELM1 DCOCLK_on D SMCLK_request SCG1 SELS Q 1: on 0: off DCOCLK SYNC DCOCLK XT2CLK DCO_Gen_on SCG0 1: on 0: off Figure 5-5. On/Off Control of DCO 5.2.5.2 Adjusting the DCO Frequency After a PUC, RSELx = 7 and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK and SMCLK are sourced from DCOCLK.
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Basic Clock Module+ Operation www.ti.com MOV.B MOV.B 5.2.5.3 &CALBC1_1MHZ,&BCSCTL1 &CALDCO_1MHZ,&DCOCTL ; Set range ; Set DCO step + modulation Using an External Resistor (ROSC) for the DCO Some MSP430F2xx devices provide the option to source the DCO current through an external resistor, ROSC, tied to DVCC, when DCOR = 1. In this case, the DCO has the same characteristics as MSP430x1xx devices, and the RSELx setting is limited to 0 to 7 with the RSEL3 ignored.
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Basic Clock Module+ Operation • • www.ti.com High-frequency oscillator fault (LFXT1OF) for LFXT1 in HF mode High-frequency oscillator fault (XT2OF) for XT2 The crystal oscillator fault bits LFXT1OF, and XT2OF are set if the corresponding crystal oscillator is turned on and not operating properly. The fault bits remain set as long as the fault condition exists and are automatically cleared if the enabled oscillators function normally.
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Basic Clock Module+ Operation www.ti.com Select LFXT1CLK DCOCLK LFXT1CLK MCLK DCOCLK Wait for LFXT1CLK LFXT1CLK Figure 5-9.
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Basic Clock Module+ Registers 5.3 www.ti.com Basic Clock Module+ Registers The basic clock module+ registers are listed in Table 5-1. Table 5-1.
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Basic Clock Module+ Registers www.ti.com 5.3.1 DCOCTL, DCO Control Register 7 6 5 4 3 DCOx rw-0 rw-1 DCOx Bits 7-5 MODx Bits 4-0 2 1 0 rw-0 rw-0 MODx rw-1 rw-0 rw-0 rw-0 DCO frequency select. These bits select which of the eight discrete DCO frequencies within the range defined by the RSELx setting is selected. Modulator selection. These bits define how often the f DCO+1 frequency is used within a period of 32 DCOCLK cycles.
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Basic Clock Module+ Registers www.ti.com 5.3.3 BCSCTL2, Basic Clock System Control Register 2 7 6 5 4 SELMx rw-0 DIVMx rw-0 SELMx Bits 7-6 DIVMx Bits 5-4 SELS Bit 3 DIVSx Bits 2-1 DCOR Bit 0 (1) (2) 284 rw-0 3 2 SELS rw-0 rw-0 1 rw-0 0 DCOR (1) (2) DIVSx rw-0 rw-0 Select MCLK. These bits select the MCLK source. 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK when XT2 oscillator not present on-chip.
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Basic Clock Module+ Registers www.ti.com 5.3.4 BCSCTL3, Basic Clock System Control Register 3 7 6 5 4 rw-0 rw-0 XT2Sx Bits 7-6 LFXT1Sx Bits 5-4 XCAPx Bits 3-2 XT2OF Bit 1 LFXT1OF Bit 0 (1) (2) (3) 3 LFXT1Sx (1) XT2Sx rw-0 2 XCAPx (2) rw-0 rw-0 rw-1 1 0 XT2OF (3) LFXT1OF (2) r0 r-(1) XT2 range select. These bits select the frequency range for XT2. 00 0.
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Basic Clock Module+ Registers www.ti.com 5.3.5 IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE (1) rw-0 Bits 7-2 Bit 1 OFIE These bits may be used by other modules. See device-specific data sheet. Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
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Chapter 6 SLAU144J – December 2004 – Revised July 2013 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller of the MSP430x2xx device family. Topic 6.1 6.2 6.3 ........................................................................................................................... Page DMA Introduction ......................................................................................
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DMA Introduction 6.1 www.ti.com DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. Devices that contain a DMA controller may have one, two, or three DMA channels available. Therefore, depending on the number of DMA channels available, some features described in this chapter are not applicable to all devices.
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DMA Introduction www.ti.
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DMA Operation 6.2 www.ti.com DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 6.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 6-2.
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DMA Operation www.ti.com 6.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 6-1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer mode is configured independently from the addressing mode. Any addressing mode can be used with any transfer mode.
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DMA Operation 6.2.2.1 www.ti.com Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 6-3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer. If DMAxSZ = 0, no transfers occur.
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DMA Operation www.ti.com 6.2.2.2 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring during the block transfer are ignored. The block transfer state diagram is shown in Figure 6-4.
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DMA Operation www.ti.
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DMA Operation www.ti.com 6.2.2.3 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared. DMAEN must be set again before another burst-block transfer can be triggered.
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DMA Operation www.ti.
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DMA Operation www.ti.com 6.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 6-2. The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place.
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DMA Operation www.ti.com Table 6-2. DMA Trigger Operation (continued) DMAxTSELx Operation 0101 A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_0CTL DAC12IE bit is set, the DAC12_0CTL DAC12IFG flag will not trigger a transfer. 0110 A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are performed, the corresponding ADC12IFGx is the trigger.
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DMA Operation www.ti.com 6.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0-DMA1-DMA2. If two or three triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer (single, block or burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in progress are not halted if a higher priority channel is triggered.
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DMA Operation www.ti.com 6.2.8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode, when the corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an interrupt request is generated. All DMAIFG flags source only one DMA controller interrupt vector and, on some devices, the interrupt vector may be shared with other modules. Please refer to the device specific datasheet for further details.
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DMA Operation www.ti.com A transfer is triggered if UCB0TXIFG is set. The UCB0TXIFG is cleared automatically when the DMA controller acknowledges the transfer. If UCB0TXIE is set, UCB0TXIFG will not trigger a transfer. 6.2.10 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes.
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DMA Registers 6.3 www.ti.com DMA Registers The DMA registers are listed in Table 6-5. Table 6-5.
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DMA Registers www.ti.com 6.3.1 DMACTL0, DMA Control Register 0 15 14 13 12 11 10 Reserved 9 8 DMA2TSELx rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 rw-(0) rw-(0) rw-(0) 8 DMA1TSELx rw-(0) rw-(0) Reserved DMA2TSELx Bits 15-12 Bits 11-8 DMA1TSELx DMA0TSELx Bits 7-4 Bits 3-0 DMA0TSELx rw-(0) rw-(0) rw-(0) Reserved DMA trigger select. These bits select the DMA transfer trigger.
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DMA Registers www.ti.com 6.3.
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DMA Registers www.ti.com DMAABORT Bit 1 DMAREQ Bit 0 DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0 No DMA start 1 Start DMA 6.3.
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DMA Registers www.ti.com 6.3.
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DMA Registers www.ti.com 6.3.
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Chapter 7 SLAU144J – December 2004 – Revised July 2013 Flash Memory Controller This chapter describes the operation of the MSP430x2xx flash memory controller. Topic 7.1 7.2 7.3 7.4 308 ........................................................................................................................... Flash Flash Flash Flash Memory Introduction ............................................................................... Memory Segmentation ......................................................
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Flash Memory Introduction www.ti.com 7.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has four registers, a timing generator, and a voltage generator to supply program and erase voltages.
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Flash Memory Segmentation www.ti.com Figure 7-2 shows the flash segmentation using an example of 32-KB flash that has eight main segments and four information segments.
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Flash Memory Operation www.ti.com 7.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU can program its own flash memory.
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Flash Memory Operation www.ti.com 7.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 7-1. Table 7-1.
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Flash Memory Operation www.ti.com 7.3.2.1 Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes. After the erase cycle completes, the CPU resumes code execution with the instruction following the dummy write.
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Flash Memory Operation 7.3.2.2 www.ti.com Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again. If a flash access occurs while BUSY = 1, it is an access violation, ACCVIFG is set, and the erase results are unpredictable. The flow to initiate an erase from flash from RAM is shown in Figure 7-6.
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Flash Memory Operation www.ti.com 7.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 7-2. Table 7-2. Write Modes BLKWRT WRT Write Mode 0 1 Byte or word write 1 1 Block write Both write modes use a sequence of individual write instructions, but using the block write mode is approximately twice as fast as byte or word mode, because the voltage generator remains on for the complete block write.
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Flash Memory Operation 7.3.3.2 www.ti.com Initiating a Byte or Word Write From Within Flash Memory The flow to initiate a byte or word write from flash is shown in Figure 7-8. Disable watchdog Setup flash controller and set WRT=1 Write byte or word Set WRT=0, LOCK=1, re-enable watchdog Figure 7-8. Initiating a Byte or Word Write From Flash ; Byte/word write from flash. 514 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0.
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Flash Memory Operation www.ti.com 7.3.3.3 Initiating a Byte or Word Write From RAM The flow to initiate a byte or word write from RAM is shown in Figure 7-9. Disable watchdog yes BUSY = 1 Setup flash controller and set WRT=1 Write byte or word yes BUSY = 1 Set WRT=0, LOCK = 1 re-enable watchdog Figure 7-9. Initiating a Byte or Word Write from RAM ; Byte/word write from RAM. 514 kHz < ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0.
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Flash Memory Operation 7.3.3.4 www.ti.com Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time tCPT must not be exceeded for any block during a block write. A block write cannot be initiated from within flash memory. The block write must be initiated from RAM only.
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Flash Memory Operation www.ti.com 7.3.3.5 Block Write Flow and Example A block write flow is shown in Figure 7-11 and the following example. Disable watchdog yes BUSY = 1 Setup flash controller Set BLKWRT=WRT=1 Write byte or word yes no WAIT=0? Block Border? Set BLKWRT=0 yes BUSY = 1 yes Another Block? Set WRT=0, LOCK=1 re-enable WDT Figure 7-11.
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Flash Memory Operation www.ti.com ; ; ; ; Write one block starting at 0F000h. Must be executed from RAM, Assumes Flash is already erased. 514 kHz < SMCLK < 952 kHz Assumes ACCVIE = NMIIE = OFIE = 0.
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Flash Memory Operation www.ti.com The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the erase and the results are unpredictable. After the erase cycle has completed, the watchdog may be reenabled. 7.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller.
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Flash Memory Operation • • • 7.3.9.1 www.ti.com Program via JTAG Program via the bootstrap loader Program via a custom solution Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals (five signals on 20- and 28-pin devices), ground and, optionally, VCC and RST/NMI. The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible. Further access to the device via JTAG is not possible.
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Flash Memory Registers www.ti.com 7.4 Flash Memory Registers The flash memory registers are listed in Table 7-4. Table 7-4.
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Flash Memory Registers www.ti.com 7.4.1 FCTL1, Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 6 5 4 3 2 1 0 BLKWRT WRT Reserved EEIEX (1) EEI (1) MERAS ERASE Reserved r0 rw-0 rw-0 rw-0 rw-0 r0 rw-0 rw-0 FRKEY FWKEY BLKWRT Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.
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Flash Memory Registers www.ti.com 7.4.3 FCTL3, Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 FAIL LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY rw-0 rw-1 r-1 rw-0 rw-(0) r(w)-0 r(w)-0 r(w)-1 FWKEYx FAIL Bits 15-8 Bit 7 LOCKA Bit 6 EMEX Bit 5 LOCK Bit 4 WAIT Bit 3 ACCVIFG Bit 2 KEYV Bit 1 BUSY Bit 0 FCTLx password. Always reads as 096h. Must be written as 0A5h.
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Flash Memory Registers www.ti.com 7.4.4 FCTL4, Flash Memory Control Register This register is not available in all devices. See the device-specific data sheet for details. 15 14 13 12 11 10 9 8 3 2 1 0 r-0 r-0 r-0 r-0 FWKEYx, Read as 096h Must be written as 0A5h 7 6 r-0 r-0 FWKEYx Reserved MRG1 Bits 15-8 Bits 7-6 Bit 5 MRG0 Bit 4 Reserved Bits 3-0 5 4 MRG1 MRG0 rw-0 rw-0 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC.
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Chapter 8 SLAU144J – December 2004 – Revised July 2013 Digital I/O This chapter describes the operation of the digital I/O ports. Topic 8.1 8.2 8.3 ........................................................................................................................... Page Digital I/O Introduction ..................................................................................... 328 Digital I/O Operation .........................................................................................
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Digital I/O Introduction 8.1 www.ti.com Digital I/O Introduction MSP430 devices have up to eight digital I/O ports implemented, P1 to P8. Each port has up to eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability.
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Digital I/O Operation www.ti.com If the pin's pullup/pulldown resistor is enabled, the corresponding bit in the PxOUT register selects pullup or pulldown. Bit = 0: The pin is pulled down Bit = 1: The pin is pulled up 8.2.3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that are selected for other functions must be set as required by the other function.
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Digital I/O Operation www.ti.com When a port pin is selected as an input to a peripheral, the input signal to the peripheral is a latched representation of the signal at the device pin. While PxSELx = 1, the internal input signal follows the signal at the pin. However, if the PxSELx = 0, the input to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit was reset. 8.2.6 Pin Oscillator Some MSP430 devices have a pin oscillator function built-in to some pins.
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Digital I/O Operation www.ti.com Fosc − T Typical Oscillation Frequency − MHz 1.50 VCC = 3.0 V 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD − External Capacitance − pF Figure 8-2. Typical Pin-Oscillation Frequency 8.2.7 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector.
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Digital I/O Operation www.ti.com NOTE: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags. PxIESx 0→1 0→1 1→0 1→0 8.2.7.3 PxINx 0 1 0 1 PxIFGx May be set Unchanged Unchanged May be set Interrupt Enable P1IE, P2IE Each PxIE bit enables the associated PxIFG interrupt flag. Bit = 0: The interrupt is disabled. Bit = 1: The interrupt is enabled. 8.2.
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Digital I/O Registers www.ti.com 8.3 Digital I/O Registers The digital I/O registers are listed in Table 8-2. Table 8-2.
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Digital I/O Registers www.ti.com Table 8-2.
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Chapter 9 SLAU144J – December 2004 – Revised July 2013 Supply Voltage Supervisor (SVS) This chapter describes the operation of the SVS. The SVS is implemented in selected MSP430x2xx devices. Topic 9.1 9.2 9.3 ........................................................................................................................... Page Supply Voltage Supervisor (SVS) Introduction .................................................... 336 SVS Operation .....................................................
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Supply Voltage Supervisor (SVS) Introduction 9.1 www.ti.com Supply Voltage Supervisor (SVS) Introduction The SVS is used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a userselected threshold.
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SVS Operation www.ti.com 9.2 SVS Operation The SVS detects if the AVCC voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 9.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V(SVS_IT-)) for comparison with AVCC. The SVS is off when VLDx = 0 and on when VLDx > 0.
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SVS Operation www.ti.com 9.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVCC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 9-2. Software Sets VLD>0 AV CC Vhys(SVS_IT−) V(SVS_IT−) V(SVSstart) Vhys(B_IT−) V(B_IT−) VCC(start) BrownOut Region Brownout Region Brownout 1 0 t d(BOR) SVSOUT t d(BOR) SVS Circuit Active 1 0 td(SVSon) Set SVS_POR 1 t d(SVSR) 0 undefined Figure 9-2.
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SVS Registers www.ti.com 9.3 SVS Registers The SVS registers are listed in Table 9-1. Table 9-1.
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SVS Registers www.ti.com 9.3.1 SVSCTL, SVS Control Register 7 6 5 4 VLDx rw-0 (1) VLDx rw-0 (1) Bits 7-4 PORON Bit 3 SVSON Bit 2 SVSOP Bit 1 SVSFG Bit 0 (1) 340 rw-0 (1) rw-0 (1) 3 2 1 0 PORON SVSON SVSOP SVSFG rw-0 (1) r (1) r (1) rw-0 (1) Voltage level detect. These bits turn on the SVS and select the nominal SVS threshold voltage level. See the device-specific data sheet for parameters. 0000 SVS is off 0001 1.9 V 0010 2.1 V 0011 2.2 V 0100 2.3 V 0101 2.4 V 0110 2.
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Chapter 10 SLAU144J – December 2004 – Revised July 2013 Watchdog Timer+ (WDT+) The watchdog timer+ (WDT+) is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the WDT+ The WDT+ is implemented in all MSP430x2xx devices. Topic 10.1 10.2 10.3 ........................................................................................................................... Page Watchdog Timer+ (WDT+) Introduction ..........................................................
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Watchdog Timer+ (WDT+) Introduction www.ti.com 10.1 Watchdog Timer+ (WDT+) Introduction The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
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Watchdog Timer+ (WDT+) Introduction www.ti.com WDTCTL 3 Int. Flag MSB Q6 0 Q9 WDTQn Y 2 1 1 Q13 0 Q15 0 Pulse Generator 16−bit Counter A B 1 Password Compare 1 0 16−bit 1 Clear PUC CLK (Asyn) 0 EQU Write Enable Low Byte EQU Fail-Safe Logic MCLK MDB SMCLK 1 WDTHOLD ACLK 1 WDTNMIES R/W WDTNMI A EN WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 Clock Request Logic LSB MCLK Active SMCLK Active ACLK Active Figure 10-1.
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Watchdog Timer+ Operation www.ti.com 10.2 Watchdog Timer+ Operation The WDT+ module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register. Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte.
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Watchdog Timer+ Operation www.ti.com 10.2.5 Watchdog Timer+ Clock Fail-Safe Operation The WDT+ module provides a fail-safe clocking feature assuring the clock to the WDT+ cannot be disabled while in watchdog mode. This means the low-power modes may be affected by the choice for the WDT+ clock. For example, if ACLK is the WDT+ clock source, LPM4 will not be available, because the WDT+ will prevent ACLK from being disabled.
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Watchdog Timer+ Registers www.ti.com 10.3 Watchdog Timer+ Registers The WDT+ registers are listed in Table 10-1. Table 10-1. Watchdog Timer+ Registers Register Watchdog timer+ control register SFR interrupt enable register 1 SFR interrupt flag register 1 (1) 346 Short Form Register Type Address Initial State WDTCTL Read/write 0120h 06900h with PUC IE1 Read/write 0000h Reset with PUC IFG1 Read/write 0002h Reset with PUC (1) WDTIFG is reset with POR.
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Watchdog Timer+ Registers www.ti.com 10.3.1 WDTCTL, Watchdog Timer+ Register 15 14 13 12 11 10 9 1 8 WDTPW, Read as 069h Must be written as 05Ah 7 6 5 4 3 2 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw-0 rw-0 rw-0 r0(w) rw-0 rw-0 WDTPW WDTHOLD Bits 15-8 Bit 7 WDTNMIES Bit 6 WDTNMI Bit 5 WDTTMSEL Bit 4 WDTCNTCL Bit 3 WDTSSEL Bit 2 WDTISx Bits 1-0 0 WDTISx rw-0 rw-0 Watchdog timer+ password. Always read as 069h.
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Watchdog Timer+ Registers www.ti.com 10.3.2 IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 NMIIE 0 WDTIE rw-0 NMIIE Bits 7-5 Bit 4 WDTIE Bits 3-1 Bit 0 These bits may be used by other modules. See device-specific data sheet. NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
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Chapter 11 SLAU144J – December 2004 – Revised July 2013 Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier is implemented in some MSP430x2xx devices. Topic 11.1 11.2 11.3 ........................................................................................................................... Page Hardware Multiplier Introduction ....................................................................... 350 Hardware Multiplier Operation ...........................
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Hardware Multiplier Introduction www.ti.com 11.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
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Hardware Multiplier Operation www.ti.com 11.2.1 Operand Registers The operand one register OP1 has four addresses, shown in Table 11-1, used to select the multiply mode. Writing the first operand to the desired address selects the type of multiply operation but does not start any operation. Writing the second operand to the operand two register OP2 initiates the multiply operation. Writing OP2 starts the selected operation with the values stored in OP1 and OP2.
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Hardware Multiplier Operation www.ti.com 11.2.2.1 MACS Underflow and Overflow The multiplier does not automatically detect underflow or overflow in the MACS mode. The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is 0FFFF FFFFh to 8000 0000h. An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number.
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Hardware Multiplier Operation www.ti.com 11.2.
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Hardware Multiplier Registers www.ti.com 11.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 11-4. Table 11-4.
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Chapter 12 SLAU144J – December 2004 – Revised July 2013 Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_A of the MSP430x2xx device family. Topic 12.1 12.2 12.3 ........................................................................................................................... Page Timer_A Introduction ....................................................................................... 356 Timer_A Operation ..
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Timer_A Introduction www.ti.com 12.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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Timer_A Operation www.ti.com TASSELx IDx Timer Block Timer Clock MCx 15 TACLK 00 ACLK 01 SMCLK 10 INCLK 11 0 16−bit Timer TAR Divider 1/2/4/8 Clear Count Mode RC EQU0 Set TAIFG TACLR CCR0 CCR1 CCR2 CCISx CMx logic COV SCS CCI2A 00 CCI2B 01 GND 10 VCC 11 Capture Mode Timer Clock 15 0 0 Sync TACCR2 1 Comparator 2 CCI EQU2 SCCI Y A EN CAP 0 1 Set TACCR2 CCIFG OUT EQU0 Output Unit2 D Set Q Timer Clock OUT2 Signal Reset POR OUTMODx Figure 12-1.
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Timer_A Operation www.ti.com NOTE: Modifying Timer_A Registers It is recommended to stop the timer before modifying its operation (with exception of the interrupt enable, and interrupt flag) to avoid errant operating conditions. When the timer clock is asynchronous to the CPU clock, any read from TAR should occur while the timer is not operating or the results may be unpredictable.
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Timer_A Operation www.ti.com Timer Clock Timer CCR0−1 CCR0 0h 1h CCR0−1 CCR0 0h Set TAIFG Set TACCR0 CCIFG Figure 12-3. Up Mode Flag Setting 12.2.3.2 Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, if the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period. If the new period is less than the current count value, the timer rolls to zero.
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Timer_A Operation www.ti.com TACCR1b TACCR0b TACCR1c TACCR0c TACCR0d 0FFFFh TACCR1a TACCR1d TACCR0a t0 t0 t1 t0 t1 t1 Figure 12-6. Continuous Mode Time Intervals Time intervals can be produced with other modes as well, where TACCR0 is used as the period register. Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than the TACCR0 value.
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Timer_A Operation www.ti.com Timer Clock Timer CCR0−1 CCR0 CCR0−1 CCR0−2 1h 0h Up/Down Set TAIFG Set TACCR0 CCIFG Figure 12-8. Up/Down Mode Flag Setting 12.2.3.6 Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately, however the new period takes effect after the counter counts down to zero.
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Timer_A Operation www.ti.com 0FFFFh TACCR0 TACCR1 TACCR2 0h Dead Time Output Mode 6:Toggle/Set Output Mode 2:Toggle/Reset EQU1 EQU1 EQU1 EQU1 TAIFG EQU0 EQU0 EQU2 EQU2 EQU2 EQU2 TAIFG Interrupt Events Figure 12-9. Output Unit in Up/Down Mode 12.2.4 Capture/Compare Blocks Two or three identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1.
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Timer_A Operation www.ti.com Idle Capture No Capture Taken Capture Read Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken COV = 1 Idle Capture Figure 12-11. Capture Cycle 12.2.4.1 Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges.
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Timer_A Operation www.ti.com Table 12-2. Output Modes OUTMODx Mode Description 000 Output The output signal OUTx is defined by the OUTx bit. The OUTx signal updates immediately when OUTx is updated. 001 Set The output is set when the timer counts to the TACCRx value. It remains set until a reset of the timer, or until another output mode is selected and affects the output. 010 Toggle/Reset The output is toggled when the timer counts to the TACCRx value.
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Timer_A Operation www.ti.com 12.2.5.3 Output Example — Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 12-13 using TACCR0 and TACCR1.
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Timer_A Operation www.ti.com 12.2.5.4 Output Example — Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 12-14 using TACCR0 and TACCR2.
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Timer_A Operation www.ti.com 12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: • TACCR0 interrupt vector for TACCR0 CCIFG • TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register. In compare mode, any CCIFG flag is set if TAR counts to the associated TACCRx value. Software may also set or clear any CCIFG flag.
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Timer_A Operation www.ti.com 12.2.6.3 TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
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Timer_A Registers www.ti.com 12.3 Timer_A Registers The Timer_A registers are listed in Table 12-3. Table 12-3.
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Timer_A Registers www.ti.com 12.3.
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Timer_A Registers www.ti.com 12.3.2 TAR, Timer_A Register 15 14 13 12 11 10 9 8 rw-(0) rw-(0) rw-(0) rw-(0) 3 2 1 0 rw-(0) rw-(0) rw-(0) rw-(0) 11 10 9 8 rw-(0) rw-(0) rw-(0) rw-(0) 3 2 1 0 rw-(0) rw-(0) rw-(0) rw-(0) TARx rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 TARx rw-(0) TARx rw-(0) Bits 15-0 rw-(0) rw-(0) Timer_A register. The TAR register is the count of Timer_A. 12.3.
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Timer_A Registers www.ti.com 12.3.
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Timer_A Registers www.ti.com 12.3.
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Chapter 13 SLAU144J – December 2004 – Revised July 2013 Timer_B Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_B of the MSP430x2xx device family. Topic 13.1 13.2 13.3 374 Timer_B ........................................................................................................................... Page Timer_B Introduction .......................................................................................
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Timer_B Introduction www.ti.com 13.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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Timer_B Introduction www.ti.
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Timer_B Operation www.ti.com 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 13.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TBR may be cleared by setting the TBCLR bit.
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Timer_B Operation www.ti.com 13.2.3.1 Up Mode The up mode is used if the timer period must be different from TBR(max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 13-2. The number of timer counts in the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TBCL0, the timer immediately restarts counting from zero.
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Timer_B Operation www.ti.com Timer Clock Timer TBR (max)−1 TBR (max) 0h 1h TBR (max)−1 TBR (max) 0h Set TBIFG Figure 13-5. Continuous Mode Flag Setting 13.2.3.4 Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
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Timer_B Operation www.ti.com TBCL0 0h Figure 13-7. Up/Down Mode The count direction is latched. This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped. If this is not desired, the TBCLR bit must be used to clear the direction. The TBCLR bit also clears the TBR value and the clock divider. In up/down mode, the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period, separated by 1/2 the timer period.
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Timer_B Operation www.ti.com The ability to simultaneously load grouped compare latches assures the dead times. TBR(max) TBCL0 TBCL1 TBCL3 0h Dead Time Output Mode 6:Toggle/Set Output Mode 2:Toggle/Reset EQU1 EQU1 EQU1 EQU1 TBIFG EQU0 EQU0 EQU3 EQU3 EQU3 EQU3 TBIFG Interrupt Events Figure 13-9. Output Unit in Up/Down Mode 13.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B.
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Timer_B Operation www.ti.com Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 1311. COV must be reset with software. Idle Capture No Capture Taken Capture Read Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Taken COV = 1 Idle Capture Figure 13-11.
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Timer_B Operation www.ti.com 13.2.4.2 Compare Mode The compare mode is selected when CAP = 0. Compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TBR counts to the value in a TBCLx: • Interrupt flag CCIFG is set • Internal signal EQUx = 1 • EQUx affects the output according to the output mode 13.2.4.2.1 Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx.
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Timer_B Operation www.ti.com 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a highimpedance state. When the TBOUTH pin function is selected for the pin, and when the pin is pulled high, all Timer_B outputs are in a high-impedance state. 13.2.5.
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Timer_B Operation www.ti.com 13.2.5.1.1 Output Example, Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 13-12 using TBCL0 and TBCL1.
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Timer_B Operation www.ti.com 13.2.5.1.2 Output Example, Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 13-13 using TBCL0 and TBCL1. TBR(max) TBCL0 TBCL1 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Interrupt Events Figure 13-13.
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Timer_B Operation www.ti.com 13.2.5.1.3 Output Example, Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 13-14 using TBCL0 and TBCL3.
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Timer_B Operation www.ti.com 13.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: • TBCCR0 interrupt vector for TBCCR0 CCIFG • TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register. In compare mode, any CCIFG flag is set when TBR counts to the associated TBCLx value. Software may also set or clear any CCIFG flag.
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Timer_B Operation www.ti.com Example 13-1. Recommended Use of TBIV ; Interrupt handler for TBCCR0 CCIFG. CCIFG_0_HND ... ; Start of handler Interrupt latency RETI ; Interrupt TB_HND ADD RETI JMP JMP RETI RETI RETI RETI Cycles handler for TBIFG, TBCCR1 and TBCCR2 CCIFG. ... ; Interrupt latency &TBIV,PC ; Add offset to Jump table ; Vector 0: No interrupt CCIFG_1_HND ; Vector 2: Module 1 CCIFG_2_HND ; Vector 4: Module 2 ; Vector 6 ; Vector 8 ; Vector 10 ; Vector 12 TBIFG_HND ...
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Timer_B Registers www.ti.com 13.3 Timer_B Registers The Timer_B registers are listed in Table 13-5: Table 13-5.
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Timer_B Registers www.ti.com 13.3.
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Timer_B Registers www.ti.com 13.3.2 TBR, Timer_B Register 15 14 13 12 11 10 9 8 rw-(0) rw-(0) rw-(0) rw-(0) 3 2 1 0 rw-(0) rw-(0) rw-(0) rw-(0) 11 10 9 8 rw-(0) rw-(0) rw-(0) rw-(0) 3 2 1 0 rw-(0) rw-(0) rw-(0) rw-(0) TBRx rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 TBRx rw-(0) TBRx rw-(0) Bits 15-0 rw-(0) rw-(0) Timer_B register. The TBR register is the count of Timer_B. 13.3.
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Timer_B Registers www.ti.com 13.3.
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Timer_B Registers www.ti.com 13.3.
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Chapter 14 SLAU144J – December 2004 – Revised July 2013 Universal Serial Interface (USI) The Universal Serial Interface (USI) module provides SPI and I2C serial communication with one hardware module. This chapter discusses both modes. Topic 14.1 14.2 14.3 ........................................................................................................................... Page USI Introduction ..............................................................................................
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USI Introduction www.ti.com 14.1 USI Introduction The USI module provides the basic functionality to support synchronous serial communication. In its simplest form, it is an 8- or 16-bit shift register that can be used to output data streams, or when combined with minimal software, can implement serial communication. In addition, the USI includes built-in hardware functionality to ease the implementation of SPI and I2C communication.
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USI Introduction www.ti.com USIGE USII2C = 0 USIOE USIPE6 SDO D Q G USILSB USI16B USIPE7 SDI 8/16 Bit Shift Register EN USISR USICNTx USIIFGCC Bit Counter EN USISWRST Set USIIFG USICKPH USICKPL USIPE5 1 Shift Clock SCLK 0 USISSELx SCLK 000 ACLK 001 SMCLK 010 SMCLK 011 USISWCLK 100 TA0 101 TA1 110 TA2 111 USIMST USIDIVx 1 Clock Divider /1/2/4/8... /128 USICLK 0 HOLD USIIFG Figure 14-1.
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USI Introduction www.ti.
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USI Operation www.ti.com 14.2 USI Operation The USI module is a shift register and bit counter that includes logic to support SPI and I2C communication. The USI shift register (USISR) is directly accessible by software and contains the data to be transmitted or the data that has been received. The bit counter counts the number of sampled bits and sets the USI interrupt flag USIIFG when the USICNTx value becomes zero, either by decrementing or by directly writing zero to the USICNTx bits.
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USI Operation www.ti.com 14.2.3 SPI Mode The USI module is configured in SPI mode when USII2C = 0. Control bit USICKPL selects the inactive level of the SPI clock while USICKPH selects the clock edge on which SDO is updated and SDI is sampled. Figure 14-3 shows the clock/data relationship for an 8-bit, MSB-first transfer. USIPE5, USIPE6, and USIPE7 must be set to enable the SCLK, SDO, and SDI port functions.
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USI Operation www.ti.com 14.2.3.3 USISR Operation The 16-bit USISR is made up of two 8-bit registers, USISRL and USISRH. Control bit USI16B selects the number of bits of USISR that are used for data transmit and receive. When USI16B = 0, only the lower 8 bits, USISRL, are used. To transfer < 8 bits, the data must be loaded into USISRL such that unused bits are not shifted out. The data must be MSB- or LSB-aligned depending on USILSB. Figure 14-4 shows an example of 7-bit data handling.
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USI Operation www.ti.com 2 14.2.4 I C Mode The USI module is configured in I2C mode when USII2C =1, USICKPL = 1, and USICKPH = 0. For I2C data compatibility, USILSB and USI16B must be cleared. USIPE6 and USIPE7 must be set to enable the SCL and SDA port functions. 14.2.4.1 I2C Master Mode To configure the USI module as an I2C master the USIMST bit must be set. In master mode, clocks are generated by the USI module and output to the SCL line while USIIFG = 0.
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USI Operation www.ti.com 14.2.4.4 I2C Receiver In I2C receiver mode the output must be disabled by clearing USIOE and the USI module is prepared for reception by writing 8 into USICNTx. This clears USIIFG and SCL is generated in master mode or released from being held low in slave mode. The USIIFG bit will be set after 8 clocks. This stops the clock signal on SCL in master mode or holds SCL low at the next low phase in slave mode.
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USI Operation www.ti.com 14.2.4.7 Releasing SCL Setting the USISCLREL bit will release SCL if it is being held low by the USI module without requiring USIIFG to be cleared. The USISCLREL bit will be cleared automatically if a START condition is received and the SCL line will be held low on the next clock. In slave operation this bit should be used to prevent SCL from being held low when the slave has detected that it was not addressed by the master.
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USI Registers www.ti.com 14.3 USI Registers The USI registers are listed in Table 14-1. Table 14-1.
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USI Registers www.ti.com 14.3.1 USICTL0, USI Control Register 0 7 6 5 4 3 2 1 0 USIPE7 USIPE6 USIPE5 USILSB USIMST USIGE USIOE USISWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 USIPE7 Bit 7 USIPE6 Bit 6 USIPE5 Bit 5 USILSB Bit 4 USIMST Bit 3 USIGE Bit 2 USIOE Bit 1 USISWRST Bit 0 406 2 USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I C mode. 0 USI function disabled 1 USI function enabled USI SDO/SCL port enable.
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USI Registers www.ti.com 14.3.2 USICTL1, USI Control Register 1 7 6 5 4 3 2 1 0 USICKPH USII2C USISTTIE USIIE USIAL USISTP USISTTIFG USIIFG rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 USICKPH Bit 7 USII2C Bit 6 USISTTIE Bit 5 USIIE Bit 4 USIAL Bit 3 USISTP Bit 2 USISTTIFG Bit 1 USIIFG Bit 0 Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge.
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USI Registers www.ti.com 14.3.3 USICKCTL, USI Clock Control Register 7 6 5 4 USIDIVx rw-0 rw-0 USIDIVx Bits 7-5 USISSELx Bits 4-2 USICKPL Bit 1 USISWCLK Bit 0 3 2 1 0 USICKPL USISWCLK rw-0 rw-0 rw-0 2 1 0 rw-0 rw-0 USISSELx rw-0 rw-0 rw-0 Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Clock source select. Not used in slave mode.
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USI Registers www.ti.com 14.3.5 USISRL, USI Low Byte Shift Register 7 6 5 4 3 2 1 0 rw rw rw rw 3 2 1 0 rw rw rw rw USISRLx rw USISRLx rw Bits 7-0 rw rw Contents of the USI low byte shift register 14.3.6 USISRH, USI High Byte Shift Register 7 6 5 4 USISRHx rw USISRHx rw Bits 7-0 rw rw Contents of the USI high byte shift register. Ignored when USI16B = 0.
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Chapter 15 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. Topic 15.1 15.2 15.3 15.4 410 ........................................................................................................................... USCI USCI USCI USCI Overview .........................
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USCI Overview www.ti.com 15.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
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USCI Introduction: UART Mode www.ti.
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USCI Operation: UART Mode www.ti.com 15.3 USCI Operation: UART Mode In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USCI. The transmit and receive functions use the same baud rate frequency. 15.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition.
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USCI Operation: UART Mode www.ti.com Blocks of Characters UCAxTXD/RXD Idle Periods of 10 Bits or More UCAxTXD/RXD Expanded UCAxTXD/RXD ST Address SP ST First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Data SP Character Within Block ST Data SP Character Within Block Idle Period Less Than 10 Bits Figure 15-3. Idle-Line Format The UCDORM bit is used to control data reception in the idle-line multiprocessor format.
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USCI Operation: UART Mode www.ti.com 15.3.3.3 Address-Bit Multiprocessor Format When UCMODEx = 10, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 15-4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USCI UCADDR bit is set when a received character has its address bit set and is transferred to UCAxRXBUF.
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USCI Operation: UART Mode www.ti.com 15.3.4 Automatic Baud Rate Detection When UCMODEx = 11 UART mode with automatic baud rate detection is selected. For automatic baud rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. A break is detected when 11 or more continuous zeros (spaces) are received. If the length of the break exceeds 22 bit times the break timeout error flag UCBTOE is set. The synch field follows the break as shown in Figure 15-5.
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USCI Operation: UART Mode www.ti.com 15.3.4.1 Transmitting a Break/Synch Field The following procedure transmits a break/synch field: • Set UCTXBRK with UMODEx = 11. • Write 055h to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates a break field of 13 bits followed by a break delimiter and the synch character. The length of the break delimiter is controlled with the UCDELIMx bits.
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USCI Operation: UART Mode www.ti.com 15.3.6 Automatic Error Detection Glitch suppression prevents the USCI from being accidentally started. Any pulse on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored. See the device-specific data sheet for parameters. When a low period on UCAxRXD exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USCI halts character reception and waits for the next low period on UCAxRXD.
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USCI Operation: UART Mode www.ti.com 15.3.7.1 Receive Data Glitch Suppression Glitch suppression prevents the USCI from being accidentally started. Any glitch on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored by the USCI and further action will be initiated as shown in Figure 15-8. See the device-specific data sheet for parameters. URXDx URXS tτ Figure 15-8.
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USCI Operation: UART Mode www.ti.com Timing for each bit is shown in Figure 15-10. For each bit received, a majority vote is taken to determine the bit value. These samples occur at the N/2 - 1/2, N/2, and N/2 + 1/2 BRCLK periods, where N is the number of BRCLKs per BITCLK.
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USCI Operation: UART Mode www.ti.com Table 15-3. BITCLK16 Modulation Pattern UCBRFx No.
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USCI Operation: UART Mode www.ti.com When greater accuracy is required, the UCBRSx modulator can also be implemented with values from 0 to 7. To find the setting that gives the lowest maximum bit error rate for any given bit, a detailed error calculation must be performed for all settings of UCBRSx from 0 to 7 with the initial UCBRFx setting and with the UCBRFx setting incremented and decremented by one. 15.3.11 Transmit Bit Timing The timing for each character is the sum of the individual bit timings.
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USCI Operation: UART Mode www.ti.com i tideal 2 1 0 t1 t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 BRCLK UCAxRXD ST D0 D1 RXD synch. ST D0 D1 tactual t0 Synchronization Error ± 0.5x BRCLK t1 t2 Sample RXD synch. Majority Vote Taken Majority Vote Taken Majority Vote Taken Figure 15-11. Receive Error The ideal sampling time is in the middle of a bit period: tbit,ideal,RX [i] = 1 (i + 0.
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USCI Operation: UART Mode www.ti.com 15.3.13 Typical Baud Rates and Errors Standard baud rate data for UCBRx, UCBRSx and UCBRFx are listed in Table 15-4 and Table 15-5 for a 32768-Hz crystal sourcing ACLK and typical SMCLK frequencies. Ensure that the selected BRCLK frequency does not exceed the device-specific maximum USCI input frequency (see the device-specific data sheet). The receive error is the accumulated time versus the ideal scanning time in the middle of each bit.
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USCI Operation: UART Mode www.ti.com Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (continued) BRCLK Frequency [Hz] Baud Rate [Baud] UCBRx UCBRSx UCBRFx 12,000,000 115200 104 1 0 -0.5 0.6 -0.9 1.2 12,000,000 128000 93 6 0 -0.8 0 -1.5 0.4 12,000,000 256000 46 7 0 -1.9 0 -2.0 2.0 16,000,000 9600 1666 6 0 -0.05 0.05 -0.05 0.1 16,000,000 19200 833 2 0 -0.1 0.05 -0.2 0.1 16,000,000 38400 416 6 0 -0.2 0.2 -0.2 0.
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USCI Operation: UART Mode www.ti.com 15.3.14 Using the USCI Module in UART Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition.
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USCI Operation: UART Mode www.ti.com Example 15-2 shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. Example 15-2. Shared Interrupt Vectors Software Example, Data Transmit USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) ...
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USCI Registers: UART Mode www.ti.com 15.4 USCI Registers: UART Mode The USCI registers applicable in UART mode are listed in Table 15-6 and Table 15-7. Table 15-6.
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USCI Registers: UART Mode www.ti.com 15.4.1 UCAxCTL0, USCI_Ax Control Register 0 7 6 5 4 3 UCPEN UCPAR UCMSB UC7BIT UCSPB rw-0 rw-0 rw-0 rw-0 rw-0 UCPEN Bit 7 UCPAR Bit 6 UCMSB Bit 5 UC7BIT Bit 4 UCSPB Bit 3 UCMODEx Bits 2-1 UCSYNC Bit 0 2 1 UCMODEx rw-0 0 UCSYNC rw-0 rw-0 Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.
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USCI Registers: UART Mode www.ti.com 15.4.2 UCAxCTL1, USCI_Ax Control Register 1 7 6 UCSSELx rw-0 rw-0 UCSSELx Bits 7-6 UCRXEIE Bit 5 UCBRKIE Bit 4 UCDORM Bit 3 UCTXADDR Bit 2 UCTXBRK Bit 1 UCSWRST Bit 0 5 4 3 2 1 0 UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 USCI clock source select. These bits select the BRCLK source clock.
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USCI Registers: UART Mode www.ti.com 15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register 7 6 5 4 3 UCBRFx rw-0 rw-0 UCBRFx Bits 7-4 UCBRSx Bits 3-1 UCOS16 Bit 0 2 1 UCBRSx rw-0 rw-0 rw-0 rw-0 0 UCOS16 rw-0 rw-0 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern. Second modulation stage select. These bits determine the modulation pattern for BITCLK.
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USCI Registers: UART Mode www.ti.com 15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw UCRXBUFx rw UCRXBUFx rw Bits 7-0 rw rw The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset. 15.4.
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USCI Registers: UART Mode www.ti.com 15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register 7 6 5 4 Reserved r-0 UCDELIMx r-0 Reserved UCDELIMx Bits 7-6 Bits 5-4 UCSTOE Bit 3 UCBTOE Bit 2 Reserved UCABDEN Bit 1 Bit 0 rw-0 rw-0 3 2 1 0 UCSTOE UCBTOE Reserved UCABDEN rw-0 rw-0 r-0 rw-0 Reserved Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times Synch field time out error 0 No error 1 Length of synch field exceeded measurable time.
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USCI Registers: UART Mode www.ti.com 15.4.14 UC1IE, USCI_A1 Interrupt Enable Register 7 6 5 4 3 2 Unused rw-0 Unused rw-0 UCA1TXIE Bits 7-4 Bits 3-2 Bit 1 UCA1RXIE Bit 0 rw-0 rw-0 1 0 UCA1TXIE UCA1RXIE rw-0 rw-0 Unused These bits may be used by other USCI modules (see the device-specific data sheet). USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled 15.4.
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Chapter 16 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. Topic 16.1 16.2 16.3 16.4 ........................................................................................................................... USCI USCI USCI USCI Overview .........
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USCI Overview www.ti.com 16.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter (for example, USCI_A is different from USCI_B). If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
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USCI Introduction: SPI Mode www.ti.
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USCI Operation: SPI Mode www.ti.com 16.3 USCI Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: • UCxSIMO: Slave in, master out – Master mode: UCxSIMO is the data output line. – Slave mode: UCxSIMO is the data input line.
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USCI Operation: SPI Mode www.ti.com 16.3.2 Character Format The USCI module in SPI mode supports 7-bit and 8-bit character lengths selected by the UC7BIT bit. In 7bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. NOTE: Default Character Format The default SPI character transmission is LSB first. For communication with other SPI interfaces it MSB-first mode may be required.
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USCI Operation: SPI Mode www.ti.com 16.3.3.1 Four-Pin SPI Master Mode In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master as described in Table 16-1. When UCxSTE is in the master-inactive state: • UCxSIMO and UCxCLK are set to inputs and no longer drive the bus • The error bit UCFE is set indicating a communication integrity violation to be handled by the user. • The internal state machines are reset and the shift operation is aborted.
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USCI Operation: SPI Mode www.ti.com 16.3.5 SPI Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode the bit clock generator is disabled and the clock is provided by the master. A transmit or receive operation is indicated by UCBUSY = 1. A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated. 16.3.5.
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USCI Operation: SPI Mode www.ti.com 16.3.6.1 Serial Clock Polarity and Phase The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown in Figure 16-4. UC UC CKPH CKPL Cycle# 0 0 UCxCLK 0 1 UCxCLK 1 0 UCxCLK 1 1 UCxCLK 1 2 3 4 5 6 7 8 UCxSTE 0 X UCxSIMO UCxSOMI MSB LSB 1 X UCxSIMO UCxSOMI MSB LSB Move to UCxTXBUF TX Data Shifted Out RX Sample Points Figure 16-4.
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USCI Operation: SPI Mode www.ti.com 16.3.8.2 SPI Receive Interrupt Operation The UCxRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF. An interrupt request is generated if UCxRXIE and GIE are also set. UCxRXIFG and UCxRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read. 16.3.8.3 USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors.
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USCI Registers: SPI Mode www.ti.com 16.4 USCI Registers: SPI Mode The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are listed in Table 16-2. Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 16-3. Table 16-2.
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USCI Registers: SPI Mode www.ti.com 16.4.1 UCAxCTL0, USCI_Ax Control Register 0, UCBxCTL0, USCI_Bx Control Register 0 7 6 5 4 3 UCCKPH UCCKPL UCMSB UC7BIT UCMST rw-0 rw-0 rw-0 rw-0 rw-0 UCCKPH Bit 7 UCCKPL Bit 6 UCMSB Bit 5 UC7BIT Bit 4 2 1 UCMODEx rw-0 0 UCSYNC=1 rw-0 Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge. Clock polarity select.
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USCI Registers: SPI Mode www.ti.com 16.4.3 UCAxBR0, USCI_Ax Bit Rate Control Register 0, UCBxBR0, USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 1 0 rw rw rw 2 1 0 rw rw rw UCBRx - low byte rw rw rw rw rw 16.4.4 UCAxBR1, USCI_Ax Bit Rate Control Register 1, UCBxBR1, USCI_Bx Bit Rate Control Register 1 7 6 5 4 3 UCBRx - high byte rw rw UCBRx rw rw rw Bit clock prescaler setting. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value. 16.4.
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USCI Registers: SPI Mode www.ti.com 16.4.7 UCAxTXBUF, USCI_Ax Transmit Buffer Register, UCBxTXBUF, USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw UCTXBUFx rw UCTXBUFx rw Bits 7-0 rw rw The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCxTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. 16.4.
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USCI Registers: SPI Mode www.ti.com 16.4.
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Chapter 17 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the I2C mode. Topic 17.1 17.2 17.3 17.4 ........................................................................................................................... USCI USCI USCI USCI Overview .............................................
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USCI Overview www.ti.com 17.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
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USCI Operation: I2C Mode www.ti.com UCA10 UCGCEN Own Address UC1OA UCxSDA Receive Shift Register Receive Buffer UC1RXBUF I2C State Machine Transmit Buffer UC 1TXBUF Transmit Shift Register Slave Address UC 1SA UCSLA10 UCxSCL UCSSELx Bit Clock Generator UCxBRx UC1CLK 00 ACLK 01 SMCLK 10 SMCLK 11 16 UCMST Prescaler/Divider BRCLK Figure 17-1. USCI Block Diagram: I2C Mode 17.3 USCI Operation: I2C Mode The I2C mode supports any slave or master I2C-compatible device.
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USCI Operation: I2C Mode www.ti.com VCC Device A MSP430 Serial Data (SDA) Serial Clock (SCL) Device C Device B Figure 17-2. I2C Bus Connection Diagram 17.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. To select I2C operation the UCMODEx bits must be set to 11. After module initialization, it is ready for transmit or receive operation.
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USCI Operation: I2C Mode www.ti.com START and STOP conditions are generated by the master and are shown in Figure 17-3. A START condition is a high-to-low transition on the SDA line while SCL is high. A STOP condition is a low-to-high transition on the SDA line while SCL is high. The bus busy bit, UCBBUSY, is set after a START and cleared after a STOP. Data on SDA must be stable during the high period of SCL as shown in Figure 17-4.
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USCI Operation: I2C Mode 1 7 S Slave Address www.ti.com 1 1 R/W ACK 1 8 1 1 Data ACK S Any Number 1 7 Slave Address 1 R/W ACK 1 8 1 1 Data ACK P Any Number Figure 17-7. I2C Module Addressing Format with Repeated START Condition 17.3.4 I2C Module Operating Modes In I2C mode the USCI module can operate in master transmitter, master receiver, slave transmitter, or slave receiver mode. The modes are discussed in the following sections. Time lines are used to illustrate the modes.
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USCI Operation: I2C Mode www.ti.com 17.3.4.1.1 I2C Slave Transmitter Mode Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own address with a set R/W bit. The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted.
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USCI Operation: I2C Mode www.ti.com 17.3.4.1.2 I2C Slave Receiver Mode Slave receiver mode is entered when the slave address transmitted by the master is identical to its own address and a cleared R/W bit is received. In slave receiver mode, serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it can hold SCL low if intervention of the CPU is required after a byte has been received.
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USCI Operation: I2C Mode www.ti.com Reception of own address and data bytes. All are acknowledged. S SLA/W A DATA A DATA A DATA A P or S UCBxRXIFG=1 UCTR=0 (Receiver) UCSTTIFG=1 UCSTPIFG=0 Bus stalled (SCL held low) if UCBxRXBUF not read Refer to: ”Slave Transmitter” Timing Diagram Read data from UCBxRXBUF Last byte is not acknowledged. DATA UCTXNACK=1 A P or S UCTXNACK=0 Bus not stalled even if UCBxRXBUF not read Reception of the general call address.
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USCI Operation: I2C Mode www.ti.com 17.3.4.1.3 I2C Slave 10-bit Addressing Mode The 10-bit addressing mode is selected when UCA10 = 1 and is as shown in Figure 17-11. In 10-bit addressing mode, the slave is in receive mode after the full address is received. The USCI module indicates this by setting the UCSTTIFG flag while the UCTR bit is cleared. To switch the slave into transmitter mode the master sends a repeated START condition together with the first byte of the address but with the R/W bit set.
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USCI Operation: I2C Mode www.ti.com 17.3.4.2 Master Mode The USCI module is configured as an I2C master by selecting the I2C mode with UCMODEx = 11 and UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must be set and its own address must be programmed into the UCBxI2COA register. When UCA10 = 0, 7-bit addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the USCI module responds to a general call. 17.3.4.2.
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USCI Operation: I2C Mode Successful transmission to a slave receiver www.ti.
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USCI Operation: I2C Mode www.ti.com 17.3.4.2.2 I2C Master Receiver Mode After initialization, master receiver mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, clearing UCTR for receiver mode, and setting UCTXSTT to generate a START condition. The USCI module checks if the bus is available, generates the START condition, and transmits the slave address.
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USCI Operation: I2C Mode Successful reception from a slave transmitter www.ti.
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USCI Operation: I2C Mode www.ti.com 17.3.4.2.3 I2C Master 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCSLA10 = 1 and is shown in Figure 17-14. Master Transmitter Successful transmission to a slave receiver S 11110 xx/W A SLA (2.) A 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 A DATA A DATA P UCTXSTT=0 UCTXSTP=0 UCBxTXIFG=1 UCTXSTP=1 UCBxTXIFG=1 Master Receiver Successful reception from a slave transmitter S 11110 xx/W A SLA (2.
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USCI Operation: I2C Mode www.ti.com 2 17.3.5 I C Clock Generation and Synchronization The I2C clock SCL is provided by the master on the I2C bus. When the USCI is in master mode, BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slave mode the bit clock generator is not used and the UCSSELx bits are don’t care. The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clock source, BRCLK.
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USCI Operation: I2C Mode www.ti.com 17.3.6 Using the USCI Module in I2C Mode with Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition.
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USCI Operation: I2C Mode www.ti.com 17.3.7.4 Interrupt Vector Assignment USCI_Ax and USCI_Bx share the same interrupt vectors. In I2C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCNACKIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I2C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector.
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USCI Registers: I2C Mode www.ti.com 17.4 USCI Registers: I2C Mode The USCI registers applicable in I2C mode for USCI_B0 are listed in Table 17-2, and for USCI_B1 in Table 17-3. Table 17-2.
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USCI Registers: I2C Mode www.ti.com 17.4.
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USCI Registers: I2C Mode www.ti.com 17.4.2 UCBxCTL1, USCI_Bx Control Register 1 7 6 UCSSELx rw-0 rw-0 UCSSELx Bits 7-6 Unused UCTR Bit 5 Bit 4 UCTXNACK Bit 3 UCTXSTP Bit 2 UCTXSTT Bit 1 UCSWRST Bit 0 5 4 3 2 1 0 Unused UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST r0 rw-0 rw-0 rw-0 rw-0 rw-1 USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK Unused Transmitter/receiver 0 Receiver 1 Transmitter Transmit a NACK.
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USCI Registers: I2C Mode www.ti.com 17.4.5 UCBxSTAT, USCI_Bx Status Register 7 6 5 4 3 2 1 0 Unused UCSCLLOW UCGC UCBBUSY UCNACKIFG UCSTPIFG UCSTTIFG UCALIFG rw-0 r-0 rw-0 r-0 rw-0 rw-0 rw-0 rw-0 Unused UCSCLLOW Bit 7 Bit 6 UCGC Bit 5 UCBBUSY Bit 4 UCNACKIFG Bit 3 UCSTPIFG Bit 2 UCSTTIFG Bit 1 UCALIFG Bit 0 Unused. SCL low 0 SCL is not held low 1 SCL is held low General call address received. UCGC is automatically cleared when a START condition is received.
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USCI Registers: I2C Mode www.ti.com 17.4.8 UCBxI2COA, USCIBx I2C Own Address Register 15 14 13 12 11 10 UCGCEN 0 0 0 0 0 9 8 rw-0 r0 r0 r0 r0 r0 rw-0 rw-0 7 6 5 4 3 2 1 0 rw-0 rw-0 rw-0 rw-0 I2COAx I2COAx rw-0 rw-0 UCGCEN Bit 15 I2COAx Bits 9-0 rw-0 rw-0 General call response enable 0 Do not respond to a general call 1 Respond to a general call I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller.
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USCI Registers: I2C Mode www.ti.com 17.4.11 IE2, Interrupt Enable Register 2 7 6 UCB0TXIE Bits 7-4 Bit 3 UCB0RXIE Bit 2 Bits 1-0 5 4 3 2 UCB0TXIE UCB0RXIE rw-0 rw-0 1 0 1 0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other modules (see the device-specific data sheet). 17.4.
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USCI Registers: I2C Mode www.ti.com 17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register 7 6 5 4 Unused rw-0 rw-0 Unused UCB1TXIFG Bits 7-4 Bit 3 UCB1RXIFG Bit 2 Bits 1-0 rw-0 rw-0 3 2 UCB1TXIFG UCB1RXIFG rw-1 rw-0 1 0 Unused. USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character.
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Chapter 18 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430AFE2xx devices. Topic 18.1 18.2 18.3 474 ...........................................................................................................................
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USART Introduction: UART Mode www.ti.com 18.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared.
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USART Operation: UART Mode www.ti.
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USART Operation: UART Mode www.ti.com NOTE: Initializing or Reconfiguring the USART Module The required USART initialization/reconfiguration process is: 1. Set SWRST (BIS.B #SWRST,&UxCTL) 2. Initialize all USART registers with SWRST = 1 (including UxCTL) 3. Enable USART module via the MEx SFRs (URXEx and/or UTXEx) 4. Clear SWRST via software (BIC.B #SWRST,&UxCTL) 5.
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USART Operation: UART Mode www.ti.com Blocks of Characters UTXDx/URXDx Idle Periods of 10 Bits or More UTXDx/URXDx Expanded UTXDx/URXDx ST Address SP ST First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Data SP Character Within Block ST Data SP Character Within Block Idle Period Less Than 10 Bits Figure 18-3. Idle-Line Format The URXWIE bit is used to control data reception in the idle-line multiprocessor format.
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USART Operation: UART Mode www.ti.com The URXWIE bit is used to control data reception in the address-bit multiprocessor format. If URXWIE is set, data characters (address bit = 0) are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated. When a character containing a set address bit is received, the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIFGx. All applicable error status flags are also set.
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USART Operation: UART Mode www.ti.com Table 18-1. Receive Error Conditions Error Condition Description Framing error A framing error occurs when a low stop bit is detected. When two stop bits are used, only the first stop bit is checked for framing error. When a framing error is detected, the FE bit is set. Parity error A parity error is a mismatch between the number of 1s in a character and the value of the parity bit.
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USART Operation: UART Mode www.ti.com No Data Written to Transmit Buffer UTXEx = 0 UTXEx = 1 Transmit Disable UTXEx = 0 Idle State (Transmitter Enabled) UTXEx = 1 Data Written to Transmit Buffer Not Completed Handle Interrupt Conditions Transmission Active Character Transmitted UTXEx = 1 UTXEx = 0 And Last Buffer Entry Is Transmitted Figure 18-6.
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USART Operation: UART Mode www.ti.com Majority Vote: (m= 0) (m= 1) Bit Start BRCLK Counter N/2 N/2−1 N/2−2 1 N/2 1 0 N/2−1 N/2−2 N/2 N/2−1 1 N/2 N/2−1 1 0 N/2 BITCLK NEVEN: INT(N/2) NODD : INT(N/2) + R(= 1) INT(N/2) + m(= 0) INT(N/2) + m(= 1) Bit Period m: corresponding modulation bit R: Remainder from N/2 division Figure 18-8. BITCLK Baud Rate Timing 18.2.6.1 Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator.
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USART Operation: UART Mode www.ti.com 18.2.6.2 Determining the Modulation Value Determining the modulation value is an interactive process. Using the timing error formula provided, beginning with the start bit , the individual bit errors are calculated with the corresponding modulator bit set and cleared. The modulation bit setting with the lower error is selected and the next bit error is calculated. This process is continued until all bit errors are minimized.
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USART Operation: UART Mode Start bit Error [%]= www.ti.com rate × (0+1)×UxBR+1) –1)×100%=2.54% (baud BRCLK ( Data bit D0 Error [%]= rate × 1+1)×UxBR+2 )–2)×100%=5.08% (baud BRCLK ( ( Data bit D1 Error [%]= rate × (2+1)×UxBR+2 )–3)×100%=0.29% (baud BRCLK ( Data bit D2 Error [%]= rate × (3+1)×UxBR+3 )–4)×100%=2.83% (baud BRCLK ( Data bit D3 Error [%]= rate × (4+1)×UxBR+3 )–5)×100%=-1.95% (baud BRCLK ( Data bit D4 Error [%]= rate × 5+1)×UxBR+4 )–6)×100%=0.
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USART Operation: UART Mode www.ti.com 18.2.6.4 Receive Bit Timing Receive timing is subject to two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 18-9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.
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USART Operation: UART Mode www.ti.com Data bit D1 Error [%]= rate × 2x(1+6 )+2×UxBR+1]-1-2)×100%=0.29% (baud BRCLK [ Data bit D2 Error [%]= rate × 2x 1+6 )+3×UxBR+2]-1-3)×100%=2.83% (baud BRCLK [ ( Data bit D3 Error [%]= rate × 2x(1+6 )+4×UxBR+2]-1-4)×100%=-1.95% (baud BRCLK [ Data bit D4 Error [%]= rate × 2x(1+6 )+5×UxBR+3]-1-5)×100%=0.59% (baud BRCLK [ Data bit D5 Error [%]= rate × 2x(1+6 )+6×UxBR+4]-1-6)×100%=3.13% (baud BRCLK [ Data bit D6 Error [%]= rate × 2x 1+6 )+7×UxBR+4]-1-7)×100%=-1.
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USART Operation: UART Mode www.ti.com 18.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. 18.2.7.1 USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF.
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USART Operation: UART Mode www.ti.com URXEIE is used to enable or disable erroneous characters from setting URXIFGx. When using multiprocessor addressing modes, URXWIE is used to auto-detect valid address characters and reject unwanted data characters. Two types of characters do not set URXIFGx: • Erroneous characters when URXEIE = 0 • Non-address characters when URXWIE = 1 When URXEIE = 1 a break condition sets the BRK bit and the URXIFGx flag. 18.2.7.
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USART Operation: UART Mode www.ti.com 18.2.7.4 Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) is ignored by the USART and no interrupt request is generated (see Figure 18-12). See the device-specific data sheet for parameters. URXDx URXS tτ Figure 18-12.
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USART Registers: UART Mode www.ti.com 18.3 USART Registers: UART Mode Table 18-3 lists the registers for all devices implementing a USART module. Table 18-4 applies only to devices with a second USART module, USART1. Table 18-3.
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USART Registers: UART Mode www.ti.com 18.3.1 UxCTL, USART Control Register 7 6 5 4 3 2 1 0 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 PENA Bit 7 PEV Bit 6 SPB Bit 5 CHAR Bit 4 LISTEN Bit 3 SYNC Bit 2 MM Bit 1 SWRST Bit 0 Parity enable 0 Parity disabled 1 Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select.
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USART Registers: UART Mode www.ti.com 18.3.2 UxTCTL, USART Transmit Control Register 7 6 Unused CKPL rw-0 rw-0 Unused CKPL Bit 7 Bit 6 SSELx Bits 5-4 URXSE Bit 3 TXWAKE Bit 2 Unused TXEPT Bit 1 Bit 0 492 5 4 SSELx rw-0 rw-0 3 2 1 0 URXSE TXWAKE Unused TXEPT rw-0 rw-0 rw-0 rw-1 Unused Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK Source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start-edge.
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USART Registers: UART Mode www.ti.com 18.3.3 UxRCTL, USART Receive Control Register 7 6 5 4 3 2 1 0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 FE Bit 7 PE Bit 6 OE Bit 5 BRK Bit 4 URXEIE Bit 3 URXWIE Bit 2 RXWAKE Bit 1 RXERR Bit 0 Framing error flag 0 No error 1 Character received with low stop bit Parity error flag. When PENA = 0, PE is read as 0. 0 No error 1 Character received with parity error Overrun error flag.
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USART Registers: UART Mode www.ti.com 18.3.6 UxMCTL, USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Modulation bits. These bits select the modulation for BRCLK. 18.3.7 UxRXBUF, USART Receive Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 r r r r r r r UxRXBUFx r Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift register.
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USART Registers: UART Mode www.ti.com 18.3.9 IE1, Interrupt Enable Register 1 7 6 UTXIE0 URXIE0 rw-0 rw-0 UTXIE0 Bit 7 URXIE0 Bit 6 Bits 5-0 5 4 3 2 1 0 1 0 1 0 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. 18.3.
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USART Registers: UART Mode www.ti.com 18.3.12 IFG2, Interrupt Flag Register 2 7 6 UTXIFG1 Bits 7-6 Bit 5 URXIFG1 Bit 4 Bits 3-0 496 5 4 UTXIFG1 URXIFG1 rw-1 rw-0 3 2 1 0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character.
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Chapter 19 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430AFE2xx devices. Topic 19.1 19.2 19.3 .....................................................................................................................
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USART Introduction: SPI Mode www.ti.com 19.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared.
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USART Operation: SPI Mode www.ti.com 19.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: • SIMO: Slave in, master out – Master mode: SIMO is the data output line. – Slave mode: SIMO is the data input line.
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USART Operation: SPI Mode www.ti.com 19.2.2 Master Mode Figure 19-2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates a data transfer when data is moved to the transmit data buffer UxTXBUF. The UxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on SIMO starting with the most significant bit.
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USART Operation: SPI Mode www.ti.com MASTER SIMO SPI Receive Buffer Data Shift Register DSR MSB Px.x STE STE SS Port.x SOMI SLAVE SIMO Transmit Buffer UxTXBUF Receive Buffer UxRXBUF Transmit Shift Register Receive Shift Register MSB MSB SOMI LSB SCLK LSB LSB UCLK COMMON SPI MSP430 USART Figure 19-3. USART Slave and External Master 19.2.3.
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USART Operation: SPI Mode www.ti.com No Clock at UCLK USPIEx = 0 USPIEx = 1 Transmit Disable USPIEx = 0 Idle State (Transmitter Enabled) SWRST USPIEx = 1 External Clock Present Not Completed Character Transmitted USPIEx = 1 PUC Handle Interrupt Conditions Transmission Active USPIEx = 0 Figure 19-5. Slave Transmit Enable State Diagram 19.2.4.2 Receive Enable The SPI receive enable state diagrams are shown in Figure 19-6 and Figure 19-7.
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USART Operation: SPI Mode www.ti.com SSEL1 SSEL0 N = 215 28 ... 27 UxBR1 UCLKI 00 ACLK 01 SMCLK 10 SMCLK 11 20 ... UxBR0 8 8 BRCLK R 16−Bit Counter Q15 ............ Q0 Toggle FF R Compare (0 or 1) BITCLK Modulation Data Shift Register R (LSB first) mX 8 m7 m0 Bit Start UxMCTL Figure 19-8. SPI Baud Rate Generator The 16-bit value of UxBR0+UxBR1 is the division factor of the USART clock source, BRCLK. The maximum baud rate that can be generated in master mode is BRCLK/2.
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USART Operation: SPI Mode www.ti.com 19.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. 19.2.6.1 SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF.
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USART Operation: SPI Mode www.ti.com 19.2.6.2 SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 19-11 and Figure 19-12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read.
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USART Registers: SPI Mode www.ti.com 19.3 USART Registers: SPI Mode Table 19-1 lists the registers for all devices implementing a USART module. Table 19-2 applies only to devices with a second USART module, USART1. Table 19-1.
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USART Registers: SPI Mode www.ti.com 19.3.1 UxCTL, USART Control Register 7 6 Unused rw-0 rw-0 Unused I2C Bits 7-6 Bit 5 CHAR Bit 4 LISTEN Bit 3 SYNC Bit 2 MM Bit 1 SWRST Bit 0 5 4 3 2 1 0 I2C CHAR LISTEN SYNC MM SWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 Unused I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0 SPI mode 1 I2C mode Character length 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled.
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USART Registers: SPI Mode www.ti.com 19.3.3 UxRCTL, USART Receive Control Register 7 6 5 FE Unused OE rw-0 rw-0 rw-0 FE Bit 7 Unused OE Bit 6 Bit 5 Unused Bits 4-0 4 3 2 1 0 rw-0 rw-0 Unused rw-0 rw-0 rw-0 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0 No conflict detected 1 A negative edge occurred on STE, indicating bus conflict Unused Overrun error flag.
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USART Registers: SPI Mode www.ti.com 19.3.8 UxTXBUF, USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7-0 The transmit data buffer is user accessible and contains current data to be transmitted. When seven-bit character-length is used, the data should be MSB justified before being moved into UxTXBUF. Data is transmitted MSB first. Writing to UxTXBUF clears UTXIFGx. 19.3.
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USART Registers: SPI Mode www.ti.com 19.3.12 IE2, Interrupt Enable Register 2 7 6 UTXIE1 Bits 7-6 Bit 5 URXIE1 Bit 4 Bits 3-0 5 4 UTXIE1 URXIE1 rw-0 rw-0 3 2 1 0 1 0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt.
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Chapter 20 SLAU144J – December 2004 – Revised July 2013 OA The OA is a general purpose operational amplifier. This chapter describes the OA. Two OA modules are implemented in the MSP430x22x4 devices. Topic 20.1 20.2 20.3 ........................................................................................................................... Page OA Introduction ............................................................................................... 512 OA Operation ............................
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OA Introduction www.ti.com 20.1 OA Introduction The OA operational amplifiers support front-end analog signal conditioning prior to analog-to-digital conversion. Features of the OA include: • Single supply, low-current operation • Rail-to-rail output • Programmable settling time vs. power consumption • Software selectable configurations • Software selectable feedback resistor ladder for PGA implementations NOTE: Multiple OA Modules Some devices may integrate more than one OA module.
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OA Operation www.ti.
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OA Operation www.ti.com 20.2.1 OA Amplifier The OA is a configurable, low-current, rail-to-rail output operational amplifier. It can be configured as an inverting amplifier, or a non-inverting amplifier, or can be combined with other OA modules to form differential amplifiers. The output slew rate of the OA can be configured for optimized settling time vs power consumption with the OAPMx bits. When OAPMx = 00 the OA is off and the output is highimpedance. When OAPMx > 0, the OA is on.
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OA Operation www.ti.com 20.2.4.1 General Purpose Opamp Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAxCTL0 bits define the signal routing. The OAx inputs are selected with the OAPx and OANx bits. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.2 Unity Gain Mode for Differential Amplifier In this mode the output of the OAx is connected to the inverting input of the OAx providing a unity gain buffer.
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OA Operation www.ti.com NOTE: Using OAx Negative Input Simultaneously as ADC Input When the pin connected to the negative input multiplexer is also used as an input to the ADC, conversion errors up to 5 mV may be observed due to internal wiring voltage drops. 20.2.4.8 Differential Amplifier Mode This mode allows internal routing of the OA signals for a two-opamp or three-opamp instrumentation amplifier. Figure 20-2 shows a two-opamp configuration with OA0 and OA1.
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OA Operation www.ti.com OAPx OAxI0 00 OA0I1 01 OAxIA 10 0 11 1 OAxIB OAPMx + 0 OA1 1 − OAPx OAxI0 00 OA0I1 01 OAxIA 10 0 11 1 OAxIB 000 OAPMx 001 else + 0 OA0 1 − 000 OAFBRx 001 000 000 001 001 010 3 010 011 else OAxRTOP 100 011 OAxRTOP 001 101 000 4R 100 110 101 001 110 010 000 4R 111 010 2R 2 011 2R 111 OAADCx 100 3 011 R 101 100 000 R 101 001 R 110 010 110 111 R 011 111 100 00 101 01 110 10 111 11 OAxFB Figure 20-3.
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OA Operation www.ti.com Figure 20-4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2 (Three opamps are not available on all devices. See device-specific data sheet for implementation.). The control register settings are shown in Table 20-5. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal. The gain settings are shown in Table 20-6. The OAx interconnections are shown in Figure 20-5. Table 20-5.
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OA Operation www.ti.
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OA Registers www.ti.com 20.3 OA Registers The OA registers are listed in Table 20-7. Table 20-7.
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OA Registers www.ti.com 20.3.1 OAxCTL0, Opamp Control Register 0 7 6 5 4 OANx rw-0 rw-0 OANx Bits 7-6 OAPx Bits 5-4 OAPMx Bits 3-2 OAADCx 3 OAPx Bits 1-0 rw-0 2 1 OAPMx rw-0 rw-0 0 OAADCx rw-0 rw-0 rw-0 Inverting input select. These bits select the input signal for the OA inverting input. 00 OAxI0 01 OAxI1 10 OAxIA (see the device-specific data sheet for connected signal) 11 OAxIB (see the device-specific data sheet for connected signal) Non-inverting input select.
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OA Registers www.ti.com 20.3.2 OAxCTL1, Opamp Control Register 1 7 6 5 4 OAFBRx rw-0 rw-0 OAFBRx Bits 7-5 OAFCx Bits 4-2 OANEXT Bit 1 OARRIP Bit 0 522 OA 3 2 OAFCx rw-0 rw-0 rw-0 rw-0 1 0 OANEXT OARRIP rw-0 rw-0 OAx feedback resistor select 000 Tap 0 - 0R/16R 001 Tap 1 - 4R/12R 010 Tap 2 - 8R/8R 011 Tap 3 - 10R/6R 100 Tap 4 - 12R/4R 101 Tap 5 - 13R/3R 110 Tap 6 - 14R/2R 111 Tap 7 - 15R/1R OAx function control.
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Chapter 21 SLAU144J – December 2004 – Revised July 2013 Comparator_A+ Comparator_A+ is an analog voltage comparator. This chapter describes the operation of the Comparator_A+ of the 2xx family. Topic 21.1 21.2 21.3 ........................................................................................................................... Page Comparator_A+ Introduction ............................................................................. 524 Comparator_A+ Operation ..............................
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Comparator_A+ Introduction www.ti.com 21.1 Comparator_A+ Introduction The Comparator_A+ module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.
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Comparator_A+ Operation www.ti.com 21.2 Comparator_A+ Operation The Comparator_A+ module is configured with user software. The setup and operation of Comparator_A+ is discussed in the following sections. 21.2.1 Comparator The comparator compares the analog voltages at the + and - input terminals. If the + terminal is more positive than the - terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON.
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Comparator_A+ Operation www.ti.com 21.2.3 Input Short Switch The CASHORT bit shorts the comparator_A+ inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 21-2. Sampling Capacitor, Cs CASHORT Analog Inputs Figure 21-2. Comparator_A+ Sample-And-Hold The required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (Ri), and the resistance of the external source (RS).
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Comparator_A+ Operation www.ti.com + Terminal Comparator Inputs − Terminal Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT Figure 21-3. RC-Filter Response at the Output of the Comparator 21.2.5 Voltage Reference Generator The voltage reference generator is used to generate VCAREF,which can be applied to either comparator input terminal. The CAREFx bits control the output of the voltage generator. The CARSEL bit selects the comparator terminal to which VCAREF is applied.
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Comparator_A+ Operation www.ti.com 21.2.7 Comparator_A+ Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A+ as shown in Figure 215. The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output, selected by the CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag generates an interrupt request. The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software.
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Comparator_A+ Operation www.ti.com The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 21-7. VC VCC Rmeas Rref 0.25 × VCC Phase I: Charge Phase II: Discharge Phase III: Charge tref Phase IV: Discharge t tmeas Figure 21-7.
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Comparator_A+ Registers www.ti.com 21.3 Comparator_A+ Registers The Comparator_A+ registers are listed in Table 21-1. Table 21-1.
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Comparator_A+ Registers www.ti.com 21.3.1 CACTL1, Comparator_A+ Control Register 1 7 6 CAEX CARSEL rw-(0) rw-(0) CAEX CARSEL Bit 7 Bit 6 CAREF Bits 5-4 CAON Bit 3 CAIES Bit 2 CAIE Bit 1 CAIFG Bit 0 5 4 CAREFx rw-(0) rw-(0) 3 2 1 0 CAON CAIES CAIE CAIFG rw-(0) rw-(0) rw-(0) rw-(0) Comparator_A+ exchange. This bit exchanges the comparator inputs and inverts the comparator output. Comparator_A+ reference select. This bit selects which terminal the VCAREF is applied to.
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Comparator_A+ Registers www.ti.com 21.3.2 CACTL2, Comparator_A+, Control Register 7 6 5 4 3 2 1 0 CASHORT P2CA4 P2CA3 P2CA2 P2CA1 P2CA0 CAF CAOUT rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-(0) CASHORT Bit 7 P2CA4 Bit 6 P2CA3 (1) P2CA2 P2CA1 Bits 5-3 P2CA0 Bit 2 CAF Bit 1 CAOUT Bit 0 (1) Input short. This bit shorts the + and - input terminals. 0 Inputs not shorted 1 Inputs shorted Input select.
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Chapter 22 SLAU144J – December 2004 – Revised July 2013 ADC10 The ADC10 module is a high-performance 10-bit analog-to-digital converter. This chapter describes the operation of the ADC10 module of the 2xx family in general. There are device with less than eight external input channels. Topic 22.1 22.2 22.3 ........................................................................................................................... Page ADC10 Introduction ...................................................
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ADC10 Introduction www.ti.com 22.1 ADC10 Introduction The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention. The module can be configured with user software to support a variety of applications.
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ADC10 Introduction www.ti.com Ve REF+ REFBURST ADC10SR REFOUT SREF1 0 REFON INCHx=0Ah 2_5V VREF+ 1 1 on 1.5V or 2.5V Reference 0 VREF−/VeREF− AVCC Ref_x AVCC INCHx Auto A0† A1† A2† A3† A4† A5† A6† A7† A12† A13† A14† A15† SREF1 SREF0 11 10 01 00 4 CONSEQx 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SREF2 ADC10OSC AVSS 1 0 ADC10SSELx ADC10ON ADC10DIVx Sample and Hold S/H VR− VR+ 00 Divider /1 ..
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ADC10 Operation www.ti.com 22.2 ADC10 Operation The ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed in the following sections. 22.2.1 10-Bit ADC Core The ADC core converts an analog input to its 10-bit digital representation and stores the result in the ADC10MEM register. The core uses two programmable/selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion.
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ADC10 Operation www.ti.com 22.2.2.1 Analog Port Selection The ADC10 external inputs Ax, VeREF+,and VREF- share terminals with general purpose I/O ports, which are digital CMOS gates (see the device-specific data sheet). When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate.
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ADC10 Operation www.ti.com 22.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: • The ADC10SC bit • The Timer_A Output Unit 1 • The Timer_A Output Unit 0 • The Timer_A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit. The SHTx bits select the sample period tsample to be 4, 8, 16, or 64 ADC10CLK cycles.
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ADC10 Operation www.ti.com For example, if RS is 10 kΩ, tsample must be greater than 2.47 µs. When the reference buffer is used in burst mode, the sampling time must be greater than the sampling time calculated and the settling time of the buffer, tREFBURST: tsample > { 11 (RS + RI) × ln(2 ) × CI tREFBURST For example, if VRef is 1.5 V and RS is 10 kΩ, tsample must be greater than 2.47 µs when ADC10SR = 0, or 2.5 µs when ADC10SR = 1. See the device-specific data sheet for parameters.
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ADC10 Operation www.ti.com 22.2.6.1 Single-Channel Single-Conversion Mode A single channel selected by INCHx is sampled and converted once. The ADC result is written to ADC10MEM. Figure 22-5 shows the flow of the single-channel, single-conversion mode. When ADC10SC triggers a conversion, successive conversions can be triggered by the ADC10SC bit. When any other trigger source is used, ENC must be toggled between each conversion.
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ADC10 Operation www.ti.com 22.2.6.2 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence stops after conversion of channel A0. Figure 22-6 shows the sequence-of-channels mode. When ADC10SC triggers a sequence, successive sequences can be triggered by the ADC10SC bit.
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ADC10 Operation www.ti.com 22.2.6.3 Repeat-Single-Channel Mode A single channel selected by INCHx is sampled and converted continuously. Each ADC result is written to ADC10MEM. Figure 22-7 shows the repeat-single-channel mode.
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ADC10 Operation www.ti.com 22.2.6.4 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence. Figure 22-8 shows the repeat-sequence-of-channels mode.
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ADC10 Operation www.ti.com 22.2.6.5 Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed.
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ADC10 Operation www.ti.com 22.2.7.1 One-Block Transfer Mode The one-block mode is selected if the ADC10TB is reset. The value n in ADC10DTC1 defines the total number of transfers for a block. The block start address is defined anywhere in the MSP430 address range using the 16-bit register ADC10SA. The block ends at ADC10SA + 2n – 2. The one-block transfer mode is shown in Figure 22-9. TB=0 ’n’th transfer ADC10SA+2n−2 ADC10SA+2n−4 DTC 2nd transfer ADC10SA+2 1st transfer ADC10SA Figure 22-9.
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ADC10 Operation www.ti.
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ADC10 Operation www.ti.com 22.2.7.2 Two-Block Transfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n in ADC10DTC1 defines the number of transfers for one block. The address range of the first block is defined anywhere in the MSP430 address range with the 16-bit register ADC10SA. The first block ends at ADC10SA+2n-2. The address range for the second block is defined as SA+2n to SA+4n-2. The two-block transfer mode is shown in Figure 22-11.
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ADC10 Operation www.ti.
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ADC10 Operation www.ti.com 22.2.7.3 Continuous Transfer A continuous transfer is selected if ADC10CT bit is set. The DTC does not stop after block one (in oneblock mode) or block two (in two-block mode) has been transferred. The internal address pointer and transfer counter are set equal to ADC10SA and n respectively. Transfers continue starting in block one.
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ADC10 Operation www.ti.com Volts 1.300 1.200 1.100 1.000 0.900 VTEMP=0.00355(TEMPC)+0.986 0.800 0.700 Celsius 0 −50 50 100 Figure 22-13. Typical Temperature Sensor Transfer Function 22.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
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ADC10 Operation www.ti.com DVCC Digital Power Supply Decoupling 10uF DVSS 100nF AVCC Analog Power Supply Decoupling (if available) 10uF AVSS 100nF VREF+ /VeREF+ Using an External Positive Reference VREF- /VeREF- Using an External Negative Reference Figure 22-15. ADC10 Grounding and Noise Considerations (External VREF) 22.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 22-16.
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ADC10 Registers www.ti.com 22.3 ADC10 Registers The ADC10 registers are listed in Table 22-3. Table 22-3.
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ADC10 Registers www.ti.com 22.3.
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ADC10 Registers ADC10IFG Bit 2 ENC Bit 1 ADC10SC Bit 0 554 ADC10 www.ti.com ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset when the interrupt request is accepted, or it may be reset by software. When using the DTC this flag is set when a block of transfers is completed. 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion. Software-controlled sample-and-conversion start.
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ADC10 Registers www.ti.com 22.3.2 ADC10CTL1, ADC10 Control Register 1 15 14 13 12 11 INCHx rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 6 5 4 3 2 7 ADC10DIVx rw-(0) 10 SHSx rw-(0) ADC10SSELx rw-(0) rw-(0) rw-(0) 9 8 ADC10DF ISSH rw-(0) rw-(0) 1 CONSEQx rw-(0) 0 ADC10BUSY rw-(0) r-0 Can be modified only when ENC = 0 INCHx Bits 15-12 SHSx Bits 11-10 ADC10DF Bit 9 ISSH Bit 8 ADC10DIVx Bits 7-5 ADC10SSELx Bits 4-3 (1) Input channel select.
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ADC10 Registers www.ti.com CONSEQx Bits 2-1 ADC10BUSY Bit 0 Conversion sequence mode select 00 Single-channel-single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC10 busy. This bit indicates an active sample or conversion operation 0 No operation is active. 1 A sequence, sample, or conversion is active. 22.3.
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ADC10 Registers www.ti.com 22.3.6 ADC10MEM, Conversion-Memory Register, 2s Complement Format 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 Conversion Results r Conversion Results r Bits 15-0 The 10-bit conversion results are left-justified, 2s complement format. Bit 15 is the MSB. Bits 5-0 are always 0. 22.3.
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ADC10 Registers www.ti.com 22.3.9 ADC10SA, Start Address Register for Data Transfer 15 14 13 12 11 10 9 8 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 4 3 2 1 0 ADC10SAx rw-(0) rw-(0) rw-(0) 7 6 5 ADC10SAx rw-(0) rw-(0) ADC10SAx Bits 15-1 Unused Bit 0 558 ADC10 rw-(0) rw-(0) 0 rw-(0) rw-(0) rw-(0) r0 ADC10 start address. These bits are the start address for the DTC. A write to register ADC10SA is required to initiate DTC transfers. Unused, Read only. Always read as 0.
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Chapter 23 SLAU144J – December 2004 – Revised July 2013 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter. This chapter describes the ADC12 of the MSP430x2xx device family. Topic 23.1 23.2 23.3 ........................................................................................................................... Page ADC12 Introduction ......................................................................................... 560 ADC12 Operation .........................
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ADC12 Introduction www.ti.com 23.1 ADC12 Introduction The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
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ADC12 Introduction www.ti.com REFON INCHx=0Ah REF2_5V VeREF+ on VREF+ AVCC INCHx AVSS 4 A0 A1 A2 A3 A4 A5 A6 A7 Floating Floating Floating Floating 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AVCC 1.5 V or 2.5 V Reference VREF−/VeREF− SREF2 1 Ref_x SREF1 SREF0 11 10 01 00 0 ADC12OSC ADC12SSELx ADC12ON ADC12DIVx VR+ VR− Sample and Hold 00 Divider /1 ...
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ADC12 Operation www.ti.com 23.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 23.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory. The core uses two programmable/selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion.
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ADC12 Operation www.ti.com 23.2.2.1 Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and, therefore, reduces overall current consumption.
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ADC12 Operation www.ti.com 23.2.4.1 Extended Sample Mode The extended sample mode is selected when SHP = 0. The SHI signal directly controls SAMPCON and defines the length of the sample period tsample. When SAMPCON is high, sampling is active. The high-tolow SAMPCON transition starts the conversion after synchronization with ADC12CLK (see Figure 23-3). Start Sampling Stop Sampling Conversion Complete Start Conversion SHI 13 x ADC12CLK SAMPCON tsample tconvert t sync ADC12CLK Figure 23-3.
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ADC12 Operation www.ti.com 23.2.4.3 Sample Timing Considerations When SAMPCON = 0, all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown in Figure 23-5. An internal MUX-on input resistance RI (maximum of 2 kΩ) in series with capacitor CI (maximum of 40 pF) is seen by the source. The capacitor CI voltage (VC) must be charged to within 1/2 LSB of the source voltage (VS) for an accurate 12-bit conversion.
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ADC12 Operation www.ti.com 23.2.6.1 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 23-6 shows the flow of the single-channel, single-conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each conversion.
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ADC12 Operation www.ti.com 23.2.6.2 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 23-7 shows the sequence-of-channels mode. When ADC12SC triggers a sequence, successive sequences can be triggered by the ADC12SC bit.
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ADC12 Operation www.ti.com 23.2.6.3 Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion, because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 23-8 shows repeat-single-channel mode.
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ADC12 Operation www.ti.com 23.2.6.4 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit, and the next trigger signal re-starts the sequence. Figure 23-9 shows the repeat-sequence-of-channels mode.
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ADC12 Operation www.ti.com 23.2.6.5 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed.
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ADC12 Operation www.ti.com Volts 1.300 1.200 1.100 1.000 0.900 VTEMP=0.00355(TEMPC)+0.986 0.800 0.700 Celsius −50 0 50 100 Figure 23-10. Typical Temperature Sensor Transfer Function 23.2.8 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
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ADC12 Operation www.ti.com Digital Power Supply Decoupling DVCC + 10 uF Analog Power Supply Decoupling 100 nF DVSS AV CC + AV SS 10 uF Using an External + Positive Reference 10 uF Using the Internal + Reference Generator 10 uF Using an External + Negative Reference 10 uF 100 nF Ve REF+ 100 nF VREF+ 100 nF VREF− / Ve REF− 100 nF Figure 23-11. ADC12 Grounding and Noise Considerations 23.2.
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ADC12 Operation www.ti.com 23.2.9.2 ADC12 Interrupt Handling Software Example Example 23-1 shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
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ADC12 Registers www.ti.com 23.3 ADC12 Registers The ADC12 registers are listed in Table 23-2. Table 23-2.
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ADC12 Registers www.ti.com 23.3.1 ADC12CTL0, ADC12 Control Register 0 15 14 13 12 11 10 SHT1x rw-(0) rw-(0) 9 8 rw-(0) rw-(0) SHT0x rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 MSC REF2_5V REFON ADC120N ADC12OVIE ADC12TOVIE ENC ADC12SC rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Can be modified only when ENC = 0 SHT1x Bits 15-12 SHT0x Bits 11-8 MSC Bit 7 REF2_5V Bit 6 Sample-and-hold time.
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ADC12 Registers REFON Bit 5 ADC12ON Bit 4 ADC12OVIE Bit 3 ADC12TOVIE Bit 2 ENC Bit 1 ADC12SC Bit 0 576 ADC12 www.ti.com Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC12 off 1 ADC12 on ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt.
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ADC12 Registers www.ti.com 23.3.
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ADC12 Registers www.ti.com 23.3.3 ADC12MEMx, ADC12 Conversion Memory Registers 15 14 13 12 0 0 0 0 11 10 9 8 r0 r0 r0 r0 rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw Conversion Results Conversion Results rw Conversion Results rw Bits 15-0 rw rw rw The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12 are always 0. Writing to the conversion memory registers corrupts the results. 23.3.
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ADC12 Registers www.ti.com 23.3.5 ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IFG9 ADC12IE8 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) ADC12IEx rw-(0) Bits 15-0 Interrupt enable.
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ADC12 Registers www.ti.com 23.3.
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Chapter 24 SLAU144J – December 2004 – Revised July 2013 TLV Structure The Tag-Length-Value (TLV) structure is used in selected MSP430x2xx devices to provide device-specific information in the device's flash memory SegmentA, such as calibration data. For the device-dependent implementation, see the device-specific data sheet. Topic 24.1 24.2 24.3 24.4 ........................................................................................................................... TLV Introduction ...............
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TLV Introduction www.ti.com 24.1 TLV Introduction The TLV structure stores device-specific data in SegmentA. The SegmentA content of an example device is shown in Table 24-1. Table 24-1.
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Supported Tags www.ti.com 24.2 Supported Tags Each device contains a subset of the tags shown in Table 24-2. See the device-specific data sheet for details. Table 24-2. Supported Tags (Device Specific) Tag Description Value TAG_EMPTY Identifies an unused memory area 0xFE TAG_DCO_30 Calibration values for the DCO at room temperature and DVCC = 3 V 0x01 TAG_ADC12_1 Calibration values for the ADC12 module 0x08 TAG_ADC10_1 Calibration values for the ADC10 module 0x08 24.2.
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Supported Tags www.ti.com 24.2.2 TAG_ADC12_1 Calibration TLV Structure The calibration data for the ADC12 module consists of eight words (see Table 24-4). Table 24-4.
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Supported Tags www.ti.com In 1. 2. 3. the example: 0x0100 × 0x0002 = 0x0200 0x0200 × 0x7BBB = 0x00F7_7600 0x00F7_7600 ÷ 0x0001_0000 = 0x0000_00F7 (= 247) The code example using the hardware multiplier follows. ; ; ; ; The ADC conversion result is stored in ADC12MEM0 It is assumed that R9 contains the address of the TAG_ADC12_1. The corrected value is available in ADC_COR MOV.W &ADC12MEM0,R10 ; move result to R10 RLA.W R10 ; R10 x 2 MOV.W R10,&MPY ; unsigned multiply OP1 MOV.
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Checking Integrity of SegmentA www.ti.com ; The corrected value is available in ADC_COR MOV.W &ADC12MEM0,R10 ; move result to R10 RLA.W R10 ; R10 * 2 MOV.W R10,&MPY ; unsigned multiply OP1 MOV.W CAL_ADC_GAIN_FACTOR(R9),&OP2 ; calibration value OP2 MOV.W &RESHI,&ADC_COR ; use upper 16-bit MPY ADD.W CAL_ADC_OFFSET(R9),&ADC_COR ; add offset correction 24.3 Checking Integrity of SegmentA The 64-byte SegmentA contains a 2-byte checksum of the data stored at 0x10C2 up to 0x10FF at addresses 0x10C0 and 0x10C1.
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Parsing TLV Structure of Segment A www.ti.com LP2 MOV.B ADD.
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Chapter 25 SLAU144J – December 2004 – Revised July 2013 DAC12 The DAC12 module is a 12-bit voltage-output digital-to-analog converter (DAC). This chapter describes the operation of the DAC12 module of the MSP430x2xx device family. Topic 25.1 25.2 25.3 588 DAC12 ........................................................................................................................... Page DAC12 Introduction .........................................................................................
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DAC12 Introduction www.ti.com 25.1 DAC12 Introduction The DAC12 module is a 12-bit voltage-output DAC. The DAC12 can be configured in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
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DAC12 Introduction www.ti.com Ve REF+ VREF+ To ADC12 module 2.5V or 1.
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DAC12 Operation www.ti.com 25.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 25.2.1 DAC12 Core The DAC12 can be configured to operate in 8-bit or 12-bit mode using the DAC12RES bit. The full-scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit. This feature allows the user to control the dynamic range of the DAC12.
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DAC12 Operation www.ti.com When DAC12LSELx = 0 the data latch is transparent and the DAC12_xDAT register is applied directly to the DAC12 core. the DAC12 output updates immediately when new DAC12 data is written to the DAC12_xDAT register, regardless of the state of the DAC12ENC bit. When DAC12LSELx = 1, DAC12 data is latched and applied to the DAC12 core after new data is written to DAC12_xDAT.
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DAC12 Operation www.ti.com Output Voltage 0 DAC Data Negative Offset Figure 25-4. Negative Offset When the output amplifier has a positive offset, a digital input of zero does not result in a zero output voltage. The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code. This is shown in Figure 25-5. Vcc Output Voltage 0 DAC Data Full-Scale Code Figure 25-5.
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DAC12 Operation www.ti.com DAC12_0 DAC12GRP DAC12_0 and DAC12_1 Updated Simultaneously DAC12_0 DAC12ENC TimerA_OUT1 DAC12_0DAT New Data DAC12_0 Updated DAC12_1DAT New Data DAC12_0 Latch Trigger DAC12_0 DAC12LSELx = 2 DAC12_0 DAC12LSELx > 0AND DAC12_1 DAC12LSELx = 2 Figure 25-6. DAC12 Group Update Example, Timer_A3 Trigger NOTE: DAC12 Settling Time The DMA controller is capable of transferring data to the DAC12 faster than the DAC12 output can settle.
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DAC12 Registers www.ti.com 25.3 DAC12 Registers The DAC12 registers are listed in Table 25-2. Table 25-2.
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DAC12 Registers www.ti.com 25.3.
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DAC12 Registers www.ti.com DAC12IFG Bit 2 DAC12ENC Bit 1 DAC12GRP Bit 0 DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending DAC12 enable conversion. This bit enables the DAC12 module when DAC12LSELx > 0. when DAC12LSELx = 0, DAC12ENC is ignored. 0 DAC12 disabled 1 DAC12 enabled DAC12 group. Groups DAC12_x with the next higher DAC12_x. Not used for DAC12_1. 0 Not grouped 1 Grouped 25.3.
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Chapter 26 SLAU144J – December 2004 – Revised July 2013 SD16_A The SD16_A module is a single-converter 16-bit sigma-delta analog-to-digital conversion module with high impedance input buffer. This chapter describes the SD16_A. The SD16_A module is implemented in the MSP430x20x3 devices. Topic 26.1 26.2 26.3 598 SD16_A ........................................................................................................................... Page SD16_A Introduction ....................................
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SD16_A Introduction www.ti.com 26.1 SD16_A Introduction The SD16_A module consists of one sigma-delta analog-to-digital converter with a high-impedance input buffer and an internal voltage reference. It has up to eight fully differential multiplexed analog input pairs including a built-in temperature sensor and a divided supply voltage. The converter is based on a secondorder oversampling sigma-delta modulator and digital decimation filter.
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SD16_A Introduction www.ti.com SD16REFON 0 VREF Reference 1.2V AV CC SD16SSELx SD16XDIVx SD16DIVx 1 AV SS Reference fM Divider 1/3/16/48 Divider 1/2/4/8 00 MCLK 01 SMCLK 10 ACLK 11 TACLK SD16VMIDON Start Conversion Logic SD16INCHx + − + − + − + − + − + − + − + − A0 A1 A2 A3 A4 A5 A6 A7 000 001 SD16BUFx† SD16OSRx SD16GAINx 010 011 100 BUF SD16SC SD16SNGL 15 2ndOrder Σ∆ Modulator PGA 1..32 0 SD16MEM0 101 SD16UNI SD16DF 110 111 SD16LP Reference SD16XOSR AVCC Temp.
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SD16_A Operation www.ti.com 26.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 26.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 26.2.
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SD16_A Operation www.ti.com During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the next decimation step of the digital filter. After these bits are modified, the next three conversions may be invalid due to the settling time of the digital filter. This can be handled automatically with the SD16INTDLYx bits. When SD16INTDLY = 00h, conversion interrupt requests will not begin until the fourth conversion after a start condition.
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SD16_A Operation www.ti.com Table 26-2. Sampling Capacitance PGA Gain Sampling Capacitance, CS 1 1.25 pF 2, 4 2.5 pF 8 5 pF 16, 32 10 pF 26.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC3 comb filter.
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SD16_A Operation www.ti.com Asynchronous Step 4 1 Synchronous Step 3 1 3 2 0.8 0.8 0.6 % VFSR 0.6 2 0.4 0.4 0.2 0.2 1 1 0 0 Conversion Conversion Figure 26-4. Digital Filter Step Response and Conversion Points 26.2.7.1 Digital Filter Output The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 26-5 shows the digital filter output and their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNI setting.
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SD16_A Operation www.ti.
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SD16_A Operation www.ti.
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SD16_A Operation www.ti.com 26.2.8 Conversion Memory Register: SD16MEM0 The SD16MEM0 register is associated with the SD16_A channel. Conversion results are moved to the SD16MEM0 register with each decimation step of the digital filter. The SD16IFG bit is set when new data is written to SD16MEM0. SD16IFG is automatically cleared when SD16MEM0 is read by the CPU or may be cleared with software. 26.2.8.
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SD16_A Operation www.ti.com 26.2.9 Conversion Modes The SD16_A module can be configured for two modes of operation, listed in Table 26-4. The SD16SNGL bit selects the conversion mode. Table 26-4. Conversion Mode Summary SD16SNGL Mode 1 Single conversion Operation 0 Continuous conversion The channel is converted once. The channel is converted continuously. 26.2.9.1 Single Conversion Setting the SD16SC bit of the channel initiates one conversion on that channel when SD16SNGL = 1.
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SD16_A Operation www.ti.com Volts 0.500 0.450 0.400 0.350 VSensor,typ = TCSensor(273 + T[oC]) + VOffset, sensor [mV] 0.300 0.250 0.200 Celsius 0 −50 50 100 Figure 26-8. Typical Temperature Sensor Transfer Function 26.2.11 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel: • SD16IFG • SD16OVIFG The SD16IFG bit is set when the SD16MEM0 memory register is written with a conversion result.
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SD16_A Operation www.ti.com 26.2.11.2 Interrupt Delay Operation The SD16INTDLYx bits control the timing for the first interrupt service request for the corresponding channel. This feature delays the interrupt request for a completed conversion by up to four conversion cycles allowing the digital filter to settle prior to generating an interrupt request. The delay is applied each time the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the channel are modified.
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SD16_A Registers www.ti.com 26.3 SD16_A Registers The SD16_A registers are listed in Table 26-5. Table 26-5.
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SD16_A Registers www.ti.com 26.3.
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SD16_A Registers www.ti.com 26.3.
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SD16_A Registers SD16SC Bit 1 Reserved Bit 0 www.ti.com SD16_A start conversion 0 No conversion start 1 Start conversion Reserved 26.3.3 SD16INCTL0, SD16_A Input Control Register 7 6 5 4 rw-0 rw-0 SD16INTDLYx rw-0 SD16INTDLYx Bits 7-6 SD16GAINx Bits 5-3 SD16INCHx Bits 2-0 614 SD16_A 3 2 rw-0 rw-0 SD16GAINx rw-0 1 0 SD16INCHx rw-0 rw-0 Interrupt delay generation after conversion start. These bits select the delay for the first interrupt after conversion start.
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SD16_A Registers www.ti.com 26.3.4 SD16MEM0, SD16_A Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r 7 6 5 r r r r r 4 3 2 1 0 r r r Conversion Results r Conversion Results r Bits 15-0 r r r Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit. 26.3.
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Chapter 27 SLAU144J – December 2004 – Revised July 2013 SD24_A The SD24_A module is a multichannel 24-bit sigma-delta analog-to-digital converter (ADC). This chapter describes the SD24_A of the MSP430x2xx family. Topic 27.1 27.2 27.3 616 SD24_A ........................................................................................................................... Page SD24_A Introduction ........................................................................................ 617 SD24_A Operation .
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SD24_A Introduction www.ti.com 27.1 SD24_A Introduction The SD24_A module consists of up to seven independent sigma-delta analog-to-digital converters, referred to as channels, and an internal voltage reference. Each channel has up to eight fully differential multiplexed analog input pairs including a built-in temperature sensor and a divided supply voltage. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters.
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SD24_A Introduction www.ti.com SD24_A Control Block SD24REFON 0 VREF Reference 1.2V SD24SSELx AVCC SD24XDIVx SD24DIVx 00 1 AVSS Reference fM Divider 1/3/16/48 Divider 1/2/4/8 MCLK 01 SMCLK 10 ACLK 11 TACLK SD24VMIDON Channel 0 Conversion Control (to prior channel) Group/Start Conversion Logic SD24INCHx A1.0 A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.
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SD24_A Operation www.ti.com 27.2 SD24_A Operation The SD24_A module is configured with user software. The setup and operation of the SD24_A is discussed in the following sections. 27.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency fM. The resulting 1-bit data stream is averaged by the digital filter for the conversion result. 27.2.
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SD24_A Operation www.ti.com The SD24INCHx bits select one of eight differential input pairs of the analog multiplexer. The gain for each PGA is selected by the SD24GAINx bits. A total of six gain settings are available. On some devices SD24AEx bits are available to enable or disable the analog input pin. Setting any SD24AEx bit disables the multiplexed digital circuitry for the associated pin. See the device-specific data sheet for pin diagrams.
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SD24_A Operation www.ti.com When the buffers are used, RS does not affect the sampling frequency fS. However, when the buffers are not used or are not present on the device, the maximum modulator frequency fM may be calculated from the minimum settling time tSettling of the sampling circuit given by: æ GAIN × 217 × V Ax tSettling ³ (RS + 1 kW) × CS × ln ç ç VREF è ö ÷ ÷ ø Where, fM = 1 2 × tSettling æ AVCC ö AVCC and VAx = max çç – VS+ , – VS– ÷÷ 2 2 è ø with VS+ and VS- referenced to AVSS.
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SD24_A Operation www.ti.com 0 −20 GAIN [dB] −40 −60 −80 −100 −120 −140 fS fM Frequency Figure 27-3. Comb Filter Frequency Response With OSR = 32 Figure 27-4 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD24INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
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SD24_A Operation www.ti.com 27.2.7.1 Digital Filter Output The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 27-5 shows the digital filter output and their relation to SD24MEMx for each OSR, LSBACC, and SD24UNI setting. For example, for OSR = 1024, LSBACC = 0, and SD24UNI = 1, the SD24MEMx register contains bits 28 to 13 of the digital filter output. When OSR = 32, the one (SD24UNI = 0) or two (SD24UNI = 1) LSBs are always zero.
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SD24_A Operation www.ti.
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SD24_A Operation www.ti.com 27.2.8 Conversion Memory Register: SD24MEMx One SD24MEMx register is associated with each SD24_A channel. Conversion results are moved to the corresponding SD24MEMx register with each decimation step of the digital filter. The SD24IFG bit is set when new data is written to SD24MEMx. SD24IFG is automatically cleared when SD24MEMx is read by the CPU or may be cleared with software. 27.2.8.
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SD24_A Operation www.ti.com 27.2.9 Conversion Modes The SD24_A module can be configured for four modes of operation, listed in Table 27-4. The SD24SNGL and SD24GRP bits for each channel selects the conversion mode. Table 27-4. Conversion Mode Summary (1) SD24SNGL SD24GRP (1) 1 0 Single channel, Single conversion Mode A single channel is converted once. Operation 0 0 Single channel, Continuous conversion A single channel is converted continuously.
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SD24_A Operation www.ti.com 27.2.9.3 Group of Channels, Single Conversion Consecutive SD24_A channels can be grouped together with the SD24GRP bit to synchronize conversions. Setting SD24GRP for a channel groups that channel with the next channel in the module. For example, setting SD24GRP for channel 0 groups that channel with channel 1. In this case, channel 1 is the master channel, enabling and disabling conversion of all channels in the group with its SD24SC bit.
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SD24_A Operation www.ti.com 27.2.10 Conversion Operation Using Preload When multiple channels are grouped the SD24PREx registers can be used to delay the conversion time frame for each channel. Using SD24PREx, the decimation time of the digital filter is increased by the specified number of fM clock cycles and can range from 0 to 255. Figure 27-9 shows an example using SD24PREx.
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SD24_A Operation www.ti.com (syncronized to master) Channel 0 SD24SNGL = 0 SD24GRP = 1 Channel 1 SD24SNGL = 1 SD24GRP = 1 Channel 2 SD24SNGL = 0 SD24GRP = 0 PRE0 SD24SC Conversion Set by Ch2 PRE0 PRE1 Auto−clear Conversion SD24SC Conv Conv Cleared by SW Set by SW (syncronized to master) Set by Ch2 PRE1 SD24SC Conversion Conversion Set by SW Conversion Auto−clear Conversion Conv Conversion Set by SW Time = Result written to SD24MEMx Figure 27-11.
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SD24_A Operation www.ti.com 27.2.12 Interrupt Handling The SD24_A has 2 interrupt sources for each ADC channel: • SD24IFG • SD24OVIFG The SD24IFG bits are set when their corresponding SD24MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD24IE bit and the GIE bit are set. The SD24_A overflow condition occurs when a conversion result is written to any SD24MEMx location before the previous conversion result was read. 27.2.12.
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SD24_A Operation www.ti.com 27.2.12.3 SD24_A Interrupt Handling Software Example The following software example shows the recommended use of SD24IV and the handling overhead. The SD24IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself.
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SD24_A Registers www.ti.com 27.3 SD24_A Registers The SD24_A registers are listed in Table 27-5 (registers for channels not implemented are unavailable; see the device-specific data sheet). Table 27-5.
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SD24_A Registers www.ti.com 27.3.
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SD24_A Registers www.ti.com 27.3.
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SD24_A Registers www.ti.com SD24IFG Bit 2 SD24SC Bit 1 SD24GRP Bit 0 SD24_A interrupt flag. SD24IFG is set when new conversion results are available. SD24IFG is automatically reset when the corresponding SD24MEMx register is read, or may be cleared with software. 0 No interrupt pending 1 Interrupt pending SD24_A start conversion 0 No conversion start 1 Start conversion SD24_A group. Groups SD24_A channel with next higher channel. Not used for the last channel. 0 Not grouped 1 Grouped 27.3.
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SD24_A Registers www.ti.com 27.3.4 SD24MEMx, SD24_A Channel x Conversion Memory Register 15 14 13 12 11 10 9 8 Conversion Results r r r 7 6 5 r r r r r 4 3 2 1 0 r r r Conversion Results r Conversion Results r Bits 15-0 r r r Conversion results. The SD24MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD24LSBACC bit. 27.3.
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SD24_A Registers www.ti.com 27.3.
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Chapter 28 SLAU144J – December 2004 – Revised July 2013 Embedded Emulation Module (EEM) This chapter describes the Embedded Emulation Module (EEM) that is implemented in all MSP430 flash devices. Topic 28.1 28.2 28.3 638 ........................................................................................................................... Page EEM Introduction ............................................................................................. 639 EEM Building Blocks .....................
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EEM Introduction www.ti.com 28.1 EEM Introduction Every MSP430 flash-based microcontroller implements an embedded emulation module (EEM). It is accessed and controlled through JTAG. Each implementation is device dependent and is described in section 1.3 EEM Configurations and the device-specific data sheet.
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EEM Introduction www.ti.com Trigger Blocks ”AND” Matrix − CombinationTriggers 0 1 2 3 4 5 6 7 & & & & & & & & MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 CPU0 CPU1 Trigger Sequencer OR CPU Stop OR Start/Stop State Storage Figure 28-1.
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EEM Building Blocks www.ti.com 28.2 EEM Building Blocks 28.2.1 Triggers The event control in the EEM of the MSP430 system consists of triggers, which are internal signals indicating that a certain event has happened. These triggers may be used as simple breakpoints, but it is also possible to combine two or more triggers to allow detection of complex events and trigger various reactions besides stopping the CPU.
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EEM Configurations www.ti.com 28.3 EEM Configurations Table 28-1 gives an overview of the EEM configurations in the MSP430 2xx family. The implemented configuration is device dependent - see the device data sheet. Table 28-1.
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Revision History www.ti.com Revision History Revision SLAU144G Comments Chapter 5 Basic Clock Module+, Added information specific to the MSP430AFE2xx devices: Figure 5-2. Basic Clock Module+ Block Diagram − MSP430AFE2xx Section 5.3, Register BCSCTL3 default Section 5.3.2, 5.3.3, 5.3.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.