Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 32 (5x5) 16-Bit 16 MHz I/O number 24

MSP430F21x2

www.ti.com

SLAS578J –NOVEMBER 2007– REVISED JANUARY 2012

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V

• Universal Serial Communication Interface

• Ultra-Low Power Consumption – Enhanced UART Supporting Auto-Baudrate

Detection (LIN)

– Active Mode: 250 µA at 1 MHz, 2.2 V

– IrDA Encoder and Decoder

– Standby Mode: 0.7 µA

– Synchronous SPI

– Off Mode (RAM Retention): 0.1 µA

– I

C™

• Ultra-Fast Wake-Up From Standby Mode in

Less Than 1 µs • Brownout Detector

• 16-Bit RISC Architecture, 62.5-ns Instruction • Serial Onboard Programming, No External

Cycle Time Programming Voltage Needed, Programmable

Code Protection by Security Fuse

• Basic Clock Module Configurations

• Bootstrap Loader

– Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% • On-Chip Emulation Module

– Internal Very-Low-Power Low-Frequency • Family Members Include:

Oscillator

– MSP430F2132

– 32-kHz Crystal

– 8KB + 256B Flash Memory

– High-Frequency (HF) Crystal up to 16 MHz

– 512B RAM

– Resonator

– MSP430F2122

– External Digital Clock Source

– 4KB + 256B Flash Memory

– External Resistor

– 512B RAM

• 16-Bit Timer0_A3 With Three Capture/Compare

– MSP430F2112

Registers

– 2KB + 256B Flash Memory

• 16-Bit Timer1_A2 With Two Capture/Compare

– 256B RAM

Registers

• Available in 28-Pin TSSOP (PW) and 32-Pin

• On-Chip Comparator for Analog Signal

QFN (RHB or RTV) Packages (See Table 1)

Compare Function or Slope Analog-to-Digital

• For Complete Module Descriptions, See the

(A/D) Conversion

MSP430x2xx Family User's Guide, Literature

• 10-Bit 200-ksps A/D Converter With Internal

Number SLAU144

Reference, Sample-and-Hold, Autoscan, and

Data Transfer Controller

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430F21x2 series is an ultra-low-power microcontroller with two built-in 16-bit timers, a fast 10-bit A/D

converter with integrated reference and a data transfer controller (DTC), a comparator, built-in communication

capability using the universal serial communication interface, and up to 24 I/O pins.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (80 pages)

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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 2 • • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 250 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.1 µA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Device Pinout, PW Package TEST/SBWTCK DVCC P2.5/ROSC/CA5 DVSS XOUT/P2.7/CA7 XIN/P2.6/CA6 RST/NMI/SBWTDIO P2.0/ACLK/A0/CA2 P2.1/TAINCLK/SMCLK/A1/CA3 P2.2/TA0.0/A2/CA4/CAOUT P3.0/UCB0STE/UCA0CLK/A5 P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P1.7/TA0.2/TDO/TDI P1.6/TA0.1/TDI/TCLK P1.5/TA0.0/TMS P1.4/SMCLK/TCK P1.3/TA0.2 P1.2/TA0.1 P1.1/TA0.0/TA1.0 P1.0/TACLK/ADC10CLK/CAOUT P2.4/TA0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Functional Block Diagram XOUT XIN DVCC D/AVSS AVCC P3.x P2.x P1.x 8 8 8 ACLK Basic Clock System+ SMCLK Flash RAM 8kB 4kB 2kB 512B 512B 256B MCLK 16MHz CPU incl.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME PW I/O DESCRIPTION RHB, RTV General-purpose digital I/O pin Timer0_A3, clock signal TACLK input P1.0/TACLK/ADC10CLK/CAOUT 21 21 I/O Timer1_A2, clock signal TACLK input ADC10, conversion clock Comparator_A+ output General-purpose digital I/O pin P1.1/TA0.0/TA1.0 22 22 I/O Timer0_A3, capture: CCI0A input, compare: Out0 Output Timer1_A2, capture: CCI0A input P1.2/TA0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME PW I/O DESCRIPTION RHB, RTV General-purpose digital I/O pin P2.4/TA0.2/A4/VREF+/VeREF+/CA1 20 19 I/O Timer0_A3, compare: Out2 Output ADC10 analog input A4 / positive reference Comparator_A+ input Input terminal of crystal oscillator XIN/P2.6/CA6 6 3 I/O General-purpose digital I/O pin Comparator_A+ input Output terminal of crystal oscillator XOUT/P2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 5.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Memory Organization Table 10.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
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MSP430F21x2 www.ti.com SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There are three 8-bit I/O ports implemented—ports P1, P2, and P3: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt condition is possible. • Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Timer1_A2 Timer1_A2 is a 16-bit timer/counter with two capture/compare registers. Timer1_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Peripheral File Map Table 16.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Table 17.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to VCC + 0.3 V ±2 mA Diode current at any device terminal Storage temperature, Tstg (1) (3) Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Active Mode Supply Current (into DVCC + AVCC ) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TEST CONDITIONS TA VCC MIN TYP MAX 2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - LPM4 Current LPM4 CURRENT vs TEMPERATURE ILPM4 − Low-Power Mode Current − µA 2.4 VCC = 3.6 V 2.2 VCC = 3 V 2.0 VCC = 2.2 V 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −40.0 −20.0 VCC = 1.8 V 0.0 20.0 40.0 60.0 80.0 100.0 TA − Temperature − °C Figure 4.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Outputs (Ports P1, P2, P3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage IOH(max) = -6 mA (2) IOH(max) = -1.5 mA (1) IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) 2.2 V 3V (1) 2.2 V IOL(max) = 6 mA (2) IOL(max) = 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P2.4 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 40.0 TA = 85°C 30.0 20.0 10.0 0.0 0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 25°C 3V 0.990 1 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 TA = 85 °C 1.02 Frequency − MHz TA = 25 °C 1.01 TA = 105 °C 1.00 TA = −40 °C 0.99 0.98 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC − Supply Voltage − V Figure 12.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 (1) (2) UNIT 2 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ 2.2 V/3 V 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - DCO With External Resistor ROSC DCO FREQUENCY vs ROSC VCC = 2.2 V, TA = 25°C DCO FREQUENCY vs ROSC VCC = 3 V, TA = 25°C 10.00 DCO Frequency − MHz DCO Frequency − MHz 10.00 1.00 0.10 RSELx = 4 0.01 10.00 100.00 1000.00 1.00 0.10 RSELx = 4 0.01 10.00 10000.00 ROSC − External Resistor − kW Figure 15. DCO FREQUENCY vs TEMPERATURE VCC = 3 V DCO FREQUENCY vs SUPPLY VOLTAGE TA = 25°C 2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, XCAPx = 0, LFXT1Sx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, XCAPx = 0, LFXT1Sx = 1 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, XCAPx = 0, LFXT1Sx = 2 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 100000.00 1800.0 LFXT1Sx = 2 10000.00 1000.00 LFXT1Sx = 2 100.00 XT Oscillator Supply Current − uA Oscillation Allowance − Ohms 1600.0 1400.0 1200.0 1000.0 800.0 600.0 400.0 LFXT1Sx = 1 LFXT1Sx = 1 200.0 LFXT1Sx = 0 10.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fmax,BITCLK Maximum BITCLK clock frequency (equals baud rate in MBaud) (1) tτ UART receive deglitch time (2) (1) (2) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V/3 V 2 2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 20. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 21.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 22. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 23.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.0/CA0 and P1.1/CA1 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT µA µA VIC Common-mode input voltage range CAON = 1 2.2 V/3 V 0 V(Ref025) Voltage at 0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com 0V VCC 0 1 CAF CAON To Internal Modules Low-Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 25. Comparator_A+ Module Block Diagram VCAOUT Overdrive V− 400 mV t (response) V+ Figure 26. Overdrive Definition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 27.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Typical Characteristics - Comparator_A+ V(RefVT) vs TEMPERATURE VCC = 2.2 V V(RefVT) vs TEMPERATURE VCC = 2.2 V 650 650.0 VCC = 2.2 V V(REFVT) − Reference Volts − mV V(REFVT) − Reference Volts − mV VCC = 3 V 600.0 Typical 550.0 500.0 450.0 400.0 −45.0 −25.0 −5.0 15.0 35.0 55.0 600 Typical 550 500 450 400 −45 75.0 95.0 115.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com 10-Bit ADC, Built-In Voltage Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC,REF+ TEST CONDITIONS IVREF+ ≤ 1 mA, REF2_5V = 0 Positive built-in reference analog IVREF+ ≤ 0.5 mA, REF2_5V = 1 supply voltage range IVREF+ ≤ 1 mA, REF2_5V = 1 VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VREF+ load regulation 2.2 V/3 V 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com 10-Bit ADC, External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (2) MIN MAX VeREF+ > VeREF-, SREF1 = 1, SREF0 = 0 1.4 VCC VeREF- ≤ VeREF+ ≤ (VCC - 0.15 V), SREF1 = 1, SREF0 = 1 (3) 1.4 3 0 1.2 V 1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 2.2 V/3 V ±1 LSB ED Differential linearity error 2.2 V/3 V ±1 LSB EO Offset error 2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V/3 V 0.025 15 µs tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0, Input/Output With Schmitt Trigger Pad Logic P1REN.0 0 P1DIR.0 P1SEL2.0 0 from Comparator 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 ADC10CLK DVSS 1 P1OUT.0 0 P1.0/TACLK/ ADC10CLK/CAOUT Bus Keeper EN P1SEL.0 P1IN.0 EN Module X IN D P1IE.x EN P1IRQ.0 Q Set P1IFG.x P1SEL.0 P1IES.0 Interrupt Edge Select Table 18. Port P1 (P1.0) Pin Functions PIN NAME (P1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P1 Pin Schematic: P1.1 to P1.3, Input/Output With Schmitt Trigger Pad Logic P1REN.x 0 P1DIR.x 1 P1OUT.x 0 0 DVCC 1 1 Direction 0: Input 1: Output 1 Timer0_A3 output DVSS P1.1/TA0_0/TA0_1 P1.2/TA1_0 P1.3/TA2_0 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x Interrupt Edge Select P1IES.x Table 19. Port P1 (P1.1 to P1.3) Pin Functions PIN NAME (P1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P1 Pin Schematic: P1.4 P1REN.4 Pad Logic P1DIR.4 0 1 P1OUT.x 0 0 DVCC 1 1 Direction 0: Input 1: Output 1 SMCLK DVSS P1.4/SMCLK/TCK Bus Keeper EN P1SEL.4 P1IN.4 EN Module X IN D P1IE.x P1IRQ.4 EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select To JTAG From JTAG Table 20. Port P1 (P1.4) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.4 (I/O) P1.4/SMCLK/TCK (1) (2) 4 P1DIR.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P1 Pin Schematic: P1.5 to P1.7 P1REN.x Pad Logic P1DIR.x 0 1 P1OUT.x 0 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X Out DVSS P1.5/TA0.0/TMS P1.6/TA0.1/TCLK P1.7/TA0.2/TDO/TDI Bus Keeper EN P1SEL.x P1IN.x EN Module X In D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge Select P1IES.x To JTAG From JTAG Table 21. Port P1 (P1.5 to P1.7) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.0 and P2.1, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = y To Comparator_A From Comparator_A CAPD.x ADC10AE0.y P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction 0: Input 1: Output 1 P2OUT.x 0 Module X OUT 1 P2.0/ACLK/A0/CA2 P2.1/TAINCLK/ SMCLK/A1/CA3 Bus Keeper EN P2SEL.x P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Table 22.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.2, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = y To Comparator_A From Comparator_A CAPD.x ADC10AE0.y P2REN.x DVSS 0 DVCC 1 1 P2DIR.2 0 P2SEL2.2 1 Module output 0 From Comparator 1 Direction 0: Input 1: Output 1 0 P2OUT.2 P2.2/TA0.0/A2/CA4/CAOUT Bus Keeper EN P2SEL.2 P2IN.2 EN Module X IN D P2IE.x EN P2IRQ.2 Q Set P2IFG.x P2SEL.x Interrupt Edge Select P2IES.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.3 and P2.4, Input/Output With Schmitt Trigger Pad Logic To/from ADC10 Reference To ADC10 INCHx = y To Comparator_A From Comparator_A CAPD.x ADC10AE0.y P2REN.x DVSS 0 DVCC 1 1 P2DIR.x 0 Direction 0: Input 1: Output 1 P2OUT .x Module X OUT 0 1 P2.3/TA0.1/A3/ VREF−/VeREF−/CA0 Bus Keeper EN P2SEL.x P2IN.x P2.4/TA0.2/A4/ VREF+/VeREF+/CA1 EN Module X IN D P2IE.x P2IRQ.x EN Q Set P2IFG.x P2SEL.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Table 24. Port P2 (P2.3 and P2.4) Pin Functions (continued) CONTROL BITS / SIGNALS (1) PIN NAME (P2.x) P2.4/TA0.2/A4/ VREF+/VeREF+/CA1 56 x 4 FUNCTION ADC10AE0.y CAPD.x P2DIR.x P2SEL.x P2SEL2.x = 0 P2.4 (I/O) 0 0 I: 0; O: 1 0 Timer0_A3.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.x To DCO DCOR in DCO P2REN.x P2DIR.5 0 P2OUT.5 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.x P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q P2IFG.5 P2SEL.5 P2IES.5 Set Interrupt Edge Select Table 25. Port P2 (P2.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx = 11 P2.7/XOUT/CA7 LFXT1 off 0 LFXT1CLK 1 Pad Logic To Comparator From Comparator P2SEL.7 CAPD.6 P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS DVCC P2.6/XIN/CA6 Bus Keeper EN P2SEL.6 P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 P2SEL.6 P2IES.6 Set Interrupt Edge Select Table 26.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx = 11 P2.6/XIN/CA6 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 Pad Logic To Comparator From Comparator P2SEL.6 CAPD.7 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS DVCC P2.7/XOUT/CA7 Bus Keeper EN P2SEL.7 P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 Set Interrupt Edge Select P2SEL.7 P2IES.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = y ADC10AE0.y P3REN.x P3DIR.x Module direction 0 P3OUT.x 0 Module X OUT 1 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.0/UCB0STE/ UCA0CLK/A5 Bus Keeper EN P3SEL.x P3IN.x Table 28. Port P3 (P3.0) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P3.x) P3.0/UCB0STE/ UCA0CLK/A5 (1) (2) 60 x 0 FUNCTION ADC10AE0.y P3DIR.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x Module direction 0 P3OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI Bus Keeper EN P3SEL.x P3IN.x EN Module X IN D Table 29. Port P3 (P3.1 to P3.5) Pin Functions PIN NAME (P3.x) P3.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com Port P3 Pin Schematic: P3.6 and P3.7, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = y ADC10AE0.y P3REN.x 0 P3DIR.x P3OUT.x 0 1 0 DVCC 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P3.6/TA0_1/A6 P3.7/TA1_1/A7 Bus Keeper EN P3SEL.x P3IN.x Table 30. Port P3 (P3.6 and P3.7) Pin Functions PIN NAME (P3.x) P3.6/TA1.0/A6 P3.7/TA1.1/A7 (1) 62 x 6 7 FUNCTION CONTROL BITS / SIGNALS (1) ADC10AE0.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
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MSP430F21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 www.ti.com REVISION HISTORY LITERATURE NUMBER SUMMARY SLAS578 Product Preview data sheet release SLAS578A Production Data data sheet release SLAS578B Corrected timer pin names throughout: TA0_0 changed to TA0.0, TA0_1 changed to TA1.0, TA1_0 changed to TA0.1, TA2_0 changed to TA0.2, TA1_1 changed to TA1.1 Added development tool information (page 2). SLAS578C Corrected TAG_ADC10_1 value from 0x10 to 0x08 (page 14).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing MSP430F2112IRTVR WQFN RTV 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F2112IRTVT WQFN RTV 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F2112TRTVR WQFN RTV 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2112IRTVR WQFN RTV 32 3000 367.0 367.0 35.0 MSP430F2112IRTVT WQFN RTV 32 250 210.0 185.0 35.0 MSP430F2112TRTVR WQFN RTV 32 3000 367.0 367.0 35.0 MSP430F2112TRTVT WQFN RTV 32 250 210.0 185.0 35.0 MSP430F2122IRTVR WQFN RTV 32 3000 367.0 367.0 35.0 MSP430F2122IRTVT WQFN RTV 32 250 210.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.