MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 23 • • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 270 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.1 µA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 MSP430F22x2 Device Pinout, DA Package TEST/SBWTCK 1 38 P1.7/TA2/TDO/TDI DVCC 2 37 P1.6/TA1/TDI P2.5/ROSC 3 36 P1.5/TA0/TMS DVSS 4 35 P1.4/SMCLK/TCK XOUT/P2.7 5 34 P1.3/TA2 XIN/P2.6 6 33 P1.2/TA1 RST/NMI/SBWTDIO 7 32 P1.1/TA0 P2.0/ACLK/A0 8 31 P1.0/TACLK/ADC10CLK P2.1/TAINCLK/SMCLK/A1 9 30 P2.4/TA2/A4/VREF+/VeREF+ P2.2/TA0/A2 10 29 P2.3/TA1/A3/VREF−/VeREF− P3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI TEST/SBWTCK DVCC DVCC P2.5/ROSC MSP430F22x2 Device Pinout, RHA Package 39 38 37 36 35 34 33 32 DVSS 1 30 P1.1/TA0 XOUT/P2.7 2 29 P1.0/TACLK/ADC10CLK XIN/P2.6 3 28 P2.4/TA2/A4/VREF+/VeREF+ DVSS 4 27 P2.3/TA1/A3/VREF−/VeREF− RST/NMI/SBWTDIO 5 26 P3.7/A7 P2.0/ACLK/A0 6 25 P3.6/A6 P2.1/TAINCLK/SMCLK/A1 7 24 P3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI TEST/SBWTCK DVCC DVCC P2.5/ROSC MSP430F22x4 Device Pinout, RHA Package 39 38 37 36 35 34 33 32 P1.1/TA0 DVSS 1 30 XOUT/P2.7 2 29 P1.0/TACLK/ADC10CLK XIN/P2.6 3 28 P2.4/TA2/A4/VREF+/VeREF+/OA1I0 DVSS 4 27 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O RST/NMI/SBWTDIO 5 26 P3.7/A7/OA1I2 P2.0/ACLK/A0/OA0I0 6 25 P3.6/A6/OA0I2 P2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 TOP VIEW D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Package Dimensions The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this data sheet for more details. Table 2.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 MSP430F22x2 Functional Block Diagram VCC P1.x/P2.x VSS 2x8 XIN P3.x/P4.x 2x8 XOUT Basic Clock System+ ACLK SMCLK MCLK Flash RAM 32kB 16kB 8kB 1kB 512B 512B ADC10 10−Bit Ports P1/P2 Ports P3/P4 2x8 I/O Interrupt capability, pull−up/down resistors 12 Channels, Autoscan, DTC 2x8 I/O pull−up/down resistors MAB 16MHz CPU incl.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions, MSP430F22x2 TERMINAL NAME NO. I/O YFF DA RHA F2 31 29 DESCRIPTION General-purpose digital I/O pin P1.0/TACLK/ADC10CLK I/O Timer_A, clock signal TACLK input ADC10, conversion clock General-purpose digital I/O pin P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output BSL transmit P1.2/TA1 E2 33 31 I/O P1.3/TA2 G1 34 32 I/O P1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Table 3. Terminal Functions, MSP430F22x2 (continued) TERMINAL NAME XOUT/P2.7 NO. I/O YFF DA RHA A1 5 2 I/O DESCRIPTION Output terminal of crystal oscillator General-purpose digital I/O pin (2) General-purpose digital I/O pin P3.0/UCB0STE/UCA0CLK/ A5 B5 11 9 I/O USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin P3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 3. Terminal Functions, MSP430F22x2 (continued) TERMINAL NAME NO. I/O YFF DA RHA P4.7/TBCLK F5 24 22 I/O RST/NMI/SBWTDIO B3 7 5 I TEST/SBWTCK D1 1 37 I DESCRIPTION General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Table 4. Terminal Functions, MSP430F22x4 TERMINAL NAME NO. I/O YFF DA RHA F2 31 29 DESCRIPTION General-purpose digital I/O pin P1.0/TACLK/ADC10CLK I/O Timer_A, clock signal TACLK input ADC10, conversion clock General-purpose digital I/O pin P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output BSL transmit P1.2/TA1 E2 33 31 I/O P1.3/TA2 G1 34 32 I/O P1.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 4. Terminal Functions, MSP430F22x4 (continued) TERMINAL NAME NO. YFF DA I/O DESCRIPTION RHA General-purpose digital I/O pin Timer_A, compare: OUT2 output P2.4/TA2/A4/ VREF+/VeREF+/OA1I0 G3 30 28 I/O ADC10, analog input A4 Positive reference voltage output or input OA1, analog input I/O P2.5/ROSC C2 3 40 I/O XIN/P2.6 A2 6 3 I/O XOUT/P2.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Table 4. Terminal Functions, MSP430F22x4 (continued) TERMINAL NAME NO. YFF DA I/O DESCRIPTION RHA General-purpose digital I/O pin P4.3/TB0/A12/OA0O E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 OA0 analog output General-purpose digital I/O pin P4.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 7.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Memory Organization Table 12.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Operational Amplifier (OA) (MSP430F22x4 only) The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion. Table 17.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Peripheral File Map Table 19.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 20.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Table 20.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature, Tstg (1) ±2 mA (3) Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Active Mode Supply Current (into DVCC + AVCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz TEST CONDITIONS TA MIN TYP MAX 2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC) ACTIVE-MODE CURRENT vs SUPPLY VOLTAGE TA = 25°C ACTIVE-MODE CURRENT vs DCO FREQUENCY 5.0 8.0 f DCO = 16 MHz 7.0 TA = 85 °C Active Mode Current − mA Active Mode Current − mA 4.0 6.0 f DCO = 12 MHz 5.0 4.0 f DCO = 8 MHz 3.0 2.0 TA = 25 °C 3.0 VCC = 3 V 2.0 TA = 85 °C TA = 25 °C 1.0 1.0 0.0 1.5 2.0 2.5 3.0 3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0,1MHz ILPM0,100kHz ILPM2 ILPM3,LFXT1 TEST CONDITIONS TA (1) (2) (3) (4) (5) TYP MAX 2.2 V 75 90 Low-power mode 0 (LPM0) current (3) 3V 90 120 2.
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MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Outputs (Ports P1, P2, P3, and P4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage IOH(max) = -6 mA (2) IOH(max) = -1.5 mA (1) IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) 2.2 V 3V (1) 2.2 V IOL(max) = 6 mA (2) IOL(max) = 1.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P4.5 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P4.5 40.0 TA = 85°C 30.0 20.0 10.
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MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO . Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 % 25°C 3V 0.990 1 1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs TEMPERATURE CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 1.03 1.02 1.02 Frequency − MHz 1.01 1.00 VCC = 2.2 V VCC = 3.0 V 0.99 Frequency − MHz VCC = 1.8 V TA = 105 °C 1.01 TA = 85 °C 1.00 TA = 25 °C 0.99 TA = −40 °C VCC = 3.6 V 0.98 0.98 0.97 −50.0 −25.0 0.0 25.0 50.0 TA − Temperature − °C Figure 11. 38 75.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ (1) (2) UNIT 2 2.2 V, 3 V 1.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25°C DT Temperature drift DV Drift with VCC (1) VCC MIN TYP MAX UNIT 2.2 V 1.8 3V 1.95 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V ±0.
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MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 2.2 V to 3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 800.0 100000.00 LFXT1Sx = 3 10000.00 1000.00 LFXT1Sx = 3 100.00 LFXT1Sx = 1 LFXT1Sx = 2 XT Oscillator Supply Current − uA Oscillation Allowance − Ohms 700.0 600.0 500.0 400.0 300.0 LFXT1Sx = 2 200.0 100.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) tτ UART receive deglitch time (1) (1) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V, 3 V MAX UNIT fSYSTEM MHz 1 MHz 2.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 20. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 21.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 22. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 23.
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MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 10-Bit ADC, Built-In Voltage Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC,REF+ TEST CONDITIONS VCC IVREF+ ≤ 1 mA, REF2_5V = 0 Positive built-in reference analog IVREF+ ≤ 0.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com 10-Bit ADC, External Reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (2) MIN MAX VeREF+ > VeREF-, SREF1 = 1, SREF0 = 0 1.4 VCC VeREF-≤ VeREF+ ≤ VCC - 0.15 V, SREF1 = 1, SREF0 = 1 (3) 1.4 3 0 1.2 V 1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 2.2 V, 3 V ±1 LSB ED Differential linearity error 2.2 V, 3 V ±1 LSB EO Offset error 2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Operational Amplifier (OA) Supply Specifications (MSP430F22x4 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC MIN Supply voltage range Supply current (1) Medium Mode 2.2 V, 3 V Slow Mode PSRR (1) MAX 180 290 110 190 50 80 2.2 Fast Mode ICC TYP Power-supply rejection ratio Noninverting 2.2 V, 3 V UNIT 3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 RO/P(OAx) Max R Load ILoad AV CC OAx 2 CLoad O/P(OAx) Min AV CC −0.2VAV 0.2V V CC OUT Figure 25. OAx Output Resistance Tests Operational Amplifier (OA) Dynamic Specifications (MSP430F22x4 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER SR TEST CONDITIONS Slew rate VCC MIN Fast Mode 1.2 Medium Mode 0.8 Slow Mode 0.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Operational Amplifier OA Feedback Network, Resistor Network (MSP430F22x4 Only) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Rtotal Total resistance of resistor string 76 96 128 kΩ Runit Unit resistor of resistor string (2) 4.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4) (MSP430F22x4 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER G Gain MIN TYP MAX OAFBRx = 0 TEST CONDITIONS 0.998 1 1.002 OAFBRx = 1 1.328 1.334 1.340 OAFBRx = 2 1.985 2.001 2.017 OAFBRx = 3 2.638 2.667 2.696 3.94 4 4.06 OAFBRx = 5 5.22 5.33 5.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V, 3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V, 3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x Interrupt Edge Select P1SEL.x P1IES.x Table 21. Port P1 (P1.0 to P1.3) Pin Functions PIN NAME (P1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access Features Pad Logic P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select To JTAG From JTAG Table 22. Port P1 (P1.4 to P1.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features Pad Logic P1REN.7 P1DIR.7 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.7 DVSS DVCC P1.7/TA2/TDO/TDI Bus Keeper P1SEL.7 EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q P1IFG.7 Set Interrupt Edge Select P1SEL.7 P1IES.7 To JTAG From JTAG From JTAG From JTAG (TDO) Table 23. Port P1 (P1.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P2REN.x P2DIR.x 0 P2OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1 Bus Keeper P2SEL.x EN P2IN.x EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x Interrupt Edge Select P2SEL.x P2IES.x + OA0 − Table 24. Port P2 (P2.0, P2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 1 ADC10AE0.1 P2REN.1 P2DIR.1 0 P2OUT.1 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.1/TAINCLK/SMCLK/ A1/OA0O Bus Keeper P2SEL.1 EN P2IN.1 EN Module X IN D P2IE.1 P2IRQ.1 EN Q Set P2IFG.1 + 1 OA0 P2SEL.1 P2IES.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger SREF2 Pad Logic VSS 0 To ADC 10 VR− 1 To ADC 10 INCHx = 3 ADC10AE0.3 P2REN.3 P2DIR.3 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.3 DVSS DVCC P2.3/TA1/ A3/VREF−/VeREF−/ OA1I1/OA1O Bus Keeper P2SEL.3 EN P2IN.3 EN Module X IN D P2IE.3 P2IRQ.3 P2IFG.3 P2SEL.3 P2IES.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 26. Port P2 (P2.3) Pin Functions PIN NAME (P2.x) x y FUNCTION P2.3 P2.3/TA1/A3/VREF/VeREF-/ OA1I1/OA1O (1) (2) (3) 64 3 3 (2) (I/O) CONTROL BITS/SIGNALS (1) P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 Timer_A3.CCI1B 0 1 0 Timer_A3.TA1 1 1 0 A3/VREF-/VeREF-/OA1I1/OA1O (3) X X 1 X = Don't care Default after reset (PUC/POR) Setting the ADC10AE0.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger Pad Logic To /from ADC10 positive reference To ADC 10 INCHx = 4 ADC10AE0.4 P2REN.4 P2DIR.4 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.4 DVSS P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 Bus Keeper P2SEL.4 EN P2IN.4 EN Module X IN D P2IE.4 P2IRQ.4 EN Q P2IFG.4 P2SEL.4 P2IES.4 Set Interrupt Edge Select + OA1 − Table 27. Port P2 (P2.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO Pad Logic To DCO DCOR P2REN.x P2DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS DVCC P2.5/ROSC Bus Keeper P2SEL.x EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Table 28. Port P2 (P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION P2.5 P2.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 Pad Logic P2SEL.7 P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS DVCC P2.6/XIN Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q P2IFG.6 Set Interrupt Edge Select P2SEL.6 P2IES.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS DVCC P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 P2SEL.7 P2IES.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 5 ADC10AE0.5 P3REN.0 P3DIR.0 USCI Direction Control 0 P3OUT.0 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.0/UCB0STE/UCA0CLK/A5 Bus Keeper P3SEL.0 EN P3IN.0 EN Module X IN D Table 31. Port P3 (P3.0) Pin Functions PIN NAME (P1.x) x y FUNCTION P3.0 (2) (I/O) P3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger Pad Logic DVSS P3REN.x P3DIR.x USCI Direction Control 0 P3OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D Table 32. Port P3 (P3.1 to P3.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P3REN.x P3DIR.x 0 DVSS 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS P3.6/A6/OA0I2 P3.7/A7/OA1I2 Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D + OA0/1 − Table 33. Port P3 (P3.6, P3.7) Pin Functions PIN NAME (P3.x) P3.6/A6/OA0I2 P3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0 P4.1/TB1 P4.2/TB2 Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Table 34. Port P4 (P4.0 to P4.2) Pin Functions PIN NAME (P4.x) x FUNCTION P4.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 † INCHx = 8+y ADC10AE1.y P4REN.x P4DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS DVCC P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O Bus Keeper P4SEL.x EN P4IN.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Table 35. Port P4 (P4.3 to P4.4) Pin Functions PIN NAME (P4.x) x y FUNCTION P4.3 P4.3/TB0/A12/OA0O 3 4 4 5 74 ADC10AE1.y 0 0 0 1 0 Timer_B3.TB0 1 1 0 A12/OA0O (3) X X 1 I: 0; O: 1 0 0 Timer_B3.CCI1B (I/O) 0 1 0 Timer_B3.TB1 1 1 0 X X 1 A13/OA1O (1) (2) (3) P4SEL.x I: 0; O: 1 (2) (I/O) P4DIR.x Timer_B3.CCI0B P4.4 P4.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 INCHx = 14 ADC10AE1.6 P4REN.5 P4DIR.5 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.5 DVSS DVCC P4.5/TB3/A14/OA0I3 Bus Keeper P4SEL.5 EN P4IN.5 EN Module X IN D + OA0 − Table 36. Port P4 (P4.5) Pin Functions PIN NAME (P4.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 15 ADC10AE1.7 P4REN.6 P4DIR.6 0 P4OUT.6 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.6/TBOUTH/ A15/OA1I3 Bus Keeper P4SEL.6 EN P4IN.6 EN Module X IN D + OA1 − Table 37. Port P4 (P4.6) Pin Functions PIN NAME (P4.x) x y FUNCTION P4.6 P4.
MSP430F22x2 MSP430F22x4 www.ti.com SLAS504G – JULY 2006 – REVISED AUGUST 2012 Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger Pad Logic DVSS P4REN.x P4DIR.x 0 P4OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.7/TBCLK Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Table 38. Port P4 (Pr.7) Pin Functions PIN NAME (P4.x) x FUNCTION P4.7 P4.7/TBCLK (1) 7 (1) (I/O) CONTROL BITS/SIGNALS P4DIR.x P4SEL.x I: 0; O: 1 0 Timer_B3.
MSP430F22x2 MSP430F22x4 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
MSP430F22x2 MSP430F22x4 www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2232IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2232IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 MSP430F2232IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2252TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 MSP430F2252TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 MSP430F2254IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2254IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.
PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2232IDAR MSP430F2232IRHAR TSSOP DA 38 2000 367.0 367.0 45.0 VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2232IRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2232IYFFR DSBGA YFF 49 2500 367.0 367.0 35.0 MSP430F2232IYFFT DSBGA YFF 49 250 210.0 185.0 35.0 MSP430F2232TRHAR VQFN RHA 40 2500 367.
PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2254IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2254IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2254IRHAT VQFN RHA 40 250 210.0 185.0 35.0 MSP430F2254IYFFR DSBGA YFF 49 2500 367.0 367.0 35.0 MSP430F2254IYFFT DSBGA YFF 49 250 210.0 185.0 35.0 MSP430F2254TRHAR VQFN RHA 40 2500 367.0 367.0 38.
D: Max = 3.518 mm, Min =3.458 mm E: Max = 3.36 mm, Min = 3.
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