MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • • • • • • • Low Supply Voltage Range 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 365 µA at 1 MHz, 2.2 V – Standby Mode (VLO): 0.5 µA – Off Mode (RAM Retention): 0.1 µA Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 P7.7 AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P8.7/XT2IN P8.6/XT2OUT Device Pinout, MSP430F241x, 80-Pin PN Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DVCC1 P6.3/A3 1 2 60 59 P7.6 P7.5 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN 3 4 5 6 58 57 56 55 P7.4 P7.3 P7.2 P7.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F241x, 64-Pin PM Package 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC1 P6.3/A3 P6.4/A4 P6.5/A5 VREF-/VeREF- 1 2 3 4 5 6 7 8 9 10 11 P1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 12 13 14 15 16 P6.6/A6 P6.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 P7.7 AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P8.7/XT2IN P8.6/XT2OUT Device Pinout, MSP430F261x, 80-Pin PN Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DVCC1 P6.3/A3 P6.4/A4 1 2 3 60 59 58 P7.6 P7.5 P7.4 P6.5/A5/DAC1 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN 4 5 6 57 56 55 P7.3 P7.2 P7.1 VREF+ XIN XOUT 7 8 9 54 53 52 P7.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com P5.5/SMCLK P5.7/TBOUTH/SVSOUT P5.6/ACLK XT2IN XT2OUT TDI/TCLK TDO/TDI TCK TMS RST/NMI P6.1/A1 P6.0/A0 AV SS P6.2/A2 DVSS1 AV CC Device Pinout, MSP430F261x, 64-Pin PM Package 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DV CC1 1 48 P6.3/A3 2 47 P5.3/UCB1CLK/UCA1STE P6.4/A4 3 46 P5.2/UCB1SOMI/UCB1SCL P6.5/A5/DAC1 P6.6/A6/DAC0 4 5 45 44 P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P6.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Device Pinout, 113-Pin ZQW Package NOTE For terminal assignments, see Table 2.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Functional Block Diagram, MSP430F241x, 80-Pin PN Package XIN/ XT2IN XOUT/ XT2OUT 2 2 DVCC1/2 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU 1MB incl. 16 Registers DVSS1/2 Flash RAM 120KB 116KB 92KB 92KB 4KB 8KB 8KB 4KB AVCC AVSS P3.x/P4.x P5.x/P6.x 2x8 4x8 P1.x/P2.x Ports P1/P2 ADC12 12-Bit Ports P3/P4 P5/P6 2x8 I/O Interrupt capability 8 Channels 4x8 I/O P7.x/P8.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Functional Block Diagram, MSP430F261x, 80-Pin PN Package XIN/ XT2IN XOUT/ XT2OUT 2 2 DVCC1/2 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU 1MB incl. 16 Registers Flash 120kB 116kB 92kB 92kB 56kB DVSS1/2 AVCC RAM 4kB 8kB 8kB 4kB 4kB ADC12 12-Bit 8 Channels AVSS DAC12 12-Bit 2 Channels Voltage Out P3.x/P4.x P5.x/P6.x 2x8 4x8 P1.x/P2.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION 64 PIN 80 PIN 113 PIN AVCC 64 80 A2 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12. AVSS 62 78 B2, B3 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12. DVCC1 1 1 A1 Digital supply voltage, positive terminal. Supplies all digital parts.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Table 2. Terminal Functions (continued) TERMINAL NO. NAME 64 PIN 80 PIN I/O DESCRIPTION 113 PIN P2.6/ADC12CLK/ DMAE0 (1)/CA6 26 26 J4 I/O General-purpose digital I/O pin Conversion clock - 12-bit ADC DMA channel 0 external trigger Comparator_A input P2.7/TA0/CA7 27 27 L5 I/O General-purpose digital I/O pin Timer_A, compare: Out0 output Comparator_A input P3.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME I/O DESCRIPTION 64 PIN 80 PIN 113 PIN P5.0/UCB1STE/ UCA1CLK 44 44 K12 I/O General-purpose digital I/O pin USCI_B1 slave transmit enable/USCI_A1 clock input/output P5.1/UCB1SIMO/ UCB1SDA 45 45 J11 I/O General-purpose digital I/O pin USCI_B1 slave-in master-out in SPI mode, SDA I2C data in I2C mode P5.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Table 2. Terminal Functions (continued) TERMINAL NO. NAME 64 PIN I/O DESCRIPTION 80 PIN 113 PIN P7.5 59 B12 I/O General-purpose digital I/O pin P7.6 60 A12 I/O General-purpose digital I/O pin P7.7 61 A11 I/O General-purpose digital I/O pin P8.0 62 B10 I/O General-purpose digital I/O pin P8.1 63 A10 I/O General-purpose digital I/O pin P8.2 64 D9 I/O General-purpose digital I/O pin P8.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU enters LPM4 immediately after power-up. Table 5.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Memory Organization Table 8.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Brownout, Supply Voltage Supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is not automatically reset).
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 12.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Timer_B7 Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 13.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Comparator_A+ The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Peripheral File Map Table 14.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Table 14.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 14.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Table 14.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 14.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Table 14.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature (3) Tstg (1) ±2 mA Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
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MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Typical Characteristics - Active Mode Supply Current (Into VCC) ACTIVE MODE CURRENT vs SUPPLY VOLTAGE (TA = 25°C) ACTIVE MODE CURRENT vs DCO FREQUENCY 7.0 10.0 9.0 6.0 TA = 25 °C 8.0 Active Mode Current − mA Active Mode Current − mA TA = 85 °C f DCO = 16 MHz f DCO = 12 MHz 7.0 6.0 5.0 f DCO = 8 MHz 4.0 3.0 4.0 TA = 85 °C 3.0 TA = 25 °C 2.0 2.0 f DCO = 1 MHz 1.0 1.0 0.0 1.5 2.0 2.5 3.0 3.
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MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Typical Characteristics - LPM4 Current ILPM4 − Low−power mode current − µA LPM4 CURRENT vs TEMPERATURE 16.0 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 Vcc = 3.6 V 7.0 Vcc = 3.0 V 6.0 5.0 Vcc = 2.2 V 4.0 3.0 2.0 1.0 Vcc = 1.8 V 0.0 −40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 TA − Temperature − °C Figure 4.
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MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Outputs (Ports P1 Through P8) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA VOH (1) (2) MAX VCC - 0.25 VCC VCC - 0.6 VCC I(OHmax) = -1.5 mA (1) 3V VCC - 0.25 VCC I(OHmax) = -6 mA (2) 3V VCC - 0.6 VCC 2.2 V VSS VSS + 0.25 2.2 V VSS VSS + 0.6 I(OLmax) = 1.5 mA (1) 3V VSS VSS + 0.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics - Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P4.5 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.
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MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics - POR and BOR VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR jor BOR Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Software sets VLD >0: SVS is active AVCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) Brownout Region Brownout Region Brownout 1 0 SVS out t d(BOR) t d(BOR) SVS Circuit is Active From VLD > to V CC < V( B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 12. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min) − V 1.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 % 25°C 3V 0.990 1 1.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics - Calibrated DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE CALIBRATED 8-MHz FREQUENCY vs SUPPLY VOLTAGE 1.02 8.20 TA = 105 °C 8.15 8.10 Frequency − MHz Frequency − MHz 1.01 TA = 105 °C 1.00 TA = 85 °C TA = 25 °C 0.99 8.00 TA = 85 °C TA = 25 °C 7.95 TA = −40 °C 7.90 7.85 TA = −40 °C 0.98 1.5 8.05 2.0 2.5 3.0 3.5 7.80 1.5 4.0 2.0 VCC − Supply Voltage − V 2.5 4.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Wake-Up From Lower-Power Modes (LPM3, LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 2.2 V, 3 V (1) (2) 1.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25°C DT Temperature drift DV Drift with VCC (1) VCC TYP UNIT 2.2 V 1.8 3V 1.95 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V ±0.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Typical Characteristics - DCO With External Resistor ROSC (continued) DCO FREQUENCY vs TEMPERATURE VCC = 3 V DCO FREQUENCY vs SUPPLY VOLTAGE TA = 25°C 2.50 2.50 2.25 ROSC = 100k DCO Frequency − MHz 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 ROSC = 1M 0.25 −25.0 0.0 25.0 50.0 TA − Temperature − °C Figure 21. 48 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 0.50 0.00 −50.
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MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1, XCAPx = 0 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2, XCAPx = 0 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 LFXT1Sx = 2 100.00 LFXT1Sx =0 10.00 0.10 1.00 LFXT1Sx = 1 10.00 100.00 Crystal Frequency − MHz Figure 23.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Crystal Oscillator XT2 (1) PARAMETER VCC MIN XT2Sx = 0 1.8 V to 3.6 V XT2 oscillator crystal frequency, mode 1 XT2Sx = 1 XT2 oscillator crystal frequency, mode 2 XT2Sx = 2 fXT2 XT2 oscillator crystal frequency, mode 0 fXT2 fXT2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 2.2 V 2 10 2.2 V to 3.6 V 2 12 3 V to 3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics - XT2 Oscillator OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 XT2Sx = 2 100.00 XT2Sx = 1 XT2Sx = 0 10.00 0.10 1.00 10.00 100.00 Crystal Frequency − MHz Figure 25.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% ± 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 2.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) (1) tτ UART receive deglitch time (2) (1) (2) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V, 3 V MAX UNIT fSYSTEM MHz 1 MHz 2.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 27. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tVALID,MO SIMO Figure 28.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 29. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 30.
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MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P2 3/CA0/TA1 and P2.4/CA1/TA2 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT µA µA VIC Common-mode input voltage range CAON = 1 2.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 0V www.ti.com VCC 0 1 CAF CAON To Internal Modules Low Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 32. Comparator_A+ Module Block Diagram VCAOUT Overdrive V− 400 mV t (response) V+ Figure 33. Overdrive Definition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 34.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Typical Characteristics, Comparator_A+ V(RefVT) vs TEMPERATURE (VCC = 3 V) V(RefVT) vs TEMPERATURE (VCC = 2.2 V) 650 650 VCC = 2.2 V 600 V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 TA − Free-Air Temperature − °C −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 35. Figure 36.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com 12-Bit ADC Power Supply and Input Range Conditions (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (2) All P6.0/A0 to P6.7/A7 terminals, Analog inputs selected in ADC12MCTLx register, P6Sel.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 12-Bit ADC Built-In Reference over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Positive built-in reference voltage output VREF+ AVCC(min) AVCC minimum voltage, positive built-in reference active TA REF2_5V = 1 for 2.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min -40°C to 85°C REF2_5V = 0 for 1.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com From Power Supply DVCC + − DVSS 10 µ F 100 nF AVCC + − AVSS 10 µ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] Apply External Reference 100 nF VREF+ or V eREF+ + − 10 µ F 100 nF VREF−/VeREF− + − 10 µ F MSP430F261x MSP430F241x 100 nF Figure 39.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 12-Bit ADC Timing Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time tADC12ON Turn-on settling time of the ADC (1) tSample Sampling time (1) (2) (3) (1) VCC MIN For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 5 6.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.
MSP430F261x MSP430F241x www.ti.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Typical Characteristics - 12-Bit DAC, Linearity Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL INL ERROR vs DIGITAL INPUT DATA 4 VCC = 2.2 V, VREF = 1.
MSP430F261x MSP430F241x www.ti.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com 12-Bit DAC Dynamic Specifications VREF = VCC, DAC12IR = 1 (see Figure 45 and Figure 46), over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tON DAC12 on-time TEST CONDITIONS DAC12_xDAT = 800h, ErrorV(O) < ±0.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 46. Slew Rate Testing ILoad Ve REF+ RLoad = 3 kΩ AV CC DAC12_x 2 DACx AC CLoad = 100pF DC Figure 47.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 APPLICATION INFORMATION Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x EN P1IRQ.x Q Set P1IFG.x P1SEL.x Interrupt Edge Select P1IES.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 15. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) x P1.0/TACLK/CAOUT 0 FUNCTION P1.0 (I/O) 1 2 0 0 1 CAOUT 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1 I: 0; O: 1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 P1.3 (I/O) P1.3/TA2 3 P1.4/SMCLK 4 P1.5/TA0 5 P1.6/TA1 P1.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS Bus Keeper EN P2SEL.x P2IN.x P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.6/ADC12CLK/DMAE0/CA6 P2.7/TA0/CA7 EN D Module X IN P2IE.x P2IRQ.x EN Q Set P2IFG.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Table 16. Port P2 (P2.0 to P2.4, P2.6, and P2.7) Pin Functions PIN NAME (P2.x) P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.6/ADC12CLK/ DMAE0 (2)/CA6 P2.7/TA0/CA7 (1) (2) 76 x 0 1 2 3 4 6 7 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.x P2DIR.x P2SEL.x P2.0 (I/O) 0 I: 0; O: 1 0 ACLK 0 1 1 CA2 1 X X P2.1 (I/O) 0 I: 0; O: 1 0 Timer_A3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P2 (P2.5), Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.5 To DCO in DCO DCOR P2REN.5 P2DIR.5 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.5 DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.x P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q Set P2SEL.5 P2IES.5 Interrupt Edge Select Table 17. Port P2 (P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION P2.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x Module direction P3OUT.x Module X OUT 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 0 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P3SEL.x P3IN.x EN Module X IN D Table 18. Port P3 (P3.0 to P3.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P4SEL.x P4IN.x EN Module X IN D Table 19. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.0/TB0 0 1 2 0 0 1 Timer_B7.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 Module Direction 1 P5OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5.0/UCB1STE/UCA1CLK P5.1/UCB1SIMO/UCB1SDA P5.2/UCB1SOMI/UCB1SCL P5.3/UCB1CLK/UCA1STE P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT P5SEL.x P5IN.x EN Module X IN D Table 20. Port P5 (P5.0 to P5.7) Pin Functions PIN NAME (P5.x) P5.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger Pad Logic ADC12 Ax P6REN.x P6DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 Bus Keeper EN P6SEL.x P6IN.x EN Module X IN D Table 21. Port P6 (P6.0 to P6.4) Pin Functions PIN NAME (P6.x) x P6.0/A0 0 P6.1/A1 1 P6.2/A2 2 P6.3/A3 3 P6.4/A4 (1) (2) 4 FUNCTION P6.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger Pad Logic DAC12_0OUT DAC12AMP > 0 ADC12 Ax ADC12 Ax P6REN.x P6DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.5/A5/DAC1 P6.6/A6/DAC0 Bus Keeper EN P6SEL.x P6IN.x EN Module X IN D Table 22. Port P6 (P6.5 and P6.6) Pin Functions PIN NAME (P6.x) x FUNCTION P6.5 (I/O) P6.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P6 (P6.7), Input/Output With Schmitt Trigger Pad Logic to SVS Mux VLD = 15 DAC12_0OUT DAC12AMP > 0 ADC12 A7 from ADC12 P6REN.7 P6DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.7 DVSS P6.7/A7/DAC1/SVSIN Bus Keeper EN P6SEL.7 P6IN.7 EN Module X IN D Table 23. Port P6 (P6.7) Pin Functions PIN NAME (P6.x) x FUNCTION P6DIR.x P6SEL.x INCH.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger (5) Pad Logic P7REN.x P7DIR.x 0 0 1 P7OUT.x 0 VSS 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P7SEL.x P7IN.x EN D Module X IN Table 24. Port P7 (P7.0 to P7.7) Pin Functions (1) PIN NAME (P7.x) P7.0 x 0 P7.1 1 P7.2 2 P7.3 3 P7.4 4 P7.5 5 P7.6 6 P7.7 (5) (1) (2) 84 7 FUNCTION P7.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger (3) Pad Logic P8REN.x P8DIR.x 0 0 1 P8OUT.x 0 VSS 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8SEL.x P8IN.x EN Module X IN D Table 25. Port P8 (P8.0 to P8.5) Pin Functions (1) PIN NAME (P8.x) P8.0 P8.1 x 0 1 P8.2 2 P8.3 3 P8.4 4 P8.5 5 (3) (1) (2) FUNCTION P8.0 (I/O) Input P8.1 (I/O) Input P8.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com Port P8 (P8.6), Input/Output With Schmitt Trigger (3) BCSCTL3.XT2Sx = 11 0 XT2CLK 1 From P8.7/XIN P8.7/XT2IN XT2 off Pad Logic P8SEL.7 P8REN.6 P8DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P8OUT.6 DVSS P8.6/XT2OUT Bus Keeper EN P8SEL.6 P8IN.6 EN Module X IN D Table 26. Port P8 (P8.6) Pin Functions (1) PIN NAME (P8.x) x FUNCTION P8.6 (I/O) P8.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 Port P8 (P8.7), Input/Output With Schmitt Trigger (2) BCSCTL3.XT2Sx = 11 P8.6/XT2OUT XT2 off 0 XT2CLK 1 Pad Logic P8SEL.6 P8REN.7 0 P8DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P8OUT.7 DVSS P8.7/XT2IN P8SEL.7 Bus Keeper EN P8IN.7 EN D Module X IN Table 27. Port P8 (P8.7) Pin Functions (1) PIN NAME (P8.x) x FUNCTION P8DIR.x P8SEL.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.
MSP430F261x MSP430F241x www.ti.com SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
MSP430F261x MSP430F241x SLAS541K – JUNE 2007 – REVISED NOVEMBER 2012 www.ti.com REVISION HISTORY LITERATURE NUMBER DESCRIPTION SLAS541 Product Preview release SLAS541A Production Data release Corrected the format and the content shown on the first page. Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list. Corrected the port schematics. Corrected "calibration data" section (page 20). Typos and formatting corrected.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 8-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F2416TPMR MSP430F2416TPNR MSP430F2416TZQWR Package Package Pins Type Drawing LQFP LQFP BGA MI CROSTA R JUNI OR PM SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CROSTA R JUNI OR MSP430F2616TPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F2616TPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2416TPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F2416TPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430F2416TZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F2417TPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F2417TPNR LQFP PN 80 1000 367.0 367.0 45.
PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2617TZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F2618TPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F2618TPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430F2618TZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430F2619TPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F2619TPNR LQFP PN 80 1000 367.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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