MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D Active Mode: 250 μA at 1 MHz, 2.2 V Standby Mode: 1.1 μA Off Mode (RAM Retention): 0.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 pin designation, MSP430F42x0 DL PACKAGE (TOP VIEW) TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC DVSS XIN XOUT AVSS AVCC VREF P6.0/A0+ P6.1/A0− P6.2/A1+ P6.3/A1− P6.4 P6.5 P6.6 P6.7 P1.7/A2+ P1.6/A2− P1.5/TACLK/ACLK/A3+ P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 pin designation, MSP430F42x0 (continued) 47 46 45 44 43 42 41 40 39 38 P2.1/S12 P2.0/S13 COM0 P5.2/COM1 P5.3/COM2 P5.4/COM3 TDO/TDI TDI/TCLK TMS TCK RST/NMI DVCC RGZ PACKAGE (TOP VIEW) P2.2/S11 2 35 P2.3/S10 XOUT 3 34 P2.4/S9 AVSS 4 33 P2.5/S8 AVCC 5 32 P2.6/S7 VREF 6 31 P2.7/S6 P6.0/A0+ 7 30 S5 P6.1/A0− 8 29 P5.7/S4 P6.2/A1+ 9 28 P5.6/S3 P6.3/A1− 10 27 P5.5/S2 P6.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 functional block diagram XIN XOUT DVCC DVSS AVCC AVSS P1 P2 P4 P3 P6 P5 8 8 8 8 8 8 ACLK Oscillator FLL+ SMCLK MCLK 8 MHz CPU incl.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 Terminal Functions TERMINAL NAME DESCRIPTION DL NO. RGZ NO. I/O TDO/TDI 1 43 I/O TDI/TCLK 2 44 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 3 45 I Test mode select. TMS is used as an input port for device programming and test. TCK 4 46 I Test clock. TCK is the clock input port for device programming and test.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 MSP430F42x0 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION DL NO. RGZ NO. I/O P2.5/S8 39 33 I/O General-purpose digital I/O / LCD segment output 8 P2.4/S9 40 34 I/O General-purpose digital I/O / LCD segment output 9 P2.3/S10 41 35 I/O General-purpose digital I/O / LCD segment output 10 P2.2/S11 42 36 I/O General-purpose digital I/O / LCD segment output 11 P2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh−0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 special function registers The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as byte mode registers. SFRs should be accessed with byte instructions. interrupt enable registers 1 and 2 7 Address 6 0h 5 4 ACCVIE NMIIE rw–0 3 2 1 OFIE rw–0 rw–0 Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 04h Address 05h Legend: rw: rw–0,1: rw–(0,1): Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature Number SLAU056.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer_A3 _ Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P6 Port P5 Port P2 Port P1 Special p functions 16 Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P2 selection P2SEL 02Eh Port P2 interrupt ena
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . .
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) TA = −40°C 40°C to 85°C I(LPM0) Low power mode, (LPM0) Low-power (see Note 1 and Note 4) TA = −40°C 40°C to 85°C I(LPM2) Low-power mode, (LPM2
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SCHMITT-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER TEST CONDITIONS VIT+ Positive going input threshold voltage Positive-going VIT− Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ − VIT−) MIN TYP MAX VCC = 2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P5, and P6 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN TYP MAX IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC IOH(max) = −1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P5, and P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 VCC = 2.2 V P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP f = 1 MHz td(LPM3) f = 2 MHz Delay time MAX UNIT 6 6 VCC = 2.2 V/3 V f = 3 MHz μs 6 RAM PARAMETER TEST CONDITIONS VRAMh MIN CPU halted (see Note 1) TYP MAX 1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP td(BOR) dVCC/dt ≤ 3 V/s (see Figure 6) VCC(start) V(B_IT−) Vhys(B_IT−) t(reset) UNIT 2000 μs 0.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics (continued) VCC 3V 2 VCC(drop)− V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw − Pulse Width − μs 1 ns tpw − Pulse Width − μs Figure 7.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER VCC f(DCOCLK) N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0, fCrystal = 32.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Sn - Stepsize Ratio between DCO Taps electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 1.17 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 10.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER CXIN CXOUT Integrated input capacitance (see Note 4) Integrated output capacitance (see Note 4) TEST CONDITIONS MIN 0 OSCCAPx = 1h, VCC = 2.2 V / 3 V 10 OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 OSCCAPx = 3h, VCC = 2.2 V / 3 V 18 OSCCAPx = 0h, VCC = 2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, power supply and recommended operating conditions PARAMETER AVCC ISD16 fSD16 Analog supply voltage Analog supply current including internal reference Analog front-end input clock frequency TEST CONDITIONS VCC MIN AVCC = DVCC AVSS = DVSS = 0V TYP MAX 2.5 3.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01) PARAMETER TEST CONDITIONS VCC SD16GAINx = 1,Signal Amplitude = 500mV SD16OSRx = 256 MIN TYP 3V 84 3V 84 SD16GAINx = 1,Signal Amplitude = 500mV SD16OSRx = 1024 3V 84 Nominal gain SD16GAINx = 1; SD16OSRx = 1024 3V dG/dT Gain temperatu
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, temperature sensor PARAMETER TEST CONDITIONS VCC MIN TCSensor Sensor temperature coefficient 1.18 VOffset,sensor Sensor offset voltage −100 VSensor Sensor output S t t voltage lt (see Note 2) TYP 1.32 MAX UNIT 1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 SD16_A, external reference input PARAMETER TEST CONDITIONS VCC VREF(I) Input voltage range SD16REFON = 0 3V IREF(I) Input current SD16REFON = 0 3V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 1.0 TYP 1.25 MAX UNIT 1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, supply specifications PARAMETER AVCC IDD PSRR Analog supply voltage Supply Current (see Notes 1 and 2) Power supply rejection ratio (see Notes 3 and 4) TEST CONDITIONS VCC AVCC = DVCC, AVSS = DVSS =0 V MIN TYP 2.20 MAX UNIT 3.60 V DAC12AMPx=2, DAC12IR=0, DAC12_xDAT=0800h 2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 12) PARAMETER TEST CONDITIONS VCC MIN TYP MAX Resolution (12-bit Monotonic) INL Integral nonlinearity (see Note 1) VREF,DAC12 = 1.2V DAC12AMPx = 7, DAC12IR = 1 2.7V ±2.0 ±8.0 LSB DNL Differential nonlinearity (see Note 1) VREF,DAC12 = 1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA INL − Integral Nonlinearity Error − LSB 4 VCC = 2.2 V, VREF = 1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER VO TEST CONDITIONS Output voltage range (see Note 1, Figure 15) CL(DAC12) Max DAC12 load capacitance IL(DAC12) Max DAC12 load current RO/P(DAC12) Output Resistance (see Figure 15) VCC MIN TYP MAX No Load, VREF,DAC12 = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS VREF Reference input voltage range Ri(VREF) Reference input resistance NOTES: 1. 2. 3. 4. TYP MAX DAC12IR=0, (see Notes 1 and 2) 2.2V/3V VCC MIN AVCC/3 AVCC+0.2 DAC12IR=1, (see Notes 3 and 4) 2.2V/3V AVCC AVCC+0.2 DAC12IR=0 2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 17. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted) PARAMETER BW−3dB TEST CONDITIONS 3 dB bandwidth, b d idth 3-dB VDC=1.5V, VAC=0.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Flash Memory TEST CONDITIONS PARAMETER VCC(PGM/ VCC MIN NOM MAX UNIT Program and Erase supply voltage 2.5 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.5V/3.6V 3 5 mA IERASE Supply current from DVCC during erase 2.5V/3.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 input/output schematics Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger Pad Logic DV SS DV SS DV SS P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 Module X OUT 1 Bus Keeper P1SEL.x P1.0/TA0 P1.1/TA0/MCLK EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select Note: x = 0,1 Port P1 (P1.0, P1.1) pin functions PIN NAME (P1.X) (P1 X) P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions INCH=4 Pad Logic 0 AV SS A4− 1 SD16AE.x P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 Module X OUT 1 P1.2/TA1/A4− Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x Set Interrupt Edge Select P1SEL.x P1IES.x Note: x = 2 Port P1 (P1.2) pin functions (P1 X) PIN NAME (P1.X) P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions INCH=y Pad Logic Ay+ SD16AE.x P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 Module X OUT 1 Bus Keeper P1SEL.x P1.3/TA2/A4+ P1.5/TACLK/ACLK/A3+ P1.7/A2+ EN P1IN.x EN Module X IN P1IRQ.x D P1IE.x EN Q P1IFG.x P1SEL.x P1IES.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 (P1.3, P1.5, P1.7) pin functions (P1 X) PIN NAME (P1.X) P1.3/TA2/A4+ CONTROL BITS / SIGNALS X 3 FUNCTION P1.3† Input/Output Timer_A3.CCI2A P1.5/TACLK/ACLK/A3+ 5 7 P1SEL.x SD16AE.x 0/1 0 0 0 1 0 Timer_A3.TA2 1 1 0 A4+ (see Note 3) X X 1 P1.5† Input/Output 0/1 0 0 Timer_A3.TACLK/INCLK 0 1 0 ACLK 1 1 0 A3+ (see Note 3) P1.7/A2+ P1DIR.x P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions INCH=3 Pad Logic 0 AV SS A3− 1 SD16AE.x DAC12OPS ’1’ if DAC12AMPx>0 P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 DVSS 1 P1.4/A3−/DAC0 Bus Keeper P1SEL.x EN P1IN.x DAC12OPS P1IE.x P1IRQ.x DAC0 EN Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Note: x = 4 Port P1 (P1.4) pin functions (P1 X) PIN NAME (P1.X) P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions INCH=2 Pad Logic 0 AV SS A2− 1 SD16AE.x P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x DV SS 0 1 P1.6/A2− Bus Keeper P1SEL.x EN P1IN.x P1IE.x EN P1IRQ.x Q P1IFG.x Set Interrupt Edge Select P1SEL.x P1IES.x Note: x = 6 Port P1 (P1.6) pin functions (P1 X) PIN NAME (P1.X) P1.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P2 pin schematic: P2.0 to P2.7, input/output with Schmitt−trigger, LCD and analog functions Pad Logic LCDS4/8/12 Segment Sy DV SS P2DIR.x 0 Direction 0: Input 1: Output 1 P2OUT.x DV SS 0 1 Bus Keeper P2SEL.x EN P2IN.x P2IE.x P2IRQ.x P2.0/S13 P2.1/S12 P2.2/S11 P2.3/S10 P2.4/S9 P2.5/S8 P2.6/S7 P2.7/S6 EN Q P2IFG.x P2SEL.x P2IES.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P2 (P2.0 to P2.7) pin functions (P2 X) PIN NAME (P2.X) P2.0/S13 CONTROL BITS / SIGNALS X 0 FUNCTION P2.0† Input/Output N/A P2.1/S12 1 2 3 4 P2.6/S7 5 6 7 1 0 1 P2.1† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 P2.2† Input/Output X X 1 0/1 0 0 0 1 0 DVSS 1 1 0 S11 X X 1 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 P2.3† Input/Output P2.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCD functions Pad Logic LCDS0/4 Segment Sy DV SS P5DIR.x 0 1 P5OUT.x DV SS P5SEL.x Direction 0: Input 1: Output 0 1 Bus Keeper EN P5.0/S1 P5.1/S0 P5.5/S2 P5.6/S3 P5.7/S4 P5IN.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 (P5.0, P5.1, P5.5, P5.6) pin functions (P5 X) PIN NAME (P5.X) P5.0/S1 CONTROL BITS / SIGNALS X 0 FUNCTION P5.0† Input/Output N/A P5.1/S0 1 5 6 LCDS0 0 0 0 1 0 1 1 0 S1 X X 1 P5.1† Input/Output 0/1 0 0 N/A 0 1 0 DVSS 1 1 0 P5.5† Input/Output N/A P5.6/S3 P5SEL.x 0/1 DVSS S0 P5.5/S2 P5DIR.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions Pad Logic LCD Signal DV SS P5DIR.x 0 Direction 0: Input 1: Output 1 P5OUT.x DV SS 0 1 Bus Keeper P5SEL.x P5.2/COM1 P5.3/COM2 P5.4/COM3 EN P5IN.x Note: x = 2 to 4 Port P5 (P5.2 to P5.4) pin functions (P5 X) PIN NAME (P5.X) CONTROL BITS / SIGNALS X P5.2/COM1 2 P5.3/COM2 3 FUNCTION P5.2† Input/Output COM1 P5.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions INCH=0/1 # Pad Logic Ay+ # P6DIR.x 0 Direction 0: Input 1: Output 1 P6OUT.x DV SS 0 1 Bus Keeper P6SEL.x P6.0/A0+ P6.2/A1+ EN P6IN.x Note: x = 0,2 y = 0,1 #Signal from or to SD16 Port P6 (P6.0, P6.2) pin functions (P6 X) PIN NAME (P6.X) P6.0/A0+ CONTROL BITS / SIGNALS X 0 FUNCTION P6.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions INCH=0/1 # Pad Logic Ay−# P6DIR.x 0 Direction 0: Input 1: Output 1 P6OUT.x DV SS 0 1 Bus Keeper P6SEL.x P6.1/A0− P6.3/A1− EN P6IN.x Note: x = 1,3 y = 0,1 #Signal from or to SD16 Port P6 (P6.1, P6.3) pin functions (P6 X) PIN NAME (P6.X) P6.1/A0− CONTROL BITS / SIGNALS X 1 FUNCTION P6.1† Input/Output A0− (see Note 3) P6.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions P6DIR.x Pad Logic 0 Direction 0: Input 1: Output 1 P6OUT.x DV SS 0 1 Bus Keeper P6SEL.x P6.4 P6.5 P6.6 P6.7 EN P6IN.x Note: x = 4 to 7 Port P6 (P6.4 to P6.7) pin functions (P6 X) PIN NAME (P6.X) P6.4 P6.5 CONTROL BITS / SIGNALS X 4 5 FUNCTION P6.4† Input/Output 0/1 0 0 1 DVSS 1 1 0/1 0 0 1 P6.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled by JTAG DVCC TDI Burn and Test Fuse TDI/TCLK Test and Emulation DVCC TMS Module TMS DVCC TCK TCK RST/NMI Tau ~ 50 ns Brownout TCK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 G D U S G D U S 53
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
MSP430F42x0 MIXED SIGNAL MICROCONTROLLER SLAS455D − MARCH 2005 − REVISED APRIL 2007 Data Sheet Revision History Literature Number Summary SLAS455D Updated functional block diagram (page 4) Clarified test conditions in recommended operating conditions table (page 17) Clarified test conditions in electrical characteristics table (page 18) Clarified test conditions in DCO table (page 25) Changed PSRR to AC PSRR in SD16_A, performance table (page 29) Changed PSRR to DC PSR in SD16_A, built-in voltage refere
Manual Update Sheet SLAZ557 – December 2013 Corrections to MSP430F42x0 Data Sheet (SLAS455D) Document Being Updated: MSP430F42x0 Mixed Signal Microcontroller Literature Number Being Updated: SLAS455D Page Change or Add 46 The table includes LCDS12 in the "CONTROL BITS / SIGNALS" column. This is correct for P2.0/S13 and P2.1/S12. For P2.2/S11, P2.3/S10, P2.4/S9, and P2.5/S8, the correct control bit is LCDS8. For P2.6/S7 and P2.7/S6, the correct control bit is LCDS4.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F4250IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 MSP430F4260IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 MSP430F4270IDLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F4250IDLR SSOP DL 48 1000 367.0 367.0 55.0 MSP430F4260IDLR SSOP DL 48 1000 367.0 367.0 55.0 MSP430F4270IDLR SSOP DL 48 1000 367.0 367.0 55.
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