MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D − Active Mode: 280 µA at 1 MHz, 2.2 V − Standby Mode: 1.1 µA − Off Mode (RAM Retention): 0.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 description (continued) The MSP430x43x(1) and the MSP430x44x(1) series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 and MSP430F44x1 devices), one or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD) with up to 160 segments
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT AVCC DVSS1 AVSS PN PACKAGE (TOP VIEW) P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVCC DVSS1 AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT AVCC DVSS1 AVSS PN PACKAGE (TOP VIEW) P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVCC DVSS1 AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 pin designation, MSP430x4481IPZ, MSP430x4491IPZ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVCC DVSS1 AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVCC DVSS1 AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x1 functional block diagram XIN XT2IN XT2OUT DVCC1/2 DVSS1/2 XOUT AVCC AVSS P1 P2 P4 P3 8 8 Port 1 Port 2 8 I/O Interrupt Capability 8 I/O Interrupt Capability P5 8 8 P6 8 8 ACLK Oscillator FLL+ Flash SMCLK MCLK 8 MHz CPU incl.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x1 functional block diagram XIN XT2IN XT2OUT DVCC1/2 DVSS1/2 XOUT AVCC AVSS P1 P2 P4 P3 8 8 Port 1 Port 2 8 I/O Interrupt Capability 8 I/O Interrupt Capability P5 8 8 P6 8 8 ACLK Oscillator FLL+ Flash SMCLK 60KB 48KB MCLK 8 MHz CPU incl.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x1 Terminal Functions TERMINAL PN NAME NO. PZ I/O NAME NO. DESCRIPTION I/O DVCC1 1 DVCC1 1 P6.3 2 I/O P6.3 2 I/O Digital supply voltage, positive terminal. General-purpose digital I/O P6.4 3 I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O P6.6 5 I/O General-purpose digital I/O P6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x1 Terminal Functions (Continued) TERMINAL PN PZ I/O NAME NO. DESCRIPTION I/O NAME NO. P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode / LCD segment output 28 P3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x1 Terminal Functions (Continued) TERMINAL PN NAME NO. PZ I/O NAME NO. DESCRIPTION I/O P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB1 57 I/O P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x Terminal Functions TERMINAL PN NAME NO. PZ I/O NAME NO. DESCRIPTION I/O DVCC1 1 DVCC1 1 P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC P6.5/A5 4 I/O P6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x Terminal Functions (Continued) TERMINAL PN PZ I/O NAME NO. DESCRIPTION I/O NAME NO. P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode / LCD segment output 28 P3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x43x Terminal Functions (Continued) TERMINAL PN NAME NO. PZ I/O NAME NO. DESCRIPTION I/O P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB1 57 I/O P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x1 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DVCC1 1 P6.3 2 I/O Digital supply voltage, positive terminal. General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x1 Terminal Functions (Continued) TERMINAL PN NAME I/O DESCRIPTION NO. S29 41 O LCD segment output 29 S30 42 O LCD segment output 30 S31 43 O LCD segment output 31 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x1 Terminal Functions (Continued) TERMINAL PN NAME I/O DESCRIPTION NO. P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input P1.5/TACLK/ ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) P1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DVCC1 1 P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC P6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x Terminal Functions (Continued) TERMINAL PN NAME I/O DESCRIPTION NO. S29 41 O LCD segment output 29 S30 42 O LCD segment output 30 S31 43 O LCD segment output 31 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 MSP430x44x Terminal Functions (Continued) TERMINAL PN NAME I/O DESCRIPTION NO. P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input P1.5/TACLK/ ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) P1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 module enable registers 1 and 2 7 UTXE0 Address 04h rw–0 6 URXE0 USPIE0 5 4 3 1 0 2 1 0 rw–0 URXE0: USART0: UART mode receive enable UTXE0: USART0: UART mode transmit enable USPIE0: USART0: SPI mode transmit and receive enable Address 2 7 6 5 UTXE1 05h rw–0 4 URXE1 USPIE1 3 rw–0 URXE1: USART1: UART mode receive enable (MSP430F44x(1) devices only) UTXE1:
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056. digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6: D D D D All individual I/O bits are independently programmable.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 USART0 The MSP430x43x(1) and the MSP430x44x(1) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 Timer_B7 (MSP430x44x(1) only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 Comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC12 (not implemented in MSP430x43x1 and MSP430x44x1) The ADC12 module supports fast, 12-bit analog-to-digital conversions.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer_B7/ _ Timer_B3 (see Note 1) Capture/compare register 6 TBCCR6 019Eh Capture/compare register 5 TBCCR5 019Ch Capture/compare register 4 TBCCR4 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 01
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash 34 Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h ADC12 Conversion memory 15 (not implemented in Conversion memory 14 MSP430F43x1 and Conversion memory 13 MSP430F44x1) Conversion memory 12 ADC12MEM15 015Eh ADC12MEM14 015Ch ADC12MEM13 015Ah ADC12MEM12
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS LCD LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode LCDM20 : LCDM16 LCDM15 : LCDM1 LCDCTL 0A4h : 0A0h 09Fh : 091h 090h USART1 (MSP430F44x(1) only) Transmit buffer U1TXBUF 07Fh Receive buffer U1RXBUF 07Eh Baud rate U1BR1 07Dh Baud rate U1BR0 07Ch Modulation control U1MCTL 07
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P4 Port P3 Port P2 Port P1 Special functions p Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 selectio
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution VCC (AVCC = DVCC1 = DVCC2 = VCC) (see Note 1) MSP430F43x(1), MSP430F44x(1) 1.8 3.6 V Supply voltage during program execution, SVS enabled, PORON=1 (see Note 1 and Note 2) VCC (AVCC = DVCC1 = DVCC2 = VCC) MSP430F43x(1), MSP430F44x(1) 2 3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS Active mode (see Note 1), f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32768 Hz XTS_FLL=0, SELM=(0,1) TA = −40°C 40°C to 85°C I(LPM0) Low power mode, (LPM0) Low-power (see Note 1 and Note 4) TA = −40°C
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6 PARAMETER VIT+ Positive going input threshold voltage Positive-going VIT− Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ − VIT−) VCC MIN TYP MAX 2.2 V 1.1 1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, P6 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS VCC MIN IOH(max) = −1.5 mA (See Note 1) 2.2 V VCC−0.25 VCC IOH(max) = −6 mA (See Note 2) 2.2 V VCC−0.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3, P4, P5, and P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25 TA = 25°C VCC = 2.2 V P2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS VCC MIN TYP MAX f = 1 MHz td(LPM3) 6 f = 2 MHz Delay time UNIT 6 2.2 V/3 V f = 3 MHz µs 6 RAM PARAMETER TEST CONDITIONS VRAMh MIN CPU halted (see Note 1) TYP MAX 1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS I(CC) CAON 1 CARSEL CAON=1, CARSEL=0, 0 CAREF CAREF=0 0 I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=1/2/3, No load at P1.6/CA0 and P1.7/CA1 V(Ref025) V(Ref050) Voltage @ 0.25 V V CC MIN TYP MAX 2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 650 VCC = 2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP td(BOR) dVCC/dt ≤ 3 V/s (see Figure 10) VCC(start) Vhys(B_IT−) t(reset) UNIT 2000 µs 0.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 typical characteristics (Continued) VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − µs tpw − Pulse Width − µs Figure 12.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 typical characteristics Software Sets VLD>0: SVS is Active VCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) BrownOut Region Brownout Region Brownout 1 0 td(BOR) SVSOut t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 13.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER MIN f(DCOCLK) f(DCO=2) FN 8 FN 4 FN 3 FN 2 0; DCOPLUS = 1 FN_8=FN_4=FN_3=FN_2=0; f(DCO=27) FN 8 FN 4 FN 3 FN 2 0; DCOPLUS = 1 FN_8=FN_4=FN_3=FN_2=0; FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 f(DCO=2) VCC = 2.2 V/3 V TYP MAX 1 VCC = 2.2 V 0.3 0.65 1.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 Sn - Stepsize Ratio between DCO Taps electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 1.17 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 16.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER TEST CONDITIONS OSCCAPx = 0h CXIN CXOUT VIL VIH Integrated input capacitance Integrated output capacitance Input levels at XIN VCC MIN TYP 2.2 V / 3 V 2.2 V/3 V 10 OSCCAPx = 2h 2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(P6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER TEST CONDITIONS Positive built-in built in reference voltage output VREF+ MIN REF2_5V = 1 for 2.5 V IVREF+ ≤ IVREF+max 3V 2.4 2.5 2.6 REF2_5V = 0 for 1.5 V IVREF+ ≤ IVREF+max 2.2 V/3 V 1.44 1.5 1.56 VREF+ + 0.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 DVCC1/DVCC2 From Power Supply + − 10 µ F DVSS1/DVSS2 100 nF AVCC + − 10 µ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] AVSS 10 µ F VREF+ or VeREF+ 100 nF VREF−/VeREF− + − 10 µ F MSP430F44x 100 nF + − Apply External Reference MSP430F43x 100 nF Figure 19.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters 2.2V/3 V 0.45 5 6.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS VCC MIN TYP MAX REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 40 120 3V 60 160 ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.2 V 986 986±5% VSENSOR 3V 986 986±5% 2.2 V 3.55 3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and Erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION input/output schematics port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic CAPD.x P1SEL.x 0: Input 1: Output 0 P1DIR.x Direction Control From Module P1OUT.x 1 0 P1.x 1 Module X OUT Bus Keeper P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1IN.x EN D Module X IN P1IE.x P1IRQ.x P1IFG.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P1, P1.6, P1.7, input/output with Schmitt trigger Pad Logic Note: Port function is active if CAPD.6 = 0 CAPD.6 P1SEL.6 0: Input 1: Output 0 P1DIR.6 P1.6/ CA0 1 P1DIR.6 0 P1OUT.6 1 DVSS Bus Keeper P1IN.6 EN D unused P1IE.7 P1IRQ.07 EN Interrupt Edge Select Q P1IFG.7 Set P1IES.x P1SEL.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger Pad Logic DVSS DVSS P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module 1 0 1 P2OUT.x Module X OUT Bus Keeper P2.0/TA2 P2.4/UTXD0 P2IN.x P2.5/URXD0 EN Module X IN D P2IE.x P2IRQ.x P2IFG.x EN Interrupt Edge Select Q Set P2IES.x Note: P2SEL.x x {0,4,5} PnSel.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P2, P2.1 to P2.3, input/output with Schmitt trigger Pad Logic DVSS DVSS Module IN of pin P1.3/TBOUTH/SVSOUT P1DIR.3 P1SEL.3 P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module P2OUT.x 1 0 1 Module X OUT Bus Keeper P2.1/TB0 P2.2/TB1 P2IN.x P2.3/TB2 EN D Module X IN P2IE.x P2IRQ.x Q P2IFG.x EN Interrupt Edge Select Set P2IES.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P2, P2.6 to P2.7, input/output with Schmitt trigger 0: Port active 1: Segment xx function active Pad Logic Port/LCD‡ Segment xx‡ P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module 1 0 P2OUT.x 1 Module X OUT Bus Keeper P2.6/CAOUT/S19‡ P2.7/ADC12CLK/S18‡ P2IN.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P3, P3.0 to P3.3, input/output with Schmitt trigger MSP430x43x(1)IPN (80-Pin) Only 0: Port active 1: Segment xx function active LCDM.5 LCDM.6 LCDM.7 Pad Logic Segment xx x43xIPZ and x44xIPZ have no segment function on Port P3: Both lines are low. P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module 1 0 1 P3OUT.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P3, P3.4 to P3.7, input/output with Schmitt trigger LCDM.7† or DVSS‡ 0: Port active 1: Segment xx function active Pad Logic Segmentxx† or DVSS‡ TBOUTHiZ# or DVSS§ P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module P3OUT.x 1 0 1 Module XOUT Bus Keeper ’x43x(1)IPN 80-Pin ’x43x(1)IPZ ’x44x(1) 100-Pin P3IN.x P3.4/S27 P3.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P4, P4.0 to P4.7, input/output with Schmitt trigger 0: Port active 1: Segment xx function active Pad Logic Port/LCD§ Segment xx P4SEL.x 0: Input 1: Output 0 P4DIR.x Direction Control From Module 1 0 1 P4OUT.x Module X OUT Bus Keeper x43x(1)IPN 80-Pin QFP: x43x(1)IPZ 100-Pin QFP: P4.7/S2 P4.6/S3 P4.5/S4 P4.3/S6 P4.4/S5 P4.2/S7 P4.1/S8 P4.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P4, P4.0 to P4.7, input/output with Schmitt trigger (continued) Direction Control for SIMO1 and UCLK1 Direction Control for SOMI1 SYNC SYNC MM DCM_SIMO1 DCM_UCLK1 MM DCM_SOMI1 STC STC STE STE port P5, P5.0 to P5.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P5, P5.2 to P5.4, input/output with Schmitt trigger 0: Port active 1: LCD function active Port/LCD LCD signal Pad Logic P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module 1 0 1 P5OUT.x Module X OUT Bus Keeper P5.2/COM1 P5.3/COM2 P5.4/COM3 P5IN.x EN Module X IN D Note: 66 2
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P5, P5.5 to P5.7, input/output with Schmitt trigger 0: Port active 1: LCD function active Port/LCD LCD signal Pad Logic P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module 1 0 1 P5OUT.x Module X OUT Bus Keeper P5.5/R13 P5.6/R23 P5.7/R33 P5IN.x EN Module X IN D Note: 5
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P6, P6.0 to P6.6, input/output with Schmitt trigger P6SEL.x 0 P6DIR.x Direction Control From Module 1 0: Input 1: Output Pad Logic P6.0/A0 .. P6.6/A6 0 P6OUT.x Module X OUT 1 Bus Keeper P6IN.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION port P6, P6.7, input/output with Schmitt trigger P6SEL.x VLP(SVS)=15 0 P6DIR.x Direction Control From Module 1 0: Input 1: Output Pad Logic P6.7/A7/SVSIN 0 P6OUT.x Module X OUT 1 Bus Keeper P6IN.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled by JTAG DVCC TDI Burn and Test Fuse TDI/TCLK Test and Emulation DVCC TMS Module TMS DVCC TCK TCK RST/NMI Tau ~ 50 ns Brownout TCK 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 G D U S G D U S
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 Data Sheet Revision History Literature Number Summary SLAS344E Added MSP430F43x1 devices Updated functional block diagram (page 6) Clarified test conditions in recommended operating conditions table (page 27) Clarified test conditions in electrical characteristics table (page 28) Added Port 2 through Port 5 to leakage current table (page 29) Corrected y-axis unit on Figures 6 and
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing MSP430F4351IPNR LQFP MSP430F4351IPZR MSP430F435IPNR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.0 Q2 LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 LQFP PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F4351IPNR LQFP MSP430F4351IPZR LQFP PN 80 1000 367.0 367.0 45.0 PZ 100 1000 367.0 367.0 45.0 MSP430F435IPNR LQFP MSP430F435IPZR LQFP PN 80 1000 367.0 367.0 45.0 PZ 100 1000 367.0 367.0 MSP430F4361IPNR LQFP 45.0 PN 80 1000 367.0 367.0 45.
MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.