Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 38 16-Bit 25 MHz I/O number 29

MSP430F5172, MSP430F5152, MSP430F5132

MSP430F5171, MSP430F5151, MSP430F5131

www.ti.com

SLAS619K –AUGUST 2010–REVISED JANUARY 2014

MSP430F51x2 and MSP430F51x1 Mixed Signal Microcontrollers

FEATURES

• Low Supply Voltage Range:

• 16-Bit Timer TA0 With Three Capture/Compare

3.6 V Down to 1.8 V Registers

• Ultra-Low-Power Consumption • Universal Serial Communication Interfaces

(1)

– Active Mode (AM): 180 µA/MHz – USCI_A0 Supports

– Standby Mode (LPM3 WDT Mode, 3 V): – Enhanced UART Supports Auto-

1.1 µA Baudrate Detection

– Off Mode (LPM4 RAM Retention, 3 V): – IrDA Encoder and Decoder

0.9 µA

– Synchronous SPI

– Shutdown Mode (LPM4.5, 3 V): 0.25 µA

– USCI_B0 Supports

• Wakeup From Standby Mode in Less Than

– I

5 µs

– Synchronous SPI

• 16-Bit RISC Architecture, Extended Memory,

• 10-Bit 200-ksps Analog-to-Digital Converter

40-ns Instruction Cycle Time

(ADC)

• Flexible Power Management System

– Internal Reference

– Fully Integrated LDO With Programmable

– Sample-and-Hold

Regulated Core Supply Voltage

– Autoscan Feature

– Supply Voltage Supervision, Monitoring,

– Up to Eight External Channels, Two Internal

and Brownout

Channels, Including Temperature Sensor

(1)

• Unified Clock System

• Up to 16-Channel On-Chip Comparator

– FLL Control Loop for Frequency

Including an Ultralow-Power Mode

(1)

Stabilization

• Serial Onboard Programming, No External

– Low-Power Low-Frequency Internal Clock

Programming Voltage Needed

Source (VLO)

• Table 1 Summarizes Available Family

– Low-Frequency Trimmed Internal Reference

Members

Source (REFO)

• Available in 40-Pin QFN (RSB), 38-Pin TSSOP

– 32-kHz Crystals (XT1)

(DA), and 40-Pin Die-Sized BGA (YFF)

– High-Frequency Crystals up to 25 MHz

Packages

(XT1)

• For Complete Module Descriptions, See the

• Hardware Multiplier Supports 32-Bit

MSP430x5xx and MSP430x6xx Family User's

Operations

Guide (SLAU208)

• Three-Channel DMA

APPLICATIONS

• Up to Twelve 5-V-Tolerant Digital Push/Pull

I/Os With Up to 20-mA Drive Strength

(1)

• Analog and Digital Sensor Systems

• 16-Bit Timer TD0 With Three Capture/Compare

• LED Lighting

Registers and Support of High-Resolution

• Digital Power Supply

Mode

• Motor Control

• 16-Bit Timer TD1 With Three Capture/Compare

• Remote Controls

Registers and Support of High-Resolution

• Thermostats

Mode

(1) Full functionality in the 40-pin QFN package options. For the

available features of other packages, see Terminal Functions.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (106 pages)

PAGE 1
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 MSP430F51x2 and MSP430F51x1 Mixed Signal Microcontrollers FEATURES 1 • 23 • • • • • • • • • • Low Supply Voltage Range: 3.6 V Down to 1.8 V Ultra-Low-Power Consumption – Active Mode (AM): 180 µA/MHz – Standby Mode (LPM3 WDT Mode, 3 V): 1.1 µA – Off Mode (LPM4 RAM Retention, 3 V): 0.9 µA – Shutdown Mode (LPM4.5, 3 V): 0.
PAGE 2
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com DESCRIPTION The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
PAGE 3
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Functional Block Diagram, MSP430F51x2 DVCC AVCC RST/NMI DVSS AVSS XIN XOUT Unified Clock System ACLK SMCLK DVIO DVSS 32KB 16KB 8KB 2KB 2KB 1KB Power Management Flash RAM LDO SVM/SVS Brownout P1.x 8 P2.x 8 P3.x 8 PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com AVSS PJ.5/XIN PJ.4/XOUT AVCC P3.7/PM_TA0.0/A6*/CB10 P3.6/PM_TA0.1/A7*/VEREF-*/CB11 P3.5/PM_TA0.2/A8*/VEREF+*/CB12 RST/NMI/SBWTDIO TEST/SBWTCK P3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Pin Designation, MSP430F51x2IDA and MSP430F51x1IDA AVCC PJ.4/XOUT PJ.5/XIN AVSS P1.0/PM_UCA0CLK/PM_UCB0STE/A0*/CB0 P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1*/CB1 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2*/CB2 P1.3/PM_UCB0CLK/PM_UCA0STE/A3*/CB3 P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4*/CB4 P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5*/CB5 PJ.0/SMCLK/TDO/CB6 PJ.1/MCLK/TDI/TCLK/CB7 PJ.2/ADC10CLK/TMS/CB8 PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Pin Designation, MSP430F51x2IYFF and MSP430F51x1IYFF YFF PACKAGE (BALL-SIDE VIEW) YFF PACKAGE (TOP VIEW) D P3.3 P3.4 P3.7 P3.6 XOUT XIN XIN XOUT P3.6 P3.7 P3.4 P3.3 G6 G5 G4 G3 G2 G1 G1 G2 G3 G4 G5 G6 DVCC P3.2 RST P3.5 P1.0 P1.1 P1.1 P1.0 P3.5 RST P3.2 DVCC F6 F5 F4 F3 F2 F1 F1 F2 F3 F4 F5 F6 DVSS PJ.6 AVCC AVSS P1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Terminal Functions Table 3. Terminal Functions TERMINAL NAME P1.0/ PM_UCA0CLK/
PM_UCB0STE/ A0 (2)/ CB0 P1.1/ PM_UCA0TXD/ PM_UCA0SIMO/ A1 (2)/ CB1 P1.2/ PM_UCA0RXD/ PM_UCA0SOMI/ A2 (2)/ CB2 P1.3/ PM_UCB0CLK/
PM_UCA0STE/ A3 (2)/ CB3 P1.4/ PM_UCB0SIMO/ PM_UCB0SDA/ A4 (2)/ CB4 P1.5/ PM_UCB0SOMI/ PM_UCB0SCL/ A5 (2)/ CB5 PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION RSB DA YFF P2.1/ PM_TD1.0 14 18 A2 I/O, DVIO General-purpose digital I/O TD1 CCR0 compare output/capture input P2.2/ PM_TD1.1 15 19 A3 I/O, DVIO General-purpose digital I/O TD1 CCR1 compare output/capture input P2.3/ PM_TD1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 3. Terminal Functions (continued) TERMINAL NAME P3.5/ PM_TA0.2/ A8 (4) VEREF+/ CB12 P3.6/ PM_TA0.1/ A7 (4)/ VEREF-/ CB11 I/O (1) NO.
PAGE 10
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
PAGE 11
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Command-Line Programmer MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
PAGE 13
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Operating Modes The MSP430 has one active mode and six software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
PAGE 15
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
PAGE 17
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Flash Memory The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port Mapping Controller The port mapping controller allows the flexible and reconfigurable mapping of digital functions to Port P1, Port P2, and Port P3. Table 8.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 9. Default Mapping PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION PM_UCA0CLK PM_UCB0STE USCI_A0 clock input/output (direction controlled by USCI) USCI_B0 SPI slave transmit enable (direction controlled by USCI) P1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Oscillator and System Clock The clock system (Unified Clock System, UCS) module includes support for a 32-kHz watch crystal oscillator and high-frequency crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an integrated internal digitally controlled oscillator (DCO).
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 10.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two modules, A and B.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com TD0 TD0 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz / 4-ns resolution. TD0 can support multiple capture/compares, PWM outputs, and interval timing. TD0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 TD1 TD1 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz / 4-ns resolution. TD1 can support multiple capture/compares, PWM outputs, and interval timing. TD1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Comparator_B The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC10_A (MSP430F51x2 Only) The ADC10_A module supports fast, 10-bit analog-to-digital conversions.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Peripheral File Map Table 15.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 16. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 17.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 23.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 28. Port Mapper for Port P3 (Base Address: 01D8h) REGISTER DESCRIPTION REGISTER OFFSET Port P3.0 mapping register P3MAP0 00h Port P3.1 mapping register P3MAP1 01h Port P3.2 mapping register P3MAP2 02h Port P3.3 mapping register P3MAP3 03h Port P3.4 mapping register P3MAP4 04h Port P3.5 mapping register P3MAP5 05h Port P3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 31. Port Registers PJ (Base Addresses: 0320h) REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup/pulldown enable PJREN 06h Port PJ drive strength PJDS 08h Port PJ selection PJSEL 0Ah Table 32.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 34. DMA General Control (Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh Table 35.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 38.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 41.
PAGE 35
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 44.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage VCC applied at DVCC to DVSS –0.3 V to 4.1 V Voltage VIO applied at VIO to DVSS –0.3 V to 6.1 V Voltage applied to any pin (excluding VCORE) (2) –0.3 V to VCC + 0.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Recommended Operating Conditions Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN Supply voltage during program execution and flash programming V(AVCC) = V(DVCC) = VCC (1) (2) VCC 1.8 3.6 V 2.0 3.6 V PMMCOREVx = 0, 1, 2 2.2 3.6 V PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V 5.5 V 85 °C (3) Supply voltage of pins P1.6, P1.7, P2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 16 12 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS I(OH5max) = –1 mA VIO (2) 1.
PAGE 43
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.
PAGE 44
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 30 DVCC = 3.0 V DVIO = 5.
PAGE 46
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1 (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 DVCC = 3.
PAGE 47
MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE DVCC = 3.0 V DVIO = 5.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1 (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0 DVCC = 3.0 V V DD = 5.5 DVIO 3.0 V TA = 85°C TA = 25°C DVCC = 1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Crystal Oscillator, XT1, Low-Frequency Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C IDVCC.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.45 V 1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVMHE = 0, DVCC = 3.6 V I(SVMH) V(SVMH) SVMH current consumption SVMH on or off voltage level SVMH propagation delay t(SVMH) SVMH on or off delay time MAX UNIT 0 nA SVMHE = 1, DVCC = 3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Wake Up From Low-Power Modes over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLK ≥ 4 MHz 3 6.5 1 MHz < fMCLK < 4 MHz 4 8.0 150 165 µs Wake-up time from LPM4.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24 and Figure 25) PARAMETER fUSCI USCI input clock frequency TEST CONDITIONS PMMCOREV = 0 tSU,MI SOMI input data setup time PMMCOREV = 3 PMMCOREV = 0 tHD,MI SOMI input data hold time PMMCOREV = 3 tVALID,MO 1.8 V 55 3V 38 2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,MI tSU,MI SOMI tVALID,MO SIMO Figure 24. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 25.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tACC tDIS tVALID,SOMI SOMI Figure 26. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tACC tDIS tVALID,SO SOMI Figure 27.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT ±1.0 ±1.0 Differential linearity error (VEREF+ – VEREF-)min ≤ (VEREF+ – VEREF-), CVEREF+ = 20 pF ±1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC MIN Supply voltage TYP 1.8 MAX 3.6 1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Timer_D, Power Supply and Reference Clock Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER DVCC Digital supply voltage fREF,DCO Timer_D input reference clock frequency I(DVCC) at 64-MHz Timer_D clock, clock generator only TEST CONDITIONS VCC V(DVSS) = 0 V MIN TYP MAX UNIT 1.8 3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Timer_D, Local Clock Generator Frequency (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 150 230 360 kHz 130 230 350 kHz 100 230 340 kHz fHRCG = 8 MHz, TDHREGEN = 0 ±0.17 %/°C fHRCG = 16 MHz, TDHREGEN = 0 ±0.16 %/°C ±0.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS DVCC(PGM/ERASE) Program and erase supply voltage MIN TYP 1.8 MAX UNIT 3.6 V IPGM Supply current from DVCC during program 3 5 mA IERASE Supply current from DVCC during erase 2 6.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = x Pad Logic To Comparator_B From Comparator_B CBPD.y Pad Logic P1REN.x P1MAP.x = PMAP_ANALOG P1DIR.x 0 From Port Mapping 1 P1OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x P1.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 46. Port P1 (P1.0 to P1.5) Pin Functions PIN NAME (P1.x) P1.0/ x 0 P1.x (I/O) PM_UCA0CLK/ PM_UCB0STE/ UCA0CLK/UCB0STE A0/ A0 (4) CB0 CONTROL BITS/SIGNALS (1) FUNCTION (2) (3) CB0 P1.1/ 1 P1.x (I/O) P1DIR.x P1SEL.x P1MAP.x CBPD.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 From Port Mapping 1 P1OUT.x 0 From Port Mapping 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P1.6/PM_TD0_0 P1.7/PM_TD0_1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To Port Mapping D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 0 DVIO 1 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To Port Mapping DVSS P2.0/PM_TD0_2 P2.1/PM_TD1_0 P2.2/PM_TD1_1 P2.3/PM_TD1_2 P2.4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0_0 P2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 48. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/ x 0 PM_TD0.2 CONTROL BITS/SIGNALS FUNCTION P2DIR.x P2SEL.x I: 0; O: 1 0 X 0 1 default TD0.TA2 1 1 default P2.x (I/O) I: 0; O: 1 0 X TD1.CCI0A 0 1 default TD1.TA0 1 1 default P2.x (I/O) I: 0; O: 1 0 X TD1.CCI1A 0 1 default TD1.TA1 1 1 default P2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port P3, P3.0 and P3.1, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVIO 1 1 Direction 0: Input 1: Output P3.0/PM_TEC1FLT2/PM_TD1_1 P3.1/PM_TEC1FLT0/PM_TD1_2 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN To Port Mapping D Table 49. Port P3 (P3.0 and P3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port P3, P3.2 and P3.3, Input/Output With Schmitt Trigger Pad Logic To Comparator_B From Comparator_B CBPD.y P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.2/PM_TD0_0/PM_SMCLK/CB14 P3.3/PM_TA0CLK/PM_CBOUT/CB13 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port P3, P3.4, Input/Output With Schmitt Trigger Pad Logic To DCO CBPD.y P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.4/PM_TD0CLK/PM_MCLK P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x Bus Holder EN To Port Mapping D Table 51. Port P3 (P3.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port P3, P3.5, Input/Output With Schmitt Trigger Pad Logic To ADC10 reference VREF- To ADC10 INCHx = x To Comparator_B From Comparator_B CBPD.y P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.5/PM_TA0_2/A8/VREF+/CB12 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port P3, P3.6, Input/Output With Schmitt Trigger Pad Logic To ADC10 reference VREF- To ADC10 INCHx = x To Comparator_B From Comparator_B CBPD.y P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.6/PM_TA0_1/A7/VREF-/CB11 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port P3, P3.7, Input/Output With Schmitt Trigger Pad Logic To ADC10 INCHx = x Pad Logic To Comparator_B From Comparator_B CBPD.y Pad Logic P3REN.x P3MAP.x = PMAP_ANALOG P3DIR.x 0 From Port Mapping 1 P3OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.7/PM_TA0_0/A6/CB10 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic To Comparator_B From Comparator_B CBPD.x PJREN.x PJDIR.x 0 DVCC 1 PJOUT.x 00 From JTAG 01 SMCLK 10 DVSS 0 DVCC 1 1 PJDS.0 0: Low drive 1: High drive 11 PJ.0/SMCLK/TDO/CB6 PJSEL.x From JTAG PJIN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic To Comparator_B From Comparator_B CBPD.x PJREN.x PJDIR.x DVSS PJOUT.x DVSS 0 DVCC 1 1 0 1 00 From JTAG 01 MCLK/ADC10CLK/ACLK 10 PJDS.x 0: Low drive 1: High drive 11 PJ.1/MCLK/TDI/TCLK/CB7 PJ.2/ADC10CLK/TMSCB8 PJ.3/ACLK/TCK/CB9 PJSEL.x From JTAG PJIN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 55. Port PJ (PJ.0 to PJ.3) Pin Functions CONTROL BITS/ SIGNALS (1) PIN NAME (PJ.x) PJ.0/ x 0 FUNCTION PJ.x (I/O) (2) PJDIR.x PJSEL.x JTAG MODE CBPD.y 0 I: 0; O: 1 0 0 SMCLK/ SMCLK 1 1 0 0 TDO/ TDO (3) X X 1 X CB6 CB6 PJ.1/ 1 MCLK/ PJ.x (I/O) (2) MCLK TDI/TCLK/ TDI/TCLK CB7 CB7 PJ.2/ 2 ADC10CLK/ PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port PJ.4, Input/Output With Schmitt Trigger Pad Logic From XT1 PJREN.4 PJDIR.4 DVSS 0 DVCC 1 1 0 1 PJOUT.4 0 DVSS 1 PJDS.x 0: Low drive 1: High drive PJSEL.5 XT1BYPASS PJ.4/XOUT PJIN.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Port PJ.5, Input/Output With Schmitt Trigger Pad Logic To XT1 PJREN.5 PJDIR.5 DVSS 0 DVCC 1 1 0 1 PJOUT.5 0 Module X OUT 1 PJ.5/XIN PJDS.0 0: Low drive 1: High drive PJSEL.5 PJIN.5 Bus Keeper EN Module X IN D Table 56. Port PJ (PJ.4 and PJ.5) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (PJ.x) PJ.4/ x 4 XOUT PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Port PJ.6, Input/Output With Schmitt Trigger Pad Logic To Comparator_B From Comparator_B CBPD..x PJREN.x PJDIR.x 0 From Module 1 PJOUT.x 0 From Module 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output PJ.6/TD1CLK/TD0_1/CB15 PJDS.x 0: Low drive 1: High drive PJSEL.x PJIN.x Bus Holder EN To Port Mapping D Table 57. Port PJ (PJ.6) Pin Functions PIN NAME (PJ.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 DEVICE DESCRIPTORS Table 58 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 58.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 58.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 58.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Table 59. 'F51x1 Device Descriptor Table(1) (continued) Timer_D0 Calibration Timer_D1 Calibration Peripheral Descriptor 92 Description Address Size bytes REF 2.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 www.ti.com SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 Table 59.
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MSP430F5172, MSP430F5152, MSP430F5132 MSP430F5171, MSP430F5151, MSP430F5131 SLAS619K – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY REVISION 94 COMMENTS SLAS619 Product Preview release SLAS619A Production Data release SLAS619B Changed Table 7. SLAS619C Changed Comparator_B VREF MAX from ±1% to ±1.5% for all test conditions in Comparator_B. SLAS619D Table 1, Corrected number of I/Os for all entries.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 22-Jan-2014 Status (1) MSP430F5172IYFFT ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFF 40 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) M430F5172 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F5131IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F5131IRSBR WQFN RSB 40 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 MSP430F5131IRSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F5131IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F5131IRSBR WQFN RSB 40 3000 367.0 367.0 35.0 MSP430F5131IRSBT WQFN RSB 40 250 210.0 185.0 35.0 MSP430F5132IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F5132IRSBR WQFN RSB 40 3000 367.0 367.0 35.0 MSP430F5132IRSBT WQFN RSB 40 250 210.
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D: Max = 3.09 mm, Min = 3.03 mm E: Max = 2.79 mm, Min = 2.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.