Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 16-Bit 25 MHz I/O number 31

MSP430F5310, MSP430F5309

MSP430F5308, MSP430F5304

www.ti.com

SLAS677E –SEPTEMBER 2010–REVISED NOVEMBER 2013

MSP430F5310 and MSP430F530x Mixed-Signal Microcontrollers

Check for Samples: MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304

FEATURES

• Low Supply-Voltage Range:

– Low-Frequency Trimmed Internal Reference

3.6 V Down to 1.8 V Source (REFO)

• Ultra-Low-Power Consumption – 32-kHz Watch Crystals (XT1)

– Active Mode (AM) – High-Frequency Crystals up to 32 MHz

All System Clocks Active (XT2)

– 195 µA/MHz (Typical) at 8 MHz, 3 V, • 16-Bit Timer TA0, Timer_A With Five

Flash Program Execution Capture/Compare Registers

– 115 µA/MHz (Typical) at 8 MHz, 3 V, RAM • 16-Bit Timer TA1, Timer_A With Three

Program Execution Capture/Compare Registers

– Standby Mode (LPM3) • 16-Bit Timer TA2, Timer_A With Three

Capture/Compare Registers

– Real-Time Clock (RTC) With Crystal,

Watchdog, and Supply Supervisor • 16-Bit Timer TB0, Timer_B With Seven

Operational, Full RAM Retention, Fast Capture/Compare Shadow Registers

Wake Up:

• Two Universal Serial Communication

1.9 µA (Typical) at 2.2 V,

Interfaces (USCIs)

2.1 µA (Typical) at 3 V

– USCI_A0 and USCI_A1 Each Support:

– Low-Power Oscillator (VLO), General-

– Enhanced UART Supports Auto-

Purpose Counter, Watchdog, and

Baudrate Detection

Supply Supervisor Operational, Full

– IrDA Encoder and Decoder

RAM Retention, Fast Wake Up:

– Synchronous SPI

1.4 µA (Typical) at 3 V

– USCI_B0 and USCI_B1 Each Support:

– Off Mode (LPM4)

Full RAM Retention, Supply Supervisor – I

Operational, Fast Wake Up:

– Synchronous SPI

1.1 µA at 3 V (Typical)

• Integrated 3.3-V Power System

– Shutdown Mode (LPM4.5)

• 10-Bit Analog-to-Digital Converter (ADC) With

0.18 µA at 3 V (Typical)

Window Comparator

• Wake Up From Standby Mode in Less Than

• Comparator

5 µs

• Hardware Multiplier Supports 32-Bit

• 16-Bit RISC Architecture, Extended Memory,

Operations

Up to 25-MHz System Clock

• Serial Onboard Programming, No External

• Flexible Power Management System

Programming Voltage Needed

– Fully Integrated LDO With Programmable

• Three-Channel Internal DMA

Regulated Core Supply Voltage

• Basic Timer With RTC Feature

– Supply Voltage Supervision, Monitoring,

• Table 1 Summarizes Family Members

and Brownout

• For Complete Module Descriptions, See the

• Unified Clock System

MSP430x5xx and MSP430x6xx Family User's

– FLL Control Loop for Frequency

Guide (SLAU208)

Stabilization

– Low-Power Low-Frequency Internal Clock

Source (VLO)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (103 pages)

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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 MSP430F5310 and MSP430F530x Mixed-Signal Microcontrollers Check for Samples: MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304 FEATURES 1 • 23 • • • • • Low Supply-Voltage Range: 3.6 V Down to 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com APPLICATIONS • • • • • • Analog and Digital Sensor Systems Digital Motor Control Remote Controls Thermostats Digital Timers Hand-Held Meters DESCRIPTION The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Functional Block Diagram – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRG, MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 6KB Flash RAM Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PA P2.x P3.x PB P4.x P5.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Pin Designation – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRGC RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK P5.3/XT2OUT P5.2/XT2IN AVSS2 NC LDOO LDOI PU.1 NC PU.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ, MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK CPUXV2 and Working Registers 32KB 24KB 16KB 6KB Flash RAM Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PA P2.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Pin Designation – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ, MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT PU.0 VSSU NC PU.1 LDOI NC LDOO P5.2/XT2IN AVSS2 P5.3/XT2OUT TEST/SBWTCK RST/NMI/SBWTDIO RGZ OR PT PACKAGE (TOP VIEW) 1 48 47 46 45 44 43 42 41 40 39 38 37 36 P4.7/PM_NONE 2 35 P4.6/PM_NONE P6.2/CB2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/CB3/A3 4 33 P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Functional Block Diagram – MSP430F5304IRGZ, MSP430F5304IPT XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK 8KB SMCLK Flash 6KB RAM MCLK CPUXV2 and Working Registers Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PA P2.x I/O Ports P1, P2 1×8 I/Os 1×1 I/Os Interrupt, Wakeup PA 1×9 I/Os P3.x PB P4.x P5.x PC P6.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Pin Designation – MSP430F5304IRGZ, MSP430F5304IPT P6.0/A0 P6.1/A1 PU.0 VSSU PU.1 NC LDOI NC LDOO AVSS2 P5.2/XT2IN TEST/SBWTCK P5.3/XT2OUT RST/NMI/SBWTDIO RGZ OR PT PACKAGE (TOP VIEW) 1 48 47 46 45 44 43 42 41 40 39 38 37 36 P4.7/PM_NONE 2 35 P4.6/PM_NONE P6.2/A2 3 34 P4.5/PM_UCA1RXD/PM_UCA1SOMI P6.3/A3 4 33 P4.4/PM_UCA1TXD/PM_UCA1SIMO P5.0/A8/VeREF+ 5 32 P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME I/O (1) DESCRIPTION RGZ, RGC ZQE PT P6.4/CB4/A4 5 N/A C1 I/O General-purpose digital I/O Comparator_B input CB4 (not available on RGZ or PT package devices) Analog input A4 – ADC (not available on RGZ or PT package devices) P6.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 2. Terminal Functions (continued) TERMINAL NO. NAME I/O (1) DESCRIPTION RGZ, RGC ZQE PT P2.1/TA1.2 27 N/A G6 I/O General-purpose digital I/O with port interrupt TA1 CCR2 capture: CCI2A input, compare: Out2 output P2.2/TA2CLK/SMCLK 28 N/A J6 I/O General-purpose digital I/O with port interrupt TA2 clock signal TA2CLK input ; SMCLK output P2.3/TA2.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME I/O (1) DESCRIPTION RGZ, RGC ZQE PT P4.5/PM_UCA1RXD/ PM_UCA1SOMI 46 34 C9 I/O General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Receive data – USCI_A1 UART mode Default mapping: Slave out, master in – USCI_A1 SPI mode P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Command-Line Programmer MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Short-Form Description CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Memory Organization Table 4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by user-defined password. Use of the UART BSL requires external access to the six pins shown in Table 5.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 8.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 9. Default Mapping PIN 22 PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI) P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, as well as configuration management (device descriptors).
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using the DMA controller can increase the throughput of peripheral modules.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 13.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC10_A (Link to User's Guide) The ADC10_A module supports fast 10-bit analog-to-digital conversions.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Peripheral File Map Table 16.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 17. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 18.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 24.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 27.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 29.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 32.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 35.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 36.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 37.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 39.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 42.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE, LDOI) (2) –0.3 V to VCC + 0.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Recommended Operating Conditions Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN Supply voltage during program execution and flash programming(AVCC = DVCC1/2 = DVCC) (1) (2) VCC NOM MAX UNIT PMMCOREVx = 0 1.8 3.6 V PMMCOREVx = 0, 1 2.0 3.6 V PMMCOREVx = 0, 1, 2 2.2 3.6 V PMMCOREVx = 0, 1, 2, 3 2.4 3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) 44 Flash RAM EXECUTION MEMORY Flash RAM VCC 3V 3V PMMCOREVx 1 MHz 8 MHz 12 MHz TYP MAX 1.74 2.58 2.78 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER LPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) ILPM4 0 73 77 85 80 80 97 3V 3 79 83 92 88 95 105 2.2 V 0 6.5 6.5 8 7.5 8 11 3V 3 7.0 7.0 9 7.9 8.9 13 0 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Schmitt-Trigger Inputs – General Purpose I/O (1) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C IDVCC.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V Measured at ACLK (2) 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) SVS current consumption V(SVSH_IT+) tpd(SVSH) t(SVSH) dVDVCC/dt (1) SVSH on voltage level (1) SVSH off voltage level (1) SVSH propagation delay SVSH on or off delay time MAX 0 SVSHE = 1, DVCC = 3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption 0 SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 V(SVMH) SVMH on or off voltage level 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tτ (1) UART receive deglitch time TEST CONDITIONS (1) VCC MIN TYP MAX 2.2 V 50 600 3V 50 600 UNIT ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 8. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 9.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 10. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 11.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 1.4 V ≤ (VeREF+ – VeREF–)min ≤ 1.6 V ED Differential linearity error (VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–), CVREF+ = 20 pF 2.2 V, 3 V ±1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VREF+ AVCC(min) IREF+ Positive built-in reference voltage AVCC minimum voltage, Positive built-in reference active Operating supply current into AVCC terminal (2) TEST CONDITIONS VCC MIN (1) TYP MAX REFVSEL = {2} for 2.5 V, REFON = 1 3V 2.51 ±1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 3.6 1.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Ports PU.0 and PU.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VLDOO = 3.3 V ± 10%, IOH = -25 mA. See Figure 14 for typical characteristics. VOL Low-level output voltage VLDOO = 3.3 V ± 10%, IOL = 25 mA. See Figure 13 for typical characteristics.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 90 VCC = 3.0 V TA = 25 ºC IOL - Typical Low-Level Output Current - mA 80 VCC = 3.0 V TA = 85 ºC VCC = 1.8 V TA = 25 ºC 70 60 50 VCC = 1.8 V TA = 85 ºC 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VOL - Low-Level Output Voltage - V Figure 13. Ports PU.0, PU.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 LDO-PWR (LDO Power System) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VLAUNCH LDO input detection threshold VLDOI LDO input voltage VLDO LDO output voltage VLDO_EXT LDOO terminal input voltage with LDO disabled LDO disabled ILDOO Maximum external current from LDOO terminal LDO is on VCC TYP 3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 From module 1 P1OUT.x 0 From module 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To module P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 D P1IE.x EN P1IRQ.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 45. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION CONTROL BITS AND SIGNALS P1DIR.x P1SEL.x P1.0 (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.CCI2A 0 1 TA0.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 From module 1 P2OUT.x 0 From module 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UB0STE/UCA0CLK P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To module D P2IE.x EN To module Q P2IFG.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 46. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 x 0 1 2 3 4 5 6 FUNCTION P2.0 (I/O) CONTROL BITS AND SIGNALS (1) P2DIR.x P2SEL.x I: 0; O: 1 0 TA1.CCI1A 0 1 TA1.1 1 1 P2.1 (I/O) I: 0; O: 1 0 TA1.CCI2A 0 1 TA1.2 1 1 P2.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 From module 1 P3OUT.x 0 From module 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN D To module Table 47. Port P3 (P3.0 to P3.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 from Port Mapping Control 1 P4OUT.x 0 from Port Mapping Control 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 48. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/P4MAP0 x 0 FUNCTION P4.0 (I/O) Mapped secondary digital function P4.1/P4MAP1 1 P4.1 (I/O) Mapped secondary digital function P4.2/P4MAP2 2 P4.2 (I/O) Mapped secondary digital function P4.3/P4MAP3 3 P4.4/P4MAP4 4 P4.3 (I/O) Mapped secondary digital function P4.4 (I/O) Mapped secondary digital function P4.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic to/from Reference to ADC10 INCHx = x P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 From module 1 P5.0/(A8/VeREF+) P5.1/(A9/VeREF–) P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN To module D Table 49. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VeREF+ (2) x 0 FUNCTION P5.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 50. Port P5 (P5.2, P5.3) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.3/XT2OUT (1) (2) (3) 80 x 2 3 FUNCTION P5.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger Pad Logic to XT1 P5REN.4 P5DIR.4 DVSS 0 DVCC 1 1 0 1 P5OUT.4 0 Module X OUT 1 P5DS.4 0: Low drive 1: High drive P5SEL.4 P5.4/XIN P5IN.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Pad Logic to XT1 P5REN.5 P5DIR.5 DVSS 0 DVCC 1 1 0 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5DS.5 0: Low drive 1: High drive P5SEL.5 XT1BYPASS P5IN.5 Bus Keeper EN Module X IN D Table 51. Port P5 (P5.4 and P5.5) Pin Functions PIN NAME (P7.x) P5.4/XIN x 4 FUNCTION P5DIR.x P5SEL.4 P5SEL.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic to ADC10 INCHx = x to Comparator_B from Comparator_B CBPD.x P6REN.x P6DIR.x 0 0 From module 1 0 DVCC 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN To module 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS Bus Keeper D Copyright © 2010–2013, Texas Instruments Incorporated P6.0/CB0/(A0) P6.1/CB1/(A1) P6.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 52. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/CB0/(A0) x 0 FUNCTION P6.0 (I/O) A0 (only on devices with ADC) CB0 (1) P6.1/CB1/(A1) P6.2/CB2/(A2) P6.3/CB3/(A3) P6.4/CB4/(A4) 1 2 3 4 P6.1 (I/O) (1) 84 X X X 1 I: 0; O: 1 0 0 1 X 1 I: 0; O: 1 0 0 P6.2 (I/O) A2 (only on devices with ADC) X 1 X CB2 (1) X X 1 I: 0; O: 1 0 0 P6.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Port PU.0, PU.1 Ports LDOO VSSU Pad Logic PUOPE PU.0 PUOUT0 PUIN0 PUIPE PUIN1 PU.1 PUOUT1 Table 53. Port PU.0, PU.1 Output Functions (1) CONTROL BITS (1) PIN NAME PUOPE PUOUT1 PUOUT0 PU.1/DM PU.0/DP 0 X X Output disabled Output disabled 1 0 0 Output low Output low 1 0 1 Output low Output high 1 1 0 Output high Output low 1 1 1 Output high Output high PU.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 55. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) X I: 0; O: 1 (4) PJ.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com DEVICE DESCRIPTORS Table 56 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 56.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 Table 56.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 www.ti.com Table 56.
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MSP430F5310, MSP430F5309 MSP430F5308, MSP430F5304 www.ti.com SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013 REVISION HISTORY REVISION COMMENTS SLAS677 Product Preview release SLAS677A Production Data release SLAS677B Released BGA package. Corrected VCB_REF min and max values by swapping them as they were backward. Added IUSB_LDO and IVBUS_DETECT to USB-PWR table. Added QFN thermal pad connection to pinout drawing and terminal function table. Added LDO and Port U description.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.