Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 64 (9x9) 16-Bit 25 MHz I/O number 47

MSP430F532x

www.ti.com

SLAS678D –AUGUST 2010–REVISED FEBRUARY 2013

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range:

– Low-Frequency Trimmed Internal Reference

3.6 V Down to 1.8 V Source (REFO)

• Ultralow Power Consumption – 32-kHz Watch Crystals (XT1)

– Active Mode (AM): – High-Frequency Crystals Up to 32 MHz

All System Clocks Active (XT2)

290 µA/MHz at 8 MHz, 3 V, Flash Program

• 16-Bit Timer TA0, Timer_A With Five

Execution (Typical)

Capture/Compare Registers

150 µA/MHz at 8 MHz, 3 V, RAM Program

• 16-Bit Timer TA1, Timer_A With Three

Execution (Typical)

Capture/Compare Registers

– Standby Mode (LPM3):

• 16-Bit Timer TA2, Timer_A With Three

Real-Time Clock With Crystal , Watchdog,

Capture/Compare Registers

and Supply Supervisor Operational, Full

• 16-Bit Timer TB0, Timer_B With Seven

RAM Retention, Fast Wake-Up:

Capture/Compare Shadow Registers

1.9 µA at 2.2 V, 2.1 µA at 3 V (Typical)

• Two Universal Serial Communication

Low-Power Oscillator (VLO), General

Interfaces

Purpose Counter, Watchdog, and Supply

Supervisor Operational, Full RAM – USCI_A0 and USCI_A1 Each Support:

Retention, Fast Wake-Up:

– Enhanced UART Supports Auto-

1.4 µA at 3 V (Typical)

Baudrate Detection

– Off Mode (LPM4):

– IrDA Encoder and Decoder

Full RAM Retention, Supply Supervisor

– Synchronous SPI

Operational, Fast Wake-Up:

– USCI_B0 and USCI_B1 Each Support:

1.1 µA at 3 V (Typical)

– I

– Shutdown Mode (LPM4.5):

– Synchronous SPI

0.18 µA at 3 V (Typical)

• Integrated 3.3-V Power System

• Wake-Up From Standby Mode in 3.5 µs

(Typical) • 12-Bit Analog-to-Digital (A/D) Converter With

Internal Reference, Sample-and-Hold, and

• 16-Bit RISC Architecture, Extended Memory,

Autoscan Feature

Up to 25-MHz System Clock

• Comparator

• Flexible Power Management System

• Hardware Multiplier Supporting 32-Bit

– Fully Integrated LDO With Programmable

Operations

Regulated Core Supply Voltage

• Serial Onboard Programming, No External

– Supply Voltage Supervision, Monitoring,

Programming Voltage Needed

and Brownout

• Three Channel Internal DMA

• Unified Clock System

• Basic Timer With Real-Time Clock Feature

– FLL Control Loop for Frequency

Stabilization • Family Members are Summarized in Table 1

– Low-Power Low-Frequency Internal Clock • For Complete Module Descriptions, See the

Source (VLO) MSP430x5xx and MSP430x6xx Family User's

Guide (SLAU208)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (103 pages)

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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • 2 • • • • • Low Supply Voltage Range: 3.6 V Down to 1.8 V Ultralow Power Consumption – Active Mode (AM): All System Clocks Active 290 µA/MHz at 8 MHz, 3 V, Flash Program Execution (Typical) 150 µA/MHz at 8 MHz, 3 V, RAM Program Execution (Typical) – Standby Mode (LPM3): Real-Time Clock With Crystal , Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake-Up: 1.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com DESCRIPTION The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive lowpower modes is optimized to achieve extended battery life in portable measurement applications.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Functional Block Diagram – MSP430F5329IPN, MSP430F5327IPN, MSP430F5325IPN XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK 128KB 96KB 64KB 32KB 8KB+2KB 6KB+2KB 4KB+2KB Flash RAM MCLK CPUXV2 and Working Registers Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PA P2.x P3.x PB P4.x P5.x PC P6.x P7.x PD P8.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Pin Designation – MSP430F5329IPN, MSP430F5327IPN, MSP430F5325IPN 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P6.3/CB3/A3 P6.2/CB2/A2 P6.1/CB1/A1 P6.0/CB0/A0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK P5.3/XT2OUT P5.2/XT2IN AVSS2 NC LDOO LDOI PU.1 NC PU.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Functional Block Diagram – MSP430F5328IRGC, MSP430F5326IRGC, MSP430F5324IRGC, MSP430F5328IZQE, MSP430F5326IZQE, MSP430F5324IZQE XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK 128KB 96KB 64KB 32KB 8KB+2KB 6KB+2KB 4KB+2KB MCLK Flash CPUXV2 and Working Registers RAM Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PA P2.x P3.x PB P4.x P5.x PC P6.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Pin Designation – MSP430F5328IRGC, MSP430F5326IRGC, MSP430F5324IRGC RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK P5.3/XT2OUT P5.2/XT2IN AVSS2 NC LDOO LDOI PU.1 NC PU.0 VSSU RGC PACKAGE (TOP VIEW) P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6 P6.7/CB7/A7 P5.0/A8/VREF+/VeREF+ P5.
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MSP430F532x www.ti.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 3. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PN RGC ZQE P6.4/CB4/A4 1 5 C1 I/O General-purpose digital I/O Comparator_B input CB4 Analog input A4 – ADC P6.5/CB5/A5 2 6 D2 I/O General-purpose digital I/O Comparator_B input CB5 Analog input A5 – ADC P6.6/CB6/A6 3 7 D1 I/O General-purpose digital I/O Comparator_B input CB6 Analog input A6 – ADC P6.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PN RGC ZQE 20 17 J2 P1.0/TA0CLK/ACLK 21 18 H2 I/O General-purpose digital I/O with port interrupt TA0 clock signal TA0CLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) P1.1/TA0.0 22 19 H3 I/O General-purpose digital I/O with port interrupt TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output P1.2/TA0.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PN RGC ZQE P3.0/UCB0SIMO/ UCB0SDA 37 34 H8 I/O General-purpose digital I/O Slave in, master out – USCI_B0 SPI mode I2C data – USCI_B0 I2C mode P3.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 3. Terminal Functions (continued) TERMINAL NAME P4.4/PM_UCA1TXD/ PM_UCA1SIMO NO. PN 51 RGC 45 I/O (1) DESCRIPTION I/O General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Transmit data – USCI_A1 UART mode Default mapping: Slave in, master out – USCI_A1 SPI mode ZQE D7 P4.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PN RGC ZQE TEST/SBWTCK (3) 71 59 A4 I PJ.0/TDO (4) 72 60 C5 I/O General-purpose digital I/O JTAG test data output port PJ.1/TDI/TCLK (4) 73 61 C4 I/O General-purpose digital I/O JTAG test data input or test clock input PJ.2/TMS (4) 74 62 A3 I/O General-purpose digital I/O JTAG test mode select PJ.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 SHORT-FORM DESCRIPTION CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Operating Modes The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 4. Interrupt Sources, Flags, and Vectors (continued) (5) INTERRUPT SOURCE INTERRUPT FLAG Reserved Reserved (5) SYSTEM INTERRUPT WORD ADDRESS PRIORITY 0FFD0h 40 ⋮ ⋮ 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, it is recommended to reserve these locations.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as shown in Table 6. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port Mapping Controller (Link to User's Guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4. Table 9.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 10. Default Mapping PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI) P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 SPI slave in master out (direction controlled by USCI) USCI_B1 I2C data (open drain and direction controlled by USCI) P4.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Watchdog Timer (WDT_A) (Link to User's Guide) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 TA2 (Link to User's Guide) TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC12_A (Link to User's Guide) The ADC12_A module supports fast, 12-bit analog-to-digital conversions.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Peripheral File Map Table 17.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 18. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 19.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 25.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 28.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 30.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 33.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 35.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 37.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 39.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 41.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 44.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 45. Comparator_B Registers (Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B control register 0 CBCTL0 00h Comp_B control register 1 CBCTL1 02h Comp_B control register 2 CBCTL2 04h Comp_B control register 3 CBCTL3 06h Comp_B interrupt register CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh Table 46.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE, LDOI) (2) –0.3 V to VCC + 0.3 V Diode current at any device pin Storage temperature range, Tstg (1) (2) (3) ±2 mA (3) –55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Recommended Operating Conditions Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN Supply voltage during program execution and flash programming(AVCCx = DVCCx = VCC) (1) (2) VCC NOM MAX UNIT PMMCOREVx = 0 1.8 3.6 V PMMCOREVx = 0, 1 2.0 3.6 V PMMCOREVx = 0, 1, 2 2.2 3.6 V PMMCOREVx = 0, 1, 2, 3 2.4 3.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) 42 Flash RAM EXECUTION MEMORY Flash RAM VCC 3V 3V PMMCOREVx 1 MHz 8 MHz 12 MHz TYP MAX 2.65 4.0 4.4 2.90 20 MHz TYP MAX TYP MAX 0 0.36 0.47 2.32 2.60 1 0.40 2 0.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) ILPM4 0 73 77 85 80 85 97 3V 3 79 83 92 88 95 105 2.2 V 0 6.5 6.5 12 10 11 17 3V 3 7.0 7.0 13 11 12 18 0 1.60 1.90 2.6 5.6 1 1.65 2.00 2.7 5.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Schmitt-Trigger Inputs – General Purpose I/O (1) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Outputs – General Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS I(OHmax) = –1 mA (2) VOH High-level output voltage 1.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.y IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 25.0 TA = 25°C 20.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C 0.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C IDVCC.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Crystal Oscillator, XT2 (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2) PARAMETER fFault,HF (7) (8) Oscillator fault frequency TEST CONDITIONS (7) XT2BYPASS = 1 VCC (8) MIN TYP 30 MAX UNIT 300 kHz Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency (1, 0) (1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s V(DVCC_BOR_hys) BORH hysteresis tRESET Pulse length required at RST/NMI pin to accept a reset MIN TYP 0.80 1.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.6 V I(SVSH) V(SVSH_IT–) V(SVSH_IT+) tpd(SVSH) t(SVSH) dVDVCC/dt (1) SVS current consumption SVSH on voltage level (1) SVSH off voltage level (1) SVSH propagation delay SVSH on or off delay time TYP MAX 0 UNIT nA SVSHE = 1, DVCC = 3.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMHE = 0, DVCC = 3.6 V I(SVMH) SVMH current consumption V(SVMH) SVMH on or off voltage level (1) 0 t(SVMH) (1) SVMH propagation delay SVMH on or off delay time UNIT nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200 nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Wake-Up From Low Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLK ≥ 4.0 MHz 3.5 7.5 1.0 MHz < fMCLK < 4.0 MHz 4.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 11. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 12.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 13. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 14.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI Integral linearity error (1) ED Differential linearity error (1) EO Offset error (3) EG Gain error (3) ET (1) (2) (3) TEST CONDITIONS 1.4 V ≤ dVREF ≤ 1.6 V (2) 1.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 1.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VREF+ AVCC(min) IREF+ Positive built-in reference voltage output AVCC minimum voltage, Positive built-in reference active Operating supply current into AVCC terminal (2) (3) TEST CONDITIONS VCC MIN REFVSEL = {2} for 2.5 V, REFON = REFOUT = 1, IVREF+= 0 A 3V 2.4625 2.50 2.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Comparator B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 3.6 1.8 V IAVCC_COMP Comparator operating supply current into AVCC. Excludes reference resistor ladder.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 90 VCC = 3.0 V TA = 25 ºC IOL - Typical Low-Level Output Current - mA 80 VCC = 3.0 V TA = 85 ºC VCC = 1.8 V TA = 25 ºC 70 60 50 VCC = 1.8 V TA = 85 ºC 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VOL - Low-Level Output Voltage - V Figure 17. Ports PU.0, PU.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs tSBW, Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 From module 1 P1OUT.x 0 From module 1 0 DVCC 1 1 Direction 0: Input 1: Output P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN To module DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 47. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1DIR.x P1SEL.x P1.0 (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 0 1 P1.1 (I/O) P1.2 (I/O) P1.3 (I/O) P1.4 (I/O) TA0.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 From module 1 P2OUT.x 0 From module 1 0 DVCC 1 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To module DVSS P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UB0STE/UCA0CLK D P2IE.x EN To module Q P2IFG.x P2SEL.x P2IES.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 48. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 x 0 1 2 3 4 FUNCTION P2.0 (I/O) 0 0 1 TA1.1 1 1 I: 0; O: 1 0 TA1.CCI2A 0 1 TA1.2 1 1 P2.2 (I/O) I: 0; O: 1 0 TA2CLK 0 1 SMCLK 1 1 I: 0; O: 1 0 TA2.CCI0A 0 1 TA2.0 1 1 I: 0; O: 1 0 0 1 P2.1 (I/O) P2.3 (I/O) P2.4 (I/O) P2.5 (I/O) TA2.CCI2A TA2.2 P2.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 From module 1 P3OUT.x 0 From module 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN To module 1 P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI P3.5/TB0.5 P3.6/TB0.6 P3.7/TB0OUTH/SVMOUT D Table 49. Port P3 (P3.0 to P3.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 from Port Mapping Control 1 P4OUT.x 0 from Port Mapping Control 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.7/P4MAP7 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN D to Port Mapping Control Table 50. Port P4 (P4.0 to P4.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic to/from Reference to ADC12 INCHx = x P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 From module 1 P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN To module D Table 51. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VREF+/VeREF+ P5.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 52. Port P5 (P5.2, P5.3) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.3/XT2OUT (1) (2) (3) 78 x 2 3 FUNCTION P5.2 (I/O) CONTROL BITS/SIGNALS (1) P5DIR.x P5SEL.2 P5SEL.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger Pad Logic to XT1 P5REN.4 P5DIR.4 DVSS 0 DVCC 1 1 0 1 P5OUT.4 0 Module X OUT 1 P5DS.4 0: Low drive 1: High drive P5SEL.4 P5.4/XIN P5IN.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Pad Logic to XT1 P5REN.5 P5DIR.5 DVSS 0 DVCC 1 1 0 1 P5OUT.5 0 Module X OUT 1 P5.5/XOUT P5DS.5 0: Low drive 1: High drive P5SEL.5 XT1BYPASS P5IN.5 Bus Keeper EN Module X IN D Table 53. Port P5 (P5.4 and P5.5) Pin Functions PIN NAME (P5.x) P5.4/XIN x 4 FUNCTION P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS I: 0; O: 1 0 X X X 1 X 0 X 1 X 1 I: 0; O: 1 0 X X XOUT crystal mode (3) X 1 X 0 P5.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 From Module 1 P5OUT.x 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5DS.x 0: Low drive 1: High drive P5SEL.x P5.6/TB0.0 P5.7/TB0.1 P5IN.x EN D To module Table 54. Port P5 (P5.6 to P5.7) Pin Functions PIN NAME (P5.x) P5.6/TB0.0 P5.7/TB0.1 (1) (1) (1) x 6 7 FUNCTION P5.6 (I/O) CONTROL BITS/SIGNALS P5DIR.x P5SEL.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic to ADC12 INCHx = x to Comparator_B from Comparator_B CBPD.x P6REN.x P6DIR.x 0 0 From module 1 0 DVCC 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN To module 82 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS D Submit Documentation Feedback Bus Keeper P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6 P6.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 55. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/CB0/(A0) x 0 FUNCTION P6.0 (I/O) A0 CB0 (1) P6.1/CB1/(A1) P6.2/CB2/(A2) P6.3/CB3/(A3) P6.4/CB4/(A4) 1 2 3 4 P6.1 (I/O) (1) X X X 1 I: 0; O: 1 0 0 1 X 1 I: 0; O: 1 0 0 P6.2 (I/O) A2 X 1 X CB2 (1) X X 1 I: 0; O: 1 0 0 P6.3 (I/O) A3 X 1 X CB3 (1) X X 1 I: 0; O: 1 0 0 X 1 X 1 P6.4 (I/O) P6.5 (I/O) P6.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger Pad Logic to ADC12 INCHx = x to Comparator_B from Comparator_B CBPD.x P7REN.x P7DIR.x 0 0 From module 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P7OUT.x DVSS P7DS.x 0: Low drive 1: High drive P7SEL.x P7.0/CB8/A12 P7.1/CB9/A13 P7.2/CB10/A14 P7.3/CB11/A15 P7IN.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 56. Port P7 (P7.0 to P7.3) Pin Functions PIN NAME (P7.x) P7.0/CB8/(A12) x 0 FUNCTION P7.0 (I/O) A12 (2) CB8 (3) P7.1/CB9/(A13) 1 0 1 X 1 0 0 (2) X 1 X X X 1 I: 0; O: 1 0 0 X 1 X X X 1 I: 0; O: 1 0 0 X 1 X X X 1 (1) P7.2 (I/O) (1) (2) (1) P7.3 (I/O) (1) A15 (2) CB11 (3) (1) (2) (3) 0 X X CB10 (3) 3 I: 0; O: 1 X A14 P7.3/CB11/(A15) CBPD I: 0; O: 1 CB9 (3) 2 (1) P7SEL.x P7.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic P7REN.x P7DIR.x 0 From module 1 P7OUT.x 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P7DS.x 0: Low drive 1: High drive P7SEL.x P7.4/TB0.2 P7.5/TB0.3 P7.6/TB0.4 P7.7/TB0CLK/MCLK P7IN.x EN To module D Table 57. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/TB0.2 P7.5/TB0.3 (1) (1) P7.6/TB0.4 (1) P7.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger Pad Logic P8REN.x P8DIR.x 0 from Port Mapping Control 1 P8OUT.x 0 from Port Mapping Control 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P8.0 P8.1 P8.2 P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.x EN D to Port Mapping Control Table 58. Port P8 (P8.0 to P8.2) Pin Functions PIN NAME (P8.x) x FUNCTION CONTROL BITS/SIGNALS P8DIR.x P8SEL.x P8.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Port PU.0, PU.1 Ports LDOO VSSU Pad Logic PUOPE PU.0 PUOUT0 PUIN0 PUIPE PUIN1 PU.1 PUOUT1 Table 59. Port PU.0, PU.1 Output Functions (1) CONTROL BITS (1) PIN NAME PUOPE PUOUT1 PUOUT0 PU.1/DM PU.0/DP 0 X X Output disabled Output disabled 1 0 0 Output low Output low 1 0 1 Output low Output high 1 1 0 Output high Output low 1 1 1 Output high Output high PU.1 and PU.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 DVSS 0 DVCC 1 1 PJDS.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 61. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) 90 X I: 0; O: 1 (4) PJ.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 DEVICE DESCRIPTORS Table 62 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 62.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Table 62.
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MSP430F532x www.ti.com SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 Table 62.
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MSP430F532x SLAS678D – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY REVISION SLAS678 94 DESCRIPTION Product Preview release SLAS678A Updated Product Preview release SLAS678B Production Data release SLAS678C Added Device Descriptors. SLAS678D Table 3, Changed ACLK description (added dividers up to 32). Table 9, Corrected typo in PM_ANALOG note. Table 11, Changed SYSRSTIV interrupt event at 1Ch to Reserved.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 14-Jan-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.