MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Mixed Signal Microcontroller Check for Samples: MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 FEATURES 1 • • 23 • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultralow-Power Consumption – Active Mode (AM): All System Clocks Active: 270 µA/MHz at 8 MHz, 3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com DESCRIPTION The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Functional Block Diagram, MSP430F5338, MSP430F5336 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK Power Management 256KB 128KB 18KB RAM Flash +8B Backup RAM SYS Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller PA P2.x P3.x PB P4.x P5.x PC P6.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F5338 MSP430F5336 PZ PACKAGE (TOP VIEW) P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P8.7 P8.6/UCB1SOMI/UCB1SCL P8.5/UCB1SIMO/UCB1SDA DVCC2 DVSS2 P8.4/UCB1CLK/UCA1STE P8.3/UCA1RXD/UCA1SOMI P8.2/UCA1TXD/UCA1SIMO P8.1/UCB1STE/UCA1CLK P8.0/TB0CLK P4.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F5335 MSP430F5333 PZ PACKAGE (TOP VIEW) P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P8.7 P8.6/UCB1SOMI/UCB1SCL P8.5/UCB1SIMO/UCB1SDA DVCC2 DVSS2 P8.4/UCB1CLK/UCA1STE P8.3/UCA1RXD/UCA1SOMI P8.2/UCA1TXD/UCA1SIMO P8.1/UCB1STE/UCA1CLK P8.0/TB0CLK P4.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P6.4/CB4/A4 1 A1 I/O General-purpose digital I/O Comparator_B input CB4 Analog input A4 – ADC P6.5/CB5/A5 2 B2 I/O General-purpose digital I/O Comparator_B input CB5 Analog input A5 – ADC I/O General-purpose digital I/O Comparator_B input CB6 Analog input A6 – ADC DAC12.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW P2.1/P2MAP1 18 H2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data P2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL I/O (1) NO. NAME DESCRIPTION PZ ZQW P1.7/TA0.2 41 M7 I/O General-purpose digital I/O with port interrupt Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output P3.0/TA1CLK/CBOUT 42 L7 I/O General-purpose digital I/O with port interrupt Timer TA1 clock input Comparator_B output P3.1/TA1.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL I/O (1) NO. NAME DESCRIPTION PZ ZQW P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O General-purpose digital I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in P8.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ ZQW PJ.0/TDO 92 B5 I/O General-purpose digital I/O Test data output port PJ.1/TDI/TCLK 93 A4 I/O General-purpose digital I/O Test data input or test clock input PJ.2/TMS 94 E7 I/O General-purpose digital I/O Test mode select PJ.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 TI-RTOS TI-RTOS is a complete real-time operating system for the MSP430 microcontrollers. It combines a real-time multitasking kernel SYS/BIOS with additional middleware components. TI-RTOS is available free of charge and provided with full source code.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Operating Modes The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 5.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 5. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations (continued) (5) INTERRUPT SOURCE INTERRUPT FLAG Reserved Reserved (5) SYSTEM INTERRUPT WORD ADDRESS PRIORITY 0FFC8h 36 ⋮ ⋮ 0FF80h 0, lowest Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. Use of the BSL requires external access to the six pins shown in Table 7. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 9. Spy-Bi-Wire Pin Requirements and Functions (continued) DEVICE SIGNAL DIRECTION VSS FUNCTION Ground supply Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 10. Port Mapping, Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION PM_CBOUT - Comparator_B output 1 PM_TB0CLK Timer TB0 clock input - PM_ADC12CLK - ADC12CLK PM_DMAE0 DMAE0 Input - PM_SVMOUT - SVM output PM_TB0OUTH Timer TB0 high impedance input TB0OUTH - 4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 11. Default Mapping (continued) PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P2.6/P2MAP6 PM_NONE - DVSS P2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors).
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F533x series includes two complete USCI modules (n = 0 to 1). Timer TA0 (Link to User's Guide) Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Timer TA1 (Link to User's Guide) Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Timer TA2 (Link to User's Guide) Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Timer TB0 (Link to User's Guide) Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 17.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Comparator_B (Link to User's Guide) The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC12_A (Link to User's Guide) The ADC12_A module supports fast 12-bit analog-to-digital conversions.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Peripheral File Map Table 18.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 19. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 20.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 26.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 29. Port P1/P2 Registers (Base Address: 0200h) (continued) REGISTER DESCRIPTION REGISTER OFFSET Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 30.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 32.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 36.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 39. Battery Backup Registers (Base Address: 0480h) REGISTER DESCRIPTION REGISTER OFFSET Battery Backup Memory 0 BAKMEM0 00h Battery Backup Memory 1 BAKMEM1 02h Battery Backup Memory 2 BAKMEM2 04h Battery Backup Memory 3 BAKMEM3 06h Battery Backup Control BAKCTL 1Ch Battery Charger Control BAKCHCTL 1Eh Table 40.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 41.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 42.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 45.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 47.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 50.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS Voltage applied to any pin (excluding VCORE, VBUS, V18) –0.3 V to 4.1 V (2) –0.3 V to VCC + 0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 25 System Frequency - MHz 20 3 16 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER EXECUTION MEMORY VCC PMMCOREVx 1 MHz TYP IAM, IAM, (1) (2) (3) 44 Flash RAM Flash RAM 3V 3V 8 MHz MAX 0.36 TYP 2.1 12 MHz MAX TYP 0 0.32 1 0.36 2.4 3.6 2 0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER ILPM0,1MHz Low-power mode 0 (3) (4) ILPM2 Low-power mode 2 (5) (4) VLO,WDT ILPM4 ILPM3.5, RTC,VCC ILPM3.5, RTC,VBAT ILPM3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER ILPM4.5 VCC Low-power mode 4.5 (LPM4.5) (12) PMMCOREVx -40°C TYP 3V MAX 0.2 25°C TYP 60°C MAX 0.3 TYP 0.6 85°C MAX TYP 0.7 0.9 MAX UNIT 1.4 µA (12) Internal regulator disabled.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Outputs – General Purpose I/O (Full Drive Strength) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OLmax) = 3 mA VOL 1.8 V I(OLmax) = 10 mA (2) Low-level output voltage VCC (1) I(OLmax) = 5 mA (1) 3V I(OLmax) = 15 mA (2) MIN MAX VSS VSS + 0.25 VSS VSS + 0.60 VSS VSS + 0.25 VSS VSS + 0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V P3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 55.0 VCC = 3.0 V P3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V Measured at ACLK (2) 1.8 V to 3.6 V Measured at ACLK 1.8 V to 3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 PMM, SVS High Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tpd(SVSH) SVSH propagation delay t(SVSH) SVSH on/off delay time dVDVCC/dt DVCC rise time MIN TYP SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 SVSHE = 0→1, SVSHFP = 1 12.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com PMM, SVM Low Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tpd(SVML) SVML propagation delay t(SVML) SVML on/off delay time TEST CONDITIONS MIN TYP SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0→1, SVMLFP = 1 12.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Battery Backup over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VBAT = 1.7 V, DVCC not connected, RTC running IVBAT Current into VBAT terminal in VBAT = 2.2 V, case no primary battery is DVCC not connected, connected. RTC running VBAT = 3 V, DVCC not connected, RTC running VCC MIN TYP TA = -40°C 0.43 TA = 25°C 0.52 TA = 60°C 0.58 TA = 85°C 0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 13.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 14. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 15.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EO Offset error See (2) 2.2 V, 3 V ±1 ±2 LSB EG Gain error (3) See (2) 2.2 V, 3 V ±2 ±4 LSB ET Total unadjusted error See (2) 2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Typical Temperature Sensor Voltage - mV 1000 950 900 850 800 750 700 650 600 550 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature - ˚C Figure 17.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = REFOUT = 1 , IVREF+ = 0 A REFVSEL = {1} for 2 V, Positive built-in reference REFON = REFOUT = 1, voltage output IVREF+ = 0 A VREF+ REFVSEL = {0} for 1.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 12-Bit DAC, Output Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN No load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 No load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 Output voltage range (1) (see Figure 19) VO TYP 0 0.005 AVCC – 0.05 AVCC 2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com 12-Bit DAC, Reference Input Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS DAC12IR = 0 (1) Reference input voltage range VeREF+ VCC (2) 2.2 V, 3 V DAC12IR = 1 (3) (4) DAC12_0 IR = DAC12_1 IR = 0 Ri(VREF+), Ri(VeREF+) MIN (6) AVCC /3 AVCC + 0.2 AVCC AVCC + 0.2 UNIT V MΩ 48 2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRHL tSRLH Figure 21. Slew Rate Testing 12-Bit DAC, Dynamic Specifications (Continued) over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted) PARAMETER BW–3dB TEST CONDITIONS 3-dB bandwidth, VDC = 1.5 V, VAC = 0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS VCC Supply voltage MIN TYP 1.8 3.6 1.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Ports PU.0 and PU.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VLDOO = 3.3 V ± 10%, IOH = -25 mA, See Figure 25 for typical characteristics VOL Low-level output voltage VLDOO = 3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 90 VCC = 3.0 V TA = 25 ºC IOL - Typical Low-Level Output Current - mA 80 VCC = 3.0 V TA = 85 ºC VCC = 1.8 V TA = 25 ºC 70 60 50 VCC = 1.8 V TA = 85 ºC 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VOL - Low-Level Output Voltage - V Figure 24. Ports PU.0, PU.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 LDO-PWR (LDO Power System) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 3.75 V 5.5 V ±9% V 1.8 3.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com JTAG and Spy-Bi-Wire Interface (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTCK TCK input frequency (4-wire JTAG) (2) Rinternal Internal pulldown resistance on TEST (2) 76 TEST CONDITIONS MIN TYP MAX UNIT 2.2 V 0 5 MHz 3V 0 10 MHz 2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P1DIR.x P1OUT.x 0 Module X OUT 1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN Module X IN P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA0.1 P1.7/TA0.2 D P1IE.x EN P1IRQ.x Q P1IFG.x P1SEL.x P1IES.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 51. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1.0 (I/O) 0 0 1 ACLK 1 1 I: 0; O: 1 0 Timer TA0.CCI0A capture input 0 1 Timer TA0.0 output 1 1 I: 0; O: 1 0 Timer TA0.CCI1A capture input 0 1 Timer TA0.1 output 1 1 I: 0; O: 1 0 Timer TA0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 From Port Mapping 1 P2OUT.x 0 From Port Mapping 1 DVSS 0 DVCC 1 Direction 0: Input 1: Output P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN To Port Mapping 1 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7 D P2IE.x EN P2IRQ.x Q P2IFG.x P2SEL.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 52. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/P2MAP0 x 0 FUNCTION P2.0 (I/O) Mapped secondary digital function P2.1/P2MAP1 1 P2.1 (I/O) Mapped secondary digital function P2.2/P2MAP2 2 P2.2 (I/O) Mapped secondary digital function P2.3/P2MAP3 3 P2.4/P2MAP4 4 P2.3 (I/O) Mapped secondary digital function P2.4 (I/O) Mapped secondary digital function P2.5/P2MAP5 5 P2.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P3DIR.x P3OUT.x 0 Module X OUT 1 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN Module X IN P3.0/TA1CLK/CBOUT P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA2CLK/SMCLK P3.5/TA2.0 P3.6/TA2.1 P3.7/TA2.2 D P3IE.x EN P3IRQ.x Q P3IFG.x P3SEL.x P3IES.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 53. Port P3 (P3.0 to P3.7) Pin Functions PIN NAME (P3.x) P3.0/TA1CLK/CBOUT P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA2CLK/SMCLK x 0 1 2 3 4 FUNCTION P3.0 (I/O) CONTROL BITS/SIGNALS P3DIR.x P3SEL.x I: 0; O: 1 0 Timer TA1.TA1CLK 0 1 CBOUT 1 1 I: 0; O: 1 0 Timer TA1.CCI0A capture input 0 1 Timer TA1.0 output 1 1 I: 0; O: 1 0 Timer TA1.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P4DIR.x P4OUT.x 0 Module X OUT 1 P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.7/TB0OUTH/SVMOUT P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN Module X IN D P4IE.x EN P4IRQ.x Q P4IFG.x P4SEL.x P4IES.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 54. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 x 0 1 2 3 4 FUNCTION P4.0 (I/O) CONTROL BITS/SIGNALS P4DIR.x P4SEL.x I: 0; O: 1 0 Timer TB0.CCI0A capture input 0 1 Timer TB0.0 output (1) 1 1 I: 0; O: 1 0 Timer TB0.CCI1A capture input 0 1 Timer TB0.1 output (1) 1 1 I: 0; O: 1 0 Timer TB0.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic To/From Reference P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 Module X OUT 1 P5.0/VREF+/VeREF+ P5.1/VREF–/VeREF– P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x Bus Keeper EN Module X IN D Table 55. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/VREF+/VeREF+ x 0 FUNCTION P5DIR.x P5SEL.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P5DIR.x P5OUT.x 0 Module X OUT 1 P5.2 P5.3 P5.4 P5.5 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x EN Module X IN D Table 56. Port P5 (P5.2 to P5.7) Pin Functions PIN NAME (P5.x) x FUNCTION CONTROL BITS/SIGNALS P5DIR.x P5SEL.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y 0 Dvss 1 From DAC12_A 2 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P6REN.x DVSS 0 DVCC 1 1 P6DIR.x P6OUT.x P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x Bus Keeper Copyright © 2010–2013, Texas Instruments Incorporated P6.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 57. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/CB0/A0 x 0 FUNCTION P6.0 (I/O) CB0 A0 (2) P6.1/CB1/A1 1 (3) P6.1 (I/O) CB1 A1 (2) P6.2/CB2/A2 2 (3) P6.2 (I/O) CB2 A2 (2) P6.3/CB3/A3 3 (3) P6.3 (I/O) CB3 A3 (2) P6.4/CB4/A4 4 (3) P6.4 (I/O) CB4 A4 P6.5/CB5/A5 5 (2) (3) P6.5 (I/O) CB5 A5 P6.6/CB6/A6/DAC0 6 (4) (2) (3) P6.6 (I/O) CB6 A6 (2) (3) DAC0 P6.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P7, P7.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P7REN.2 P7DIR.2 DVSS 0 DVCC 1 1 0 1 P7OUT.2 P7DS.2 0: Low drive 1: High drive P7SEL.2 P7.2/XT2IN P7IN.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Port P7, P7.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P7REN.3 P7DIR.3 DVSS 0 DVCC 1 1 0 1 P7OUT.3 P7.3/XT2OUT P7DS.3 0: Low drive 1: High drive P7SEL.3 P7IN.3 Bus Keeper Table 58. Port P7 (P7.2 and P7.3) Pin Functions PIN NAME (P5.x) P7.2/XT2IN P7.3/XT2OUT (1) (2) (3) 90 x 2 3 FUNCTION P7.2 (I/O) CONTROL BITS/SIGNALS (1) P7DIR.x P7SEL.2 P7SEL.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger 0 Dvss 1 From DAC12_A 2 Pad Logic 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 To ADC12 INCHx = y To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P7REN.x DVSS 0 DVCC 1 1 P7DIR.x P7OUT.x P7DS.x 0: Low drive 1: High drive P7SEL.x P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1 P7IN.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Table 59. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 x 4 5 6 FUNCTION P7.4 (I/O) 7 (3) 92 P7SEL.x CBPD.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic P8REN.x P8DIR.x 0 From module 1 P8OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P8.0/TB0CLK P8.1/UCB1STE/UCA1CLK P8.2/UCA1TXD/UCA1SIMO P8.3/UCA1RXD/UCA1SOMI P8.4/UCB1CLK/UCA1STE P8.5/UCB1SIMO//UCB1SDA P8.6/UCB1SOMI/UCB1SCL P8.7 P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic P9REN.x DVSS 0 DVCC 1 1 Direction 0: Input 1: Output P9DIR.x P9OUT.x P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7 P9DS.x 0: Low drive 1: High drive P9IN.x Table 61. Port P9 (P9.0 to P9.7) Pin Functions PIN NAME (P9.x) x FUNCTION CONTROL BITS/SIGNALS P9DIR.x P9SEL.x P9.0 0 P9.0 (I/O) I: 0; O: 1 0 P9.1 1 P9.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Port PU.0, PU.1 Ports LDOO VSSU Pad Logic PUOPE PU.0 PUOUT0 PUIN0 PUIPE PUIN1 PU.1 PUOUT1 Table 62. Port PU.0, PU.1 Output Functions CONTROL BITS PIN NAME FUNCTION PUSEL PUDIR PUOUT1 PUOUT0 PU.1 PU.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 Table 63. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) X I: 0; O: 1 (4) PJ.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 www.ti.com DEVICE DESCRIPTORS Table 64 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 64.
MSP430F5338, MSP430F5336 MSP430F5335, MSP430F5333 www.ti.com SLAS721C – AUGUST 2010 – REVISED AUGUST 2013 REVISION HISTORY REVISION COMMENTS SLAS721 Product Preview release SLAS721A Production Data release SLAS721B Changed description of ACLK in Terminal Functions. Added missing rows for DVSS and DNC (PW pins 29 and 30) in Terminal Functions. Changed typos to Interrupt Flag names on Timer TA2 rows in Table 5. Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 12.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.