MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Mixed Signal Microcontroller Check for Samples: MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A, MSP430F5419A, MSP430F5418A FEATURES 1 • 23 • • • • • Low Supply Voltage Range: 3.6 V Down to 1.8 V Ultralow-Power Consumption – Active Mode (AM): All System Clocks Active 230 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical) 110 µA/MHz at 8 MHz, 3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com APPLICATIONS • • • • • • Analog and Digital Sensor Systems Digital Motor Control Remote Controls Thermostats Digital Timers Hand-Held Meters DESCRIPTION The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Functional Block Diagram MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW DVCC DVSS XIN XOUT AVCC AVSS PA P2.x RST/NMI P1.x XT2IN XT2OUT Unified Clock System ACLK 256KB 192KB 128KB SMCLK Flash MCLK CPUXV2 and Working Registers 16KB RAM Power Management SYS LDO SVM/SVS Brownout Watchdog PB P4.x P3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Pin Designation, MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F5438AIPZ MSP430F5436AIPZ MSP430F5419AIPZ P9.7 P9.6 P9.5/UCA2RXDUCA2SOMI P9.4/UCA2TXD/UCA2SIMO P9.3/UCB2CLK/UCA2STE P9.2/UCB2SOMI/UCB2SCL P9.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Pin Designation, MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN P6.3/A3 P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCLK P5.3/XT2OUT P5.2/XT2IN DVSS4 DVCC4 P8.6/TA1.1 P8.5/TA1.0 P8.4/TA0.4 P8.3/TA0.3 P8.2/TA0.2 P8.1/TA0.1 PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P6.4/A4 P6.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Pin Designation, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW ZQW PACKAGE (TOP VIEW) 6 P6.4 P6.2 RST PJ.1 P5.3 P5.2 P11.2 P11.0 P10.6 P10.4 P10.1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P6.6 P6.3 P6.1 PJ.3 PJ.0 P10.5 P10.3 P9.6 P9.5 B1 B2 B3 B4 B5 B9 B10 P7.5 P6.7 C1 C2 P5.0 P7.6 DVSS4 DVCC4 P10.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN ZQW P6.4/A4 1 1 A1 I/O General-purpose digital I/O Analog input A4 – ADC P6.5/A5 2 2 E4 I/O General-purpose digital I/O Analog input A5 – ADC P6.6/A6 3 3 B1 I/O General-purpose digital I/O Analog input A6 – ADC P6.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN ZQW P2.1/TA1.0 26 26 L2 I/O General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output P2.2/TA1.1 27 27 M2 I/O General-purpose digital I/O with port interrupt TA1 CCR1 capture: CCI1A input, compare: Out1 output P2.3/TA1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN ZQW P4.6/TB0.6 49 52 M11 I/O General-purpose digital I/O TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output P4.7/TB0CLK/SMCLK 50 53 M12 I/O General-purpose digital I/O TB0 clock input SMCLK output P5.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN ZQW P9.3/UCB2CLK/UCA2STE 71 N/A E9 I/O General-purpose digital I/O Clock signal input – USCI_B2 SPI slave mode Clock signal output – USCI_B2 SPI master mode Slave transmit enable – USCI_A2 SPI mode P9.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN ZQW (4) 94 74 D5 I/O General-purpose digital I/O JTAG test mode select PJ.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 SYS/BIOS SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time analysis. SYS/BIOS is available free of charge and is provided with full source code.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Short-Form Description CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as shown in Table 4. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors).
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 11.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com ADC12_A (Link to User's Guide) The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Peripheral File Map Table 12.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 13. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 14.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 20.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 23.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 26.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 29.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 31.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 33.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 34.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 36.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 38.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 41.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 43.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE) (2) –0.3 V to VCC + 0.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 25 System Frequency - MHz 3 20 2 2, 3 1 1, 2 1, 2, 3 0, 1 0, 1, 2 0, 1, 2, 3 12 8 0 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) FREQUENCY (fDCO = fMCLK = fSMCLK) PARAMETER IAM, IAM, (1) (2) (3) 42 Flash RAM EXECUTION MEMORY Flash RAM VCC 3.0 V 3.0 V PMMCOREVx 1 MHz 8 MHz 12 MHz TYP MAX TYP MAX 0 0.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER ILPM0,1MHz ILPM2 Low-power mode 0 (3) (4) Low-power mode 2 (5) (4) ILPM4 0 69 93 69 93 69 93 69 93 3 73 100 73 100 73 100 73 100 2.2 V 0 11 15.5 11 15.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA VOH I(OHmax) = –10 mA (2) High-level output voltage I(OHmax) = –5 mA (1) I(OHmax) = –15 mA (2) I(OLmax) = 3 mA VOL (2) 3V MAX VCC – 0.25 VCC VCC – 0.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Crystal Oscillator, XT1, High-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IDVCC.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK, ACLK, External: TACLK, Duty cycle = 50% ± 10% 1.8 V/ 3.0 V tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V/ 3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 12. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tHD,MO tVALID,MO SIMO Figure 13.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 14. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 15.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI Integral linearity error (1) ED Differential linearity error (1) EO Offset error (3) EG Gain error (3) ET (1) (2) (3) TEST CONDITIONS 1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 DVCC 1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN Module X IN 0 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/SMCLK P1.7 D P1IE.x EN P1IRQ.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 44. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1.0 (I/O) 0 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 0 1 P1.1 (I/O) P1.2 (I/O) P1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 0 Module X OUT 1 DVCC 1 P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN Module X IN 0 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK P2.5 P2.6/ACLK P2.7/ADC12CLK/DMAE0 D P2IE.x EN P2IRQ.x Q P2IFG.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 45. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1CLK/MCLK P2.1/TA1.0 x 0 1 P2.2/TA1.1 2 P2.3/TA1.2 3 P2.4/RTCCLK 4 FUNCTION CONTROL BITS/SIGNALS P2DIR.x P2SEL.x P2.0 (I/O) I: 0; O: 1 0 TA1CLK 0 1 MCLK 1 1 I: 0; O: 1 0 TA1.CCI0A 0 1 TA1.0 1 1 I: 0; O: 1 0 TA1.CCI1A 0 1 TA1.1 1 1 I: 0; O: 1 0 TA1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 0 Module X OUT 1 0 DVCC 1 P3DS.x 0: Low drive 1: High drive P3SEL.x P3IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS P3.0/UB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/USC0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 DVCC 1 1 P4DS.x 0: Low drive 1: High drive P4SEL.x P4IN.x EN Module X IN 0 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 47. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/TB0.0 x 0 P4.1/TB0.1 1 P4.2/TB0.2 2 P4.3/TB0.3 3 P4.4/TB0.5 4 FUNCTION 4.0 (I/O) 0 0 1 TB0.0 (1) 1 1 4.1 (I/O) I: 0; O: 1 0 TB0.CCI1A and TB0.CCI1B 0 1 TB0.1 (1) 1 1 4.2 (I/O) I: 0; O: 1 0 TB0.CCI2A and TB0.CCI2B 0 1 TB0.2 (1) 1 1 4.3 (I/O) I: 0; O: 1 0 TB0.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y To/From ADC12 Reference P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 Module X OUT 1 P5DS.x 0: Low drive 1: High drive P5SEL.x P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– P5IN.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 48. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– (1) (2) (3) (4) (5) (6) 76 x 0 1 FUNCTION P5.0 (I/O) (2) CONTROL BITS/SIGNALS (1) P5DIR.x P5SEL.x REFOUT I: 0; O: 1 0 X A8/VeREF+ (3) X 1 0 A8/VREF+ (4) X 1 1 P5.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 49. Port P5 (P5.2) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.3/XT2OUT (1) (2) (3) 78 x 2 3 FUNCTION P5.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5.4/UCB1SOMI/UCB1SCL P5.5/UCB1CLK/UCA1STE P5.6/UCA1TXD/UCA1SIMO P5.7/UCA1RXD/UCA1SOMI P5DS.x 0: Low drive 1: High drive P5SEL.x P5IN.x EN Module X IN D Table 50. Port P5 (P5.4 to P5.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P6REN.x P6DIR.x DVSS 0 DVCC 1 1 0 1 P6OUT.x 0 Module X OUT 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN Module X IN 80 Bus Keeper P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 51. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/A0 x 0 FUNCTION P6.0 (I/O) A0 (2) P6.1/A1 1 P6.1 (I/O) A1 (2) P6.2/A2 2 3 4 5 6 7 (3) (3) P6.7 (I/O) A7 (2) (1) (2) (2) (3) P6.6 (I/O) A6 (2) P6.7/A7 (3) P6.5 (I/O) A5 (1) P6.6/A6 (3) P6.4 (I/O) A4 (2) P6.5/A5 (3) P6.3 (I/O) A3 (2) P6.4/A4 (3) P6.2 (I/O) A2 (2) P6.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P7, P7.0, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.0 P7DIR.0 DVSS 0 DVCC 1 1 0 1 P7OUT.0 0 Module X OUT 1 P7DS.0 0: Low drive 1: High drive P7SEL.0 P7.0/XIN P7IN.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P7, P7.1, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.1 P7DIR.1 DVSS 0 DVCC 1 1 0 1 P7OUT.1 0 Module X OUT 1 P7.1/XOUT P7DS.1 0: Low drive 1: High drive P7SEL.0 XT1BYPASS P7IN.1 Bus Keeper EN Module X IN D Table 52. Port P7 (P7.0 and P7.1) Pin Functions PIN NAME (P7.x) P7.0/XIN x 0 FUNCTION P7.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger Pad Logic P7REN.x P7DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P7OUT.x DVSS P7.2/TB0OUTH/SVMOUT P7.3/TA1.2 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x EN Module X IN D Table 53. Port P7 (P7.2 and P7.3) Pin Functions PIN NAME (P7.x) P7.2/TB0OUTH/SVMOUT P7.3/TA1.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P7REN.x P7DIR.x DVSS 0 DVCC 1 1 0 1 P7OUT.x 0 Module X OUT 1 P7.4/A12 P7.5/A13 P7.6/A14 P7.7/A15 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x Bus Keeper EN D Module X IN Table 54. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/A12 x 4 FUNCTION P7.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic P8REN.x P8DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P8OUT.x DVSS P8.0/TA0.0 P8.1/TA0.1 P8.2/TA0.2 P8.3/TA0.3 P8.4/TA0.4 P8.5/TA1.0 P8.6/TA1.1 P8.7 P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.x EN D Module X IN Table 55. Port P8 (P8.0 to P8.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic P9REN.x P9DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P9OUT.x DVSS P9.0/UCB2STE/UCA2CLK P9.1/UCB2SIMO/UCB2SDA P9.2/UCB2SOMI/UCB2SCL P9.3/UCB2CLK/UCA2STE P9.4/UCA2TXD/UCA2SIMO P9.5/UCA2RXD/UCA2SOMI P9.6 P9.7 P9DS.x 0: Low drive 1: High drive P9SEL.x P9IN.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger Pad Logic P10REN.x P10DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P10OUT.x DVSS P10DS.x 0: Low drive 1: High drive P10SEL.x P10IN.x EN P10.0/UCB3STE/UCA3CLK P10.1/UCB3SIMO/UCB3SDA P10.2/UCB3SOMI/UCB3SCL P10.3/UCB3CLK/UCA3STE P10.4/UCA3TXD/UCA3SIMO P10.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger Pad Logic P11REN.x P11DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P11OUT.x DVSS P11.0/ACLK P11.1/MCLK P11.2/SMCLK P11DS.x 0: Low drive 1: High drive P11SEL.x P11IN.x EN D Module X IN Table 58. Port P11 (P11.0 to P11.2) Pin Functions PIN NAME (P11.x) P11.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 59. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) X I: 0; O: 1 (4) PJ.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com DEVICE DESCRIPTORS (TLV) Table 60 shows the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 60.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 60. Device Descriptor Table(1) (continued) Peripheral Descriptor Description Address Size bytes F5438A F5437A F5436A F5435A F5419A F5418A Value Value Value Value Value Value REF 1.5-V Reference 01A28h 2 per unit per unit per unit per unit per unit per unit REF 2.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com Table 60.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A www.ti.com SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 Table 60.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A MSP430F5419A, MSP430F5418A SLAS655D – JANUARY 2010 – REVISED AUGUST 2013 www.ti.com REVISION HISTORY 96 REVISION DESCRIPTION SLAS655 Product Preview release SLAS655A Production Data release SLAS655B Changed fXT1,HF,SW MIN from 1.5 MHz to 0.7 MHz, page 48 Changed fXT2,HF,SW MIN from 1.5 MHz to 0.7 MHz, page 49 SLAS655C Features, Changed Wake-Up From Standby Mode time to 3.5 µs. Table 2, Changed ACLK description.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com (4) 15-Jul-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F5418AIPNR Package Package Pins Type Drawing LQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 MSP430F5419AIZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430F5436AIZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F5418AIPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430F5419AIZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.6 MSP430F5436AIZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.6 MSP430F5438AIZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.
MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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