Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16-Bit 18 MHz I/O number 87

MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435

MSP430F5419, MSP430F5418

www.ti.com

SLAS612D –AUGUST 2009–REVISED AUGUST 2013

Mixed Signal Microcontroller

Check for Samples: MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435, MSP430F5419, MSP430F5418

FEATURES

• Low Supply Voltage Range: 2.2 V to 3.6 V

• 16-Bit Timer TA0, Timer_A With Five

Capture/Compare Registers

• Ultralow-Power Consumption

• 16-Bit Timer TA1, Timer_A With Three

– Active Mode (AM):

Capture/Compare Registers

All System Clocks Active

312 µA/MHz at 8 MHz, 3.0 V, Flash Program • 16-Bit Timer TB0, Timer_B With Seven

Execution (Typical) Capture/Compare Shadow Registers

140 µA/MHz at 8 MHz, 3.0 V, RAM Program

• Up to Four Universal Serial Communication

Execution (Typical)

Interfaces

– Standby Mode (LPM3):

– USCI_A0, USCI_A1, USCI_A2, and USCI_A3

Real-Time Clock With Crystal, Watchdog,

Each Support:

and Supply Supervisor Operational, Full

– Enhanced UART Supports Auto-

RAM Retention, Fast Wake-Up:

Baudrate Detection

2.6 µA at 3.0 V (Typical)

– IrDA Encoder and Decoder

Low-Power Oscillator (VLO), General-

– Synchronous SPI

Purpose Counter, Watchdog, and Supply

Supervisor Operational, Full RAM – USCI_B0, USCI_B1, USCI_B2, and USCI_B3

Retention, Fast Wake-Up: Each Support:

1.8 µA at 3.0 V (Typical)

– I

– Off Mode (LPM4):

– Synchronous SPI

Full RAM Retention, Supply Supervisor

• 12-Bit Analog-to-Digital Converter (ADC)

Operational, Fast Wake-Up:

– Internal Reference

1.69 µA at 3.0 V (Typical)

– Sample-and-Hold

• Wake Up From Standby Mode in Less Than

– Autoscan Feature

5 µs

– 14 External Channels, 2 Internal Channels

• 16-Bit RISC Architecture

• Hardware Multiplier Supporting 32-Bit

– Extended Memory

Operations

– Up to 18-MHz System Clock

• Serial Onboard Programming, No External

• Flexible Power Management System

Programming Voltage Needed

– Fully Integrated LDO With Programmable

• Three-Channel Internal DMA

Regulated Core Supply Voltage

• Basic Timer With Real-Time Clock Feature

– Supply Voltage Supervision, Monitoring,

• Family Members are Summarized in Table 1

and Brownout

• For Complete Module Descriptions, See the

• Unified Clock System

MSP430x5xx and MSP430x6xx Family User's

– FLL Control Loop for Frequency

Guide (SLAU208)

Stabilization

– Low-Power Low-Frequency Internal Clock

Source (VLO)

– Low-Frequency Trimmed Internal Reference

Source (REFO)

– 32-kHz Crystals

– High-Frequency Crystals up to 32 MHz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (103 pages)

PAGE 1
MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Mixed Signal Microcontroller Check for Samples: MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435, MSP430F5419, MSP430F5418 FEATURES 1 • • 23 • • • • Low Supply Voltage Range: 2.2 V to 3.6 V Ultralow-Power Consumption – Active Mode (AM): All System Clocks Active 312 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical) 140 µA/MHz at 8 MHz, 3.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com APPLICATIONS • • • • • • Analog and Digital Sensor Systems Digital Motor Control Remote Controls Thermostats Digital Timers Hand-Held Meters DESCRIPTION The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Functional Block Diagram, MSP430F5438IPZ, MSP430F5436IPZ, MSP430F5419IPZ DVCC DVSS XIN XOUT AVCC AVSS PA P2.x RST/NMI P1.x XT2IN XT2OUT Unified Clock System ACLK 256KB 192KB 128KB SMCLK Flash MCLK CPUXV2 and Working Registers 16KB Power Management SYS LDO SVM/SVS Brownout RAM Watchdog PB P4.x P3.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Pin Designation, MSP430F5438IPZ, MSP430F5436IPZ, MSP430F5419IPZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F5438IPZ MSP430F5436IPZ MSP430F5419IPZ P9.7 P9.6 P9.5/UCA2RXDUCA2SOMI P9.4/UCA2TXD/UCA2SIMO P9.3/UCB2CLK/UCA2STE P9.2/UCB2SOMI/UCB2SCL P9.1/UCB2SIMO/UCB2SDA P9.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Pin Designation, MSP430F5437IPN, MSP430F5435IPN, MSP430F5418IPN P6.3/A3 P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI/SBWTDIO PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCLK P5.3/XT2OUT P5.2/XT2IN DVSS4 DVCC4 P8.6/TA1.1 P8.5/TA1.0 P8.4/TA0.4 P8.3/TA0.3 P8.2/TA0.2 P8.1/TA0.1 PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P6.4/A4 P6.5/A5 P6.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN P6.4/A4 1 1 I/O General-purpose digital I/O Analog input A4 – ADC P6.5/A5 2 2 I/O General-purpose digital I/O Analog input A5 – ADC P6.6/A6 3 3 I/O General-purpose digital I/O Analog input A6 – ADC P6.7/A7 4 4 I/O General-purpose digital I/O Analog input A7 – ADC P7.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN P2.1/TA1.0 26 26 I/O General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output P2.2/TA1.1 27 27 I/O General-purpose digital I/O with port interrupt TA1 CCR1 capture: CCI1A input, compare: Out1 output P2.3/TA1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN P4.6/TB0.6 49 52 I/O General-purpose digital I/O TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output P4.7/TB0CLK/SMCLK 50 53 I/O General-purpose digital I/O TB0 clock input SMCLK output P5.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN P9.3/UCB2CLK/UCA2STE 71 N/A I/O General-purpose digital I/O Clock signal input – USCI_B2 SPI slave mode Clock signal output – USCI_B2 SPI master mode Slave transmit enable – USCI_A2 SPI mode P9.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME I/O (1) NO. DESCRIPTION PZ PN (4) 94 74 I/O General-purpose digital I/O Test mode select PJ.3/TCK (4) 95 75 I/O General-purpose digital I/O Test clock RST/NMI/SBWTDIO (3) 96 76 I/O Reset input active low Non-maskable interrupt input Spy-bi-wire data input/output P6.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com SYS/BIOS SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time analysis. SYS/BIOS is available free of charge and is provided with full source code.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as shown in Table 4. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 6.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430F6xx Family User's Guide (SLAU208). Digital I/O (Link to User's Guide) There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Real-Time Clock (RTC_A) (Link to User's Guide) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated realtime clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 System Module (SYS) (Link to User's Guide) The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors).
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com DMA Controller (Link to User's Guide) The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com TA1 (Link to User's Guide) TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 TB0 (Link to User's Guide) TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 11.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com ADC12_A (Link to User's Guide) The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Peripheral File Map Table 12.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 13. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 14.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 20.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 22.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 25.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 29.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 31.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 32.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 33.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 35.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 37.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 39.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 42.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage VCC applied at supply pins DVCC/AVCC to supply pins DVSS/AVSS Voltage applied to any pin (excluding VCORE) –0.3 V to 4.1 V (2) –0.3 V to VCC + 0.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 System Frequency - MHz 3 18 2 0 2.2 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) Frequency (fDCO = fMCLK = fSMCLK) EXECUTION MEMORY VCC PMMCOREVx Flash Flash 3.0 V 2 0.37 0.45 1.27 1.47 2.50 2.84 5.00 5.56 mA RAM RAM 3.0 V 2 0.20 0.29 0.60 0.72 1.12 1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = –3 mA VOH High-level output voltage I(OHmax) = –10 mA (2) I(OHmax) = –5 mA (1) I(OHmax) = –15 mA (2) I(OLmax) = 3 mA VOL Low-level output voltage (2) 1.8 V 3V MIN MAX VCC – 0.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 3.0 V Px.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C VCC = 3.0 V Px.y 55.0 50.0 IOL – Typical Low-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 60.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C ΔIDVCC.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Crystal Oscillator, XT1, High-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IDVCC.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.55 V 1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SVSHE = 0, DVCC = 3.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Wake-Up From Low Power Modes over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode (1) PMMCOREV = SVSMLRRL = 2, SVSLFP = 1 2.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 12. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 13.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note (1), Figure 14 and Figure 15) PARAMETER TEST CONDITIONS VCC MIN TYP MAX STE lead time, STE low to clock 2.2 V, 3 V tSTE,LAG STE lag time, Last clock to STE high 2.2 V, 3 V tSTE,ACC STE access time, STE low to SOMI data out 2.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tHD,MO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 15.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com 12-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator (1) Conversion time VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 4.8 5.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 12-Bit ADC, Temperature Sensor and Built-In VMID over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ISENSOR Operating supply current into AVCC terminal (1) VSENSOR See (2) TCSENSOR VCC MIN TYP REFON = 0, INCH = 0Ah, ADC12ON = N/A, TA = 25°C 2.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS DVCC(PGM/ERASE) Program and erase supply voltage MIN TYP 1.8 MAX 3.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 DVCC 1 1 P1DS.x 0: Low drive 1: High drive P1SEL.x P1IN.x EN Module X IN 0 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/SMCLK P1.7 D P1IE.x EN P1IRQ.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 43. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 x 0 1 2 3 4 FUNCTION P1.0 (I/O) 0 0 1 ACLK 1 1 I: 0; O: 1 0 TA0.CCI0A 0 1 TA0.0 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 TA0.CCI2A 0 1 TA0.2 1 1 I: 0; O: 1 0 0 1 P1.1 (I/O) P1.2 (I/O) P1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 0 0 Module X OUT 1 DVCC 1 P2DS.x 0: Low drive 1: High drive P2SEL.x P2IN.x EN Module X IN 0 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK P2.5 P2.6/ACLK P2.7/ADC12CLK/DMAE0 D P2IE.x EN P2IRQ.x Q P2IFG.x P2SEL.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 44. Port P2 (P2.0 to P2.7) Pin Functions PIN NAME (P2.x) P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK x 0 1 2 3 4 FUNCTION CONTROL BITS/SIGNALS P2DIR.x P2SEL.x P2.0 (I/O) I: 0; O: 1 0 TA1CLK 0 1 MCLK 1 1 I: 0; O: 1 0 TA1.CCI0A 0 1 TA1.0 1 1 I: 0; O: 1 0 TA1.CCI1A 0 1 TA1.1 1 1 I: 0; O: 1 0 TA1.CCI2A 0 1 TA1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS P3.0/UB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/USC0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCB1STE/UCA1CLK P3.7/UCB1SIMO/UCB1SDA P3DS.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 P4IN.x EN 70 DVCC 1 P4DS.x 0: Low drive 1: High drive P4SEL.x Module X IN 0 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 46. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.5 x 0 1 2 3 4 FUNCTION 4.0 (I/O) 0 0 1 TB0.0 (1) 1 1 4.1 (I/O) I: 0; O: 1 0 TB0.CCI1A and TB0.CCI1B 0 1 TB0.1 (1) 1 1 4.2 (I/O) I: 0; O: 1 0 TB0.CCI2A and TB0.CCI2B 0 1 TB0.2 (1) 1 1 4.3 (I/O) I: 0; O: 1 0 TB0.CCI3A and TB0.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y To/From ADC12 Reference P5REN.x P5DIR.x DVSS 0 DVCC 1 1 0 1 P5OUT.x 0 Module X OUT 1 P5DS.x 0: Low drive 1: High drive P5SEL.x P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– P5IN.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 47. Port P5 (P5.0 and P5.1) Pin Functions PIN NAME (P5.x) P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– x 0 1 FUNCTION P5.0 (I/O) (4) (5) (6) (7) (8) P5DIR.x P5SEL.x REFOUT I: 0; O: 1 0 X VeREF+ (3) X 1 0 VREF+ (4) X 1 1 A8 (5) X 1 0 P5.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P5, P5.2, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.2 P5DIR.2 DVSS 0 DVCC 1 1 0 1 P5OUT.2 0 Module X OUT 1 P5DS.2 0: Low drive 1: High drive P5SEL.2 P5.2/XT2IN P5IN.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P5, P5.3, Input/Output With Schmitt Trigger Pad Logic To XT2 P5REN.3 P5DIR.3 DVSS 0 DVCC 1 1 0 1 P5OUT.3 0 Module X OUT 1 P5.3/XT2OUT P5DS.3 0: Low drive 1: High drive P5SEL.3 P5IN.3 Bus Keeper EN Module X IN D Table 48. Port P5 (P5.2) Pin Functions PIN NAME (P5.x) P5.2/XT2IN P5.3/XT2OUT (1) (2) (3) x 2 3 FUNCTION P5.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5DS.x 0: Low drive 1: High drive P5SEL.x P5.4/UCB1SOMI/UCB1SCL P5.5/UCB1CLK/UCA1STE P5.6/UCA1TXD/UCA1SIMO P5.7/UCA1RXD/UCA1SOMI P5IN.x EN Module X IN D Table 49. Port P5 (P5.4 to P5.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P6REN.x P6DIR.x DVSS 0 DVCC 1 1 0 1 P6OUT.x 0 Module X OUT 1 P6DS.x 0: Low drive 1: High drive P6SEL.x P6IN.x EN Module X IN Bus Keeper P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 50. Port P6 (P6.0 to P6.7) Pin Functions PIN NAME (P6.x) P6.0/A0 x 0 FUNCTION P6.0 (I/O) A0 (2) P6.1/A1 1 P6.1 (I/O) A1 (2) P6.2/A2 2 3 4 5 6 7 (3) 78 (3) P6.7 (I/O) A7 (2) (1) (2) (2) (3) P6.6 (I/O) A6 (2) P6.7/A7 (3) P6.5 (I/O) A5 (1) P6.6/A6 (3) P6.4 (I/O) A4 (2) P6.5/A5 (3) P6.3 (I/O) A3 (2) P6.4/A4 (3) P6.2 (I/O) A2 (2) P6.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P7, P7.0, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.0 P7DIR.0 DVSS 0 DVCC 1 1 0 1 P7OUT.0 0 Module X OUT 1 P7DS.0 0: Low drive 1: High drive P7SEL.0 P7.0/XIN P7IN.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P7, P7.1, Input/Output With Schmitt Trigger Pad Logic To XT1 P7REN.1 P7DIR.1 DVSS 0 DVCC 1 1 0 1 P7OUT.1 0 Module X OUT 1 P7.1/XOUT P7DS.1 0: Low drive 1: High drive P7SEL.0 XT1BYPASS P7IN.1 Bus Keeper EN Module X IN D Table 51. Port P7 (P7.0 and P7.1) Pin Functions PIN NAME (P7.x) P7.0/XIN x 0 FUNCTION P7.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger Pad Logic P7REN.x P7DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P7OUT.x DVSS P7.2/TB0OUTH/SVMOUT P7.3/TA1.2 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x EN Module X IN D Table 52. Port P7 (P7.2 and P7.3) Pin Functions PIN NAME (P7.x) P7.2/TB0OUTH/SVMOUT P7.3/TA1.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Pad Logic To ADC12 INCHx = y P7REN.x P7DIR.x DVSS 0 DVCC 1 1 0 1 P7OUT.x 0 Module X OUT 1 P7.4/A12 P7.5/A13 P7.6/A14 P7.7/A15 P7DS.x 0: Low drive 1: High drive P7SEL.x P7IN.x Bus Keeper EN D Module X IN Table 53. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) P7.4/A12 x 4 FUNCTION P7.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger Pad Logic P8REN.x P8DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P8OUT.x DVSS P8.0/TA0.0 P8.1/TA0.1 P8.2/TA0.2 P8.3/TA0.3 P8.4/TA0.4 P8.5/TA1.0 P8.6/TA1.1 P8.7 P8DS.x 0: Low drive 1: High drive P8SEL.x P8IN.x EN D Module X IN Table 54. Port P8 (P8.0 to P8.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger Pad Logic P9REN.x P9DIR.x 0 0 Module X OUT 1 0 DVCC 1 P9DS.x 0: Low drive 1: High drive P9SEL.x P9IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P9OUT.x DVSS P9.0/UCB2STE/UCA2CLK P9.1/UCB2SIMO/UCB2SDA P9.2/UCB2SOMI/UCB2SCL P9.3/UCB2CLK/UCA2STE P9.4/UCA2TXD/UCA2SIMO P9.5/UCA2RXD/UCA2SOMI P9.6 P9.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger Pad Logic P10REN.x P10DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P10OUT.x DVSS P10.0/UCB3STE/UCA3CLK P10.1/UCB3SIMO/UCB3SDA P10.2/UCB3SOMI/UCB3SCL P10.3/UCB3CLK/UCA3STE P10.4/UCA3TXD/UCA3SIMO P10.5/UCA3RXD/UCA3SOMI P10.6 P10.7 P10DS.x 0: Low drive 1: High drive P10SEL.x P10IN.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger Pad Logic P11REN.x P11DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P11OUT.x DVSS P11.0/ACLK P11.1/MCLK P11.2/SMCLK P11DS.x 0: Low drive 1: High drive P11SEL.x P11IN.x EN D Module X IN Table 57. Port P11 (P11.0 to P11.2) Pin Functions PIN NAME (P11.x) P11.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.0 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 DVSS 0 DVCC 1 1 PJ.0/TDO PJDS.0 0: Low drive 1: High drive From JTAG PJIN.0 EN D Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Pad Logic PJREN.x PJDIR.x 0 DVSS 1 PJOUT.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 58. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x CONTROL BITS/ SIGNALS (1) FUNCTION PJDIR.x PJ.0/TDO 0 (2) I: 0; O: 1 PJ.1 (I/O) (2) I: 0; O: 1 PJ.0 (I/O) TDO (3) PJ.1/TDI/TCLK 1 X TDI/TCLK (3) PJ.2/TMS 2 PJ.2 (I/O) TMS (3) PJ.3/TCK 3 (1) (2) (3) (4) 88 X I: 0; O: 1 (4) PJ.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 TLV (Device Descriptor) Structures Table 59 lists the complete contents of the device descriptor tag-length-value (TLV) structure. Table 59.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com Table 59.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 www.ti.com SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 Table 59.
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MSP430F5438, MSP430F5437, MSP430F5436, MSP430F5435 MSP430F5419, MSP430F5418 SLAS612D – AUGUST 2009 – REVISED AUGUST 2013 www.ti.com REVISION HISTORY REVISION SLAS612 92 DESCRIPTION Initial release SLAS612A Removed previews of MSP430F5437IZQW, MSP430F5435IZQW, MSP430F5418IZQW SLAS612B All A-suffix devices moved to separate data sheet (SLAS655) SLAS612C Corrected base address for USCI_B3 SLAS612D Changed status to NRND. Added Applications. Table 2, Corrected ACLK description.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing MSP430F5418IPNR LQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2 MSP430F5419IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 MSP430F5435IPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F5418IPNR LQFP MSP430F5419IPZR LQFP PN 80 1000 367.0 367.0 45.0 PZ 100 1000 367.0 367.0 45.0 MSP430F5435IPNR LQFP MSP430F5436IPZR LQFP PN 80 1000 367.0 367.0 45.0 PZ 100 1000 367.0 367.0 MSP430F5437IPNR 45.0 LQFP PN 80 1000 367.0 367.0 45.0 MSP430F5438IPZR LQFP PZ 100 1000 367.0 367.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.