MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D D − Active Mode: 400 μA at 1 MHz, 2.2 V − Standby Mode: 1.3 μA − Off Mode (RAM Retention): 0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 AVAILABLE OPTIONS{ PACKAGED DEVICES} TA −40°C 40°C to 85°C PLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW) MSP430FG4616IPZ MSP430FG4616IZQW MSP430FG4617IPZ MSP430FG4617IZQW MSP430FG4618IPZ MSP430FG4618IZQW MSP430FG4619IPZ MSP430FG4619IZQW MSP430CG4616IPZ MSP430CG4616IZQW MSP430CG4617IPZ MSP430CG4617IZQW MSP430CG4618IPZ MSP430CG4618IZQW MSP430CG4619IPZ MSP430CG4619IZQW † For the most current packag
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P2.4/UCA0TXD P2.5/UCA0RXD P2.6/CAOUT P2.7/ADC12CLK/DMAE0 P3.0/UCB0STE P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 P4.0/UTXD1 P4.1/URXD1 DVSS2 DVCC2 LCDCAP/R33 P5.7/R23 P5.6/LCDREF/R13 P5.5/R03 P5.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 pin designation, MSP430xG461xIZQW (top view) A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 NOTE: For terminal assignments, see the MSP430xG461x Terminal Functions table.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 functional block diagram XIN/ XT2IN XOUT/ XT2OUT 2 2 Oscillators FLL+ DVCC1/2 DVSS1/2 Enhanced Emulation (FG only) JTAG Interface AVSS P1.x/P2.x 2x8 Flash (FG) ROM (CG) ACLK 120kB 116kB 92kB 92kB SMCLK MCLK 8MHz CPUX incl.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Terminal Functions TERMINAL I/O DESCRIPTION NO. PZ NO. ZQW DVCC1 1 A1 P6.3/A3/OA1O 2 B1 P6.4/A4/OA1I0 3 P6.5/A5/OA2O 4 P6.6/A6/DAC0/OA2I0 5 P6.7/A7/DAC1/SVSIN 6 C3 I/O General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NO. PZ NO. ZQW I/O P8.2/S23 35 M5 I/O General-purpose digital I/O / LCD segment output 23 P8.1/S24 36 H5 I/O General-purpose digital I/O / LCD segment output 24 P8.0/S25 37 J5 I/O General-purpose digital I/O / LCD segment output 25 P7.7/S26 38 M6 I/O General-purpose digital I/O / LCD segment output 26 P7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NO. PZ NO. ZQW I/O DESCRIPTION P3.4/TB3 67 E12 I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output P3.3/UCB0CLK 68 E11 I/O General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock output—USCI_B0/SPI mode P3.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NO. PZ NO. ZQW AVSS 98 A3 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1 DVSS1 (see Note 1) 99 B3 Digital supply voltage, negative terminal AVCC 100 A2 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1; must not power up prior to DVCC1/DVCC2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g., CALL PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 special function registers (SFRs) The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs should be accessed with byte instructions. interrupt enable 1 and 2 7 Address 6 0h 5 4 ACCVIE NMIIE rw–0 WDTIE 1 OFIE rw–0 0 WDTIE rw–0 Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a general-purpose timer.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 interrupt flag register 1 and 2 7 Address 6 5 02h 4 3 2 NMIIFG rw–0 rw–1 WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin 7 Address 03h 6 BTIFG 5 4 UTXIFG1 URXIFG1 rw–1 rw–0 3 rw–0 UCA0RXIFG USCI_A0 receive-interrupt flag
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 memory organization MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619 Size Flash Flash 92KB 0FFFFh − 0FFC0h 018FFFh − 002100h 92KB 0FFFFh − 0FFC0h 019FFFh − 003100h 116KB 0FFFFh − 0FFC0h 01FFFFh − 003100h 120KB 0FFFFh − 0FFC0h 01FFFFh − 002100h Size 4KB 020FFh − 01100h 8KB 030FFh − 01100h 8KB 030FFh − 01100h 4KB 020FFh − 01100h Extended Size 2KB 020FFh − 01900h 6KB 030FFh − 01900h 6KB 030FFh − 01900h 2
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 bootstrap loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. The BSL is optional for ROM-based devices.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide (SLAU056). DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 LCD_A drive with regulated charge pump The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Timer_B7 Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Comparator_A The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog+ Watchdog timer control WDTCTL 0120h Timer_B7 _ Capture/compare register 6 TBCCR6 019Eh Capture/compare register 5 TBCCR5 019Ch Capture/compare register 4 TBCCR4 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B regist
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) DMA DMA Channel 0 DMA Channel 1 DMA Channel 2 24 DMA module control 0 DMACTL0 0122h DMA module control 1 DMACTL1 0124h DMA interrupt vector DMAIV 0126h DMA channel 0 control DMA0CTL 01D0h DMA channel 0 source address DMA0SA 01D2h DMA channel 0 destination address DMA0DA 01D6h DMA channel 0 transfer size DMA0SZ 01DAh DMA chann
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) ADC12 Conversion memory 15 ADC12MEM15 015Eh See also Peripherals With Byte y Access Conversion memory 14 ADC12MEM14 015Ch Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS OA2 Operational Amplifier 2 control register 1 Operational Amplifier 2 control register 0 OA2CTL1 OA2CTL0 0C5h 0C4h OA1 Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 0 OA1CTL1 OA1CTL0 0C3h 0C2h OA0 Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 0 OA0CTL1 OA0CTL0 0C1h 0C0h LCD_A
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) USCI USCI I2C Slave Address UCBI2CSA 011Ah USCI I2C Own Address UCBI2COA 0118h USCI Synchronous Transmit Buffer UCBTXBUF 06Fh USCI Synchronous Receive Buffer UCBRXBUF 06Eh USCI Synchronous Status UCBSTAT 06Dh USCI I2C Interrupt Enable UCBI2CIE 06Ch USCI Synchronous Bit Rate 1 UCBBR1 06Bh USCI Synchronous Bit Rate 0 UCBBR0 06Ah
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P10 Port P9 Port P8 Port P7 Port P6 Port P5 Port P4 Port P3 Port P2 Port P1 28 Port P10 selection P10SEL 00Fh Port P10 direction P10DIR 00Dh Port P10 output P10OUT 00Bh Port P10 input P10IN 009h Port P9 selection P9SEL 00Eh Port P9 direction P9DIR 00Ch Port P9 output P9OUT 00Ah Port P9 input P9IN 008h Port P8 se
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Special p functions SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage range applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage range applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . .
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS Active mode ((see Note 1 and Note 4)) f(MCLK) = f(SMCLK) = 1 MHz, MH f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) (FG461x: Program executes from flash) I(AM) MAX 280 370 VCC = 3 V 470 580 VCC = 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) PARAMETER TEST CONDITIONS VIT+ Positive going input threshold voltage Positive-going VIT− Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ − VIT−) MIN TYP MAX VCC = 2.2 V 1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 to P10 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN TYP MAX IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC IOH(max) = −1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 25°C VCC = 2.2 V P2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP f = 1 MHz td(LPM3) f = 2 MHz Delay time MAX UNIT 6 6 VCC = 2.2 V/3 V f = 3 MHz μs 6 RAM PARAMETER VRAMh TEST CONDITIONS CPU halted (see Note 1) MIN 1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) LCD_A PARAMETER TEST CONDITIONS Supply voltage (see Note 2) Charge pump enabled (LCDCPEN = 1; VLCDx > 0000) ICC(LCD) Supply current (see Note 2 ) VLCD(typ)=3 V; LCDCPEN = 1, VLCDx= 1000; all segments on, fLCD = fACLK/32, no LCD connected (see Note 4) TA = 25°C CLCD Capacitor on LCDCAP (see Note 1 and Note
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS I(CC) CAON 1 CARSEL=0, CAON=1, CARSEL 0 CAREF=0 CAREF 0 I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=1/2/3, No load at P1.6/CA0 P1 6/CA0 and P1.7/CA1 V(Ref025) V(Ref050) Voltage @ 0.25 V V CC TYP MAX VCC = 2.2 V 25 40 VCC = 3 V 45 60 VCC = 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 typical characteristics REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 650 VCC = 2.2 V 600 VREF − Reference Voltage − mV VREF − Reference Voltage − mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 TA − Free-Air Temperature − °C Figure 6. V(RefVT) vs Temperature 0V 0 −5 15 35 55 Figure 7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP td(BOR) dVCC/dt ≤ 3 V/s (see Figure 10) VCC(start) V(B_IT−) Vhys(B_IT−) t(reset) UNIT 2000 μs 0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 typical characteristics (continued) VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 12.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 typical characteristics Software Sets VLD>0: SVS is Active VCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) BrownOut Region Brownout Region Brownout 1 0 td(BOR) SVSOut t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 13. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(drop) VCC(drop) − V 1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER f(DCOCLK) VCC N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0 MIN TYP 2.2 V 0.3 0.65 1.25 3V 0.3 0.7 1.3 2.2 V 2.5 5.6 10.5 3V 2.7 6.1 11.3 2.2 V 0.7 1.3 2.3 3V 0.8 1.5 2.5 2.2 V 5.7 10.8 18 3V 6.5 12.1 20 2.2 V 1.2 2 3 3V 1.3 2.2 3.5 2.2 V 9 15.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Sn - Stepsize Ratio between DCO Taps electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 1.17 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 16.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER CXIN CXOUT Integrated input capacitance (see Note 4) Integrated output capacitance (see Note 4) TEST CONDITIONS MIN 0 OSCCAPx = 1h, VCC = 2.2 V / 3 V 10 OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 OSCCAPx = 3h, VCC = 2.2 V / 3 V 18 OSCCAPx = 0h, VCC = 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART mode) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals Baudrate in MBaud) tτ UART receive deglitch time (see Note 1) TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ± 10% 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID ,MO SIMO Figure 18. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI SOMI tVALID ,MO SIMO Figure 19.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,SIMO tHD,SIMO SIMO tACC tVALID ,SOMI tDIS SOMI Figure 20.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C mode) (see Figure 22) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ± 10% 2.2 V/3 V 0 fSCL ≤ 100kHz 2.2 V/3 V 4.0 fSCL > 100kHz 2.2 V/3 V 0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All external Ax terminals.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER Positive built in reference built-in voltage output VREF+ AVCC(min) AVCC minimum voltage, Positive built-in built in reference active IVREF+ Load current out of VREF+ terminal Load current regulation Load-current VREF+ terminal IL(VREF)+ TEST CONDITIONS MIN NOM
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 DVCC1/2 From Power Supply + − 10 μ F DVSS1/2 100 nF AVCC + − 10 μ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 100 nF VREF+ or VeREF+ + − Apply External Reference 10 μ F 100 nF VREF−/VeREF− + − 10 μ F MSP430FG461x AVSS 100 nF Figure 24.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time MIN NOM MAX UNIT For specified performance of ADC12 linearity parameters VCC = 2.2V/3 V 0.45 5 6.3 MHz ADC12DIV=0, fADC12CLK=fADC12OSC VCC = 2.2 V/ 3 V 3.7 5 6.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS VCC MIN NOM MAX Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 40 120 ISENSOR 3V 60 160 VSENSOR (see Note 2) ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 26) PARAMETER TEST CONDITIONS Resolution INL DNL EO MIN (12-bit Monotonic) Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 1) Offset voltage without calibration (see Notes 1, 2) Offset voltage with calibration (see Notes 1, 2) dE(O
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA INL − Integral Nonlinearity Error − LSB 4 VCC = 2.2 V, VREF = 1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER TEST CONDITIONS VCC MIN No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 VO Output voltage range (see Note 1, Figure 29) No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 RLoad= 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS Reference input voltage range VeREF+ VCC MIN DAC12IR=0 (see Notes 1 and 2) 2 2 V/3 V 2.2 DAC12IR=1 (see Notes 3 and 4) DAC12_0 IR=DAC12_1 IR =0 TYP MAX AVCC/3 AVCC+0.2 AVcc AVcc+0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 31.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) operational amplifier OA, supply specifications PARAMETER VCC ICC TEST CONDITIONS Supply voltage Supply current (see Note 1) VCC — MIN TYP 2.2 MAX UNIT 3.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 operational amplifier OA, input/output specifications PARAMETER TEST CONDITIONS VCC OARRIP = 1 (rail-to-rail mode off) VI/P Voltage supply supply, I/P IIkg Input leakage current, I/P (see Notes 1 and 2) OARRIP = 0 (rail-to-rail mode on) TA = −40 to +55_C — — TA = +55 to +85_C MIN TYP VCC−1.2 −0.1 VCC+0.1 −5 ±0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) RO/P(OAx) Max RLoad ILoad AV CC OAx 2 CLoad O/P(OAx) Min 0.2V AV CC −0.2VAV V CC OUT Figure 34. OAx Output Resistance Tests operational amplifier OA, dynamic specifications PARAMETER SR TEST CONDITIONS Slew rate VCC TYP MAX UNIT — 1.2 Medium Mode — 0.8 Slow Mode — 0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4) PARAMETER G Gain TEST CONDITIONS VCC MIN TYP MAX OAFBRx = 0 0.996 1.00 1.002 OAFBRx = 1 1.329 1.334 1.340 OAFBRx = 2 1.987 2.001 2.016 OAFBRx = 3 2.64 2.667 2.70 2 2 V/ 3 V 2.2 3.93 4.00 4.06 OAFBRx = 5 5.22 5.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) flash memory (MSP430FG461x devices only) TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and Erase supply voltage fFTG Flash Timing Generator frequency IPGM Supply current from DVCC during program IERASE Supply current from DVCC during erase IGMERASE Supply current from DVCC during glob
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematics Port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 Module X OUT 1 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Note: x = 0,1,2,3,4,5 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P1.0/TA0 P1.1/TA0/MCLK P1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P1 (P1.0 to P1.5) pin functions (P1 X) PIN NAME (P1.X) P1.0/TA0 CONTROL BITS / SIGNALS X 0 FUNCTION P1.0 (I/O) Timer_A3.CCI0A Timer_A3.TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK 1 2 3 4 5 P1DIR.x P1SEL.x I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 Timer_A3.CCI0B 0 1 MCLK 1 1 I: 0; O: 1 0 Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1 I: 0; O: 1 0 Timer_B7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P1, P1.6, P1.7, input/output with Schmitt trigger Pad Logic DVSS DVSS CAPD.x P1DIR.x 0 Direction 0: Input 1: Output 1 P1OUT.x 0 Module X OUT 1 P1.6/CA0 P1.7/CA1 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P2CA0 P1IE.x P1IRQ.x EN Comp_A Q P1IFG.x P1SEL.x P1IES.x 0 1 CA0 Set + Interrupt Edge Select − 0 1 CA1 Note: x = 6,7 P2CA1 Port P1 (P1.6 and P1.7) pin functions PIN NAME (P1.X) (P1 X) P1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger Pad Logic DVSS DVSS TBOUTH P2DIR.x 0 Direction 0: Input 1: Output 1 P2OUT.x 0 Module X OUT 1 Bus Keeper P2SEL.x EN P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 P2.6/CAOUT P2.7/ADC12CLK/DMAE0 P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions (P2 X) PIN NAME (P2.X) P2.0/TA2 CONTROL BITS / SIGNALS X 0 FUNCTION P2.0 (I/O) Timer_A3.CCI2A Timer_A3.TA2 P2.1/TB0 P2.2/TB1 P2.3/TB3 1 2 3 P2.6/CAOUT 6 P2.7/ADC12CLK/DMAE0 7 P2SEL.x I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 Timer_B7.CCI0A and Timer_B7.CCI0B 0 1 Timer_B7.TB0 (see Note 1) 1 1 I: 0; O: 1 0 Timer_B7.CCI1A and Timer_B7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P2, P2.4 to P2.5, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P2DIR.x Direction control from Module X P2OUT.x Module X OUT 0 Direction 0: Input 1: Output 1 0 1 P2.4/UCA0TXD P2.5/UCA0RXD Bus Keeper P2SEL.x EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Note: x = 4,5 Port P2 (P2.4 and P2.5) pin functions PIN NAME (P2.X) (P2 X) P2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P3, P3.0 to P3.3, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P3DIR.x 0 Direction 0: Input 1: Output 1 P3OUT.x 0 Module X OUT 1 Bus Keeper P3SEL.x P3.0/UCB0STE P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK EN P3IN.x EN Module X IN D Note: x = 0,1,2,3 Port P3 (P3.0 to P3.3) pin functions PIN NAME (P3.X) (P3 X) P3.0/UCB0STE CONTROL BITS / SIGNALS X 0 FUNCTION P3.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P3, P3.4 to P3.7, input/output with Schmitt trigger Pad Logic DVSS DVSS TBOUTH P3DIR.x 0 Direction 0: Input 1: Output 1 P3OUT.x 0 Module X OUT 1 P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D Note: x = 4,5,6,7 Port P3 (P3.4 to P3.7) pin functions PIN NAME (P3.X) (P3 X) P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 CONTROL BITS / SIGNALS X 4 5 6 7 FUNCTION P3DIR.x P3SEL.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P4, P4.0 to P4.1, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P4DIR.x 0 Direction control from Module X Direction 0: Input 1: Output 1 0 P4OUT.x 1 Module X OUT P4.1/URXD1 P4.0/UTXD1 Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Note: x = 0,1 Port P4 (P4.0 to P4.1) pin functions PIN NAME (P4.X) (P4 X) CONTROL BITS / SIGNALS X P4.0/UTXD1 0 P4.1/URXD1 1 FUNCTION P4.0 (I/O) USART1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P4, P4.2 to P4.7, input/output with Schmitt trigger Pad Logic LCDS32/36 Segment Sy DVSS P4DIR.x Direction control from Module X P4OUT.x Module X OUT 0 Direction 0: Input 1: Output 1 0 1 Bus Keeper P4SEL.x EN P4.7/UCA0RXD/S34 P4.6/UCA0TXD/S35 P4.5/UCLK1/S36 P4.4/SOMI1/S37 P4.3/SIMO1/S38 P4.2/STE1/S39 P4IN.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P4 (P4.2 to P4.5) pin functions (P4 X) PIN NAME (P4.X) P4.2/STE1/S39 CONTROL BITS / SIGNALS X 2 FUNCTION P4.2 (I/O) USART1.STE1 S39 (see Note 1) P4.3/SIMO/S38 P4.4/SOMI/S37 P4.5/SOMI/S36 P4.6/UCA0TXD/S35 P4.7/UCA0RXD/S34 3 4 5 6 7 P4.3 (I/O) P4SEL.x LCDS36 0 0 X 1 0 X X 1 I: 0; O: 1 0 0 USART1.SIMO1 (see Notes 1, 2) X 1 0 S38 (see Note 1) X X 1 I: 0; O: 1 0 0 P4.4 (I/O) USART1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P5, P5.0, input/output with Schmitt trigger INCH=13# Pad Logic A13# LCDS0 Segment Sy P5DIR.x 0 1 P5OUT.x DVSS Direction 0: Input 1: Output 0 1 Bus Keeper P5SEL.x P5.0/S1/A13/OA1I1 EN P5IN.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P5 (P5.0) pin functions CONTROL BITS / SIGNALS PIN NAME (P5.X) X P5.0/S1/A13/OA1I1 0 FUNCTION P5.0 (I/O) (see Note 1) P5DIR.x P5SEL.x INCHx OAPx(OA1) OANx(OA1) LCDS0 0 I: 0; O: 1 0 X X OAI11 (see Note 1) 0 X X 1 0 A13 (see Notes 1, 3) X 1 13 X X S1 enabled (see Note 1) X 0 X X 1 S1 disabled (see Note 1) X 1 X X 1 NOTES: 1. X: Don’t care 2. N/A: Not available or not applicable. 3.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P5, P5.1, input/output with Schmitt trigger INCH=12# Pad Logic A12# LCDS0 Segment Sy DAC12.1OPS P5DIR.x 0 1 P5OUT.x DVSS Direction 0: Input 1: Output 0 1 P5.1/S0/A12/DAC1 Bus Keeper P5SEL.x EN P5IN.x Note: x = 1 y=0 DVSS DAC1 0 1 2 0 if DAC12.1AMPx = 0 and DAC12.1OPS = 1 1 if DAC12.1AMPx = 1 and DAC12.1OPS = 1 2 if DAC12.1AMPx > 1 and DAC12.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P5 (P5.1) pin functions CONTROL BITS / SIGNALS (P5 X) PIN NAME (P5.X) X P5.1/S0/A12/DAC1 1 FUNCTION P5DIR.x P5SEL.x INCHx DAC12.1OPS DAC12.1AMPx LCDS0 P5.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P5, P5.2 to P5.4, input/output with Schmitt trigger Pad Logic LCD Signal DVSS P5DIR.x 0 Direction 0: Input 1: Output 1 P5OUT.x DVSS 0 1 P5.2/COM1 P5.3/COM2 P5.4/COM3 Bus Keeper P5SEL.x EN P5IN.x Note: x = 2,3,4 Port P5 (P5.2 to P5.4) pin functions (P5 X) PIN NAME (P5.X) CONTROL BITS / SIGNALS X P5.2/COM1 2 P5.3/COM2 3 FUNCTION P5.2 (I/O) COM1 (see Note 1) P5.3 (I/O) COM2 (see Note 1) P5.4/COM3 4 P5.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P5, P5.5 to P5.7, input/output with Schmitt trigger Pad Logic LCD Signal DVSS P5DIR.x 0 Direction 0: Input 1: Output 1 P5OUT.x DVSS 0 1 Bus Keeper P5SEL.x P5.5/R03 P5.6/LCDREF/R13 P5.7/R03 EN P5IN.x Note: x = 5,6,7 Port P5 (P5.5 to P5.7) pin functions (P5 X) PIN NAME (P5.X) CONTROL BITS / SIGNALS X P5.5/R03 5 P5.6/LCDREF/R13 6 FUNCTION P5.5 (I/O) R03 (see Note 1) P5.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger INCH=0/2/4# Pad Logic Ay# P6DIR.x 0 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/A0/OA0I0 P6.2/A2/OA0I1 P6.4/A4/OA1I0 0 1 Bus Keeper P6SEL.x EN P6IN.x Note: x = 0, 2, 4 y = 0, 1 # = Signal from or to ADC12 + OA0/1 − Port P6 (P6.0, P6.2, and P6.4) pin functions CONTROL BITS / SIGNALS PIN NAME (P6.X) P6.0/A0/OA0I0 P6.2/A2/OA0I1 P6.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger INCH=1/3/5# Pad Logic Ay# P6DIR.x 0 1 P6OUT.x DVSS Direction 0: Input 1: Output P6.1/A1/OA0O P6.3/A3/OA1O P6.5/A5/OA2O 0 1 Bus Keeper P6SEL.x EN P6IN.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P6 (P6.1, P6.3, and P6.5) pin functions (P6 X) PIN NAME (P6.X) P6.1/A1/OA0O CONTROL BITS / SIGNALS X 1 FUNCTION P6DIR.x P6SEL.x OAADC1 OAPMx INCHx P6.1 (I/O) (see Note 1) I: 0; O: 1 0 X 0 X OA0O (see Notes 1, 4) X X 1 >0 X A1 (see Notes 1, 3) P6.3/A3/OA1O P6.5/A5/OA2O 3 5 X 1 X 0 1 P6.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P6, P6.6, input/output with Schmitt trigger INCH=6# Pad Logic A6# P6DIR.x 0 1 P6OUT.x DVSS Direction 0: Input 1: Output P6.6/A6/DAC0/OA2I0 0 1 Bus Keeper P6SEL.x DAC12.0AMP > 0 DAC12.0OPS EN P6IN.x Note: x = 6 # = Signal from or to ADC12 + OA2 − DVSS DAC0 0 1 2 0 if DAC12.0AMPx= 0 and DAC12.0OPS = 0 1 if DAC12.0AMPx= 1 and DAC12.0OPS = 0 2 if DAC12.0AMPx> 1 and DAC12.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P6 (P6.6) pin functions CONTROL BITS / SIGNALS PIN NAME (P6.X) X FUNCTION P6.6/A6/DAC0/OA2I0 6 P6DIR.x P6SEL.x INCHx DAC12.0OPS DAC12.0AMPx OAPx (OA2) OANx (OA2) P6.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P6, P6.7, input/output with Schmitt trigger To SVS Mux # INCH=7 Pad Logic A7# P6DIR.x 0 1 P6OUT.x DVSS Direction 0: Input 1: Output 0 1 P6SEL.x Bus Keeper VLD =15 EN P6.7/A7/DAC1/SVSIN DAC12.1AMP > 0 DAC12.1OPS P6IN.x Note: x = 7 # = Signal from or to ADC12 DVSS DAC1 0 1 2 0 if DAC12.1AMPx = 0 and DAC12.1OPS = 0 1 if DAC12.1AMPx = 1 and DAC12.1OPS = 0 2 if DAC12.1AMPx > 1 and DAC12.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P6 (P6.7) pin functions CONTROL BITS / SIGNALS (P6 X) PIN NAME (P6.X) X P6.7/A7/DAC1/SVSIN 7 FUNCTION P6DIR.x P6SEL.x INCHx DAC12.1OPS DAC12.1AMPx P6.7 (I/O) (see Note 1) I: 0; O: 1 0 X 1 X DAC1 high impedance (see Note 1) X X X 0 0 DVSS (see Note 1) X X X 0 1 DAC1 output (see Note 1) X X X 0 >1 A7 (see Notes 1, 2) X 1 7 X X SVSIN (see Notes 1,3) 0 1 0 1 X NOTES: 1.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P7, P7.0 to P7.3, input/output with Schmitt trigger Pad Logic LCDS28/32 Segment Sy DVSS P7DIR.x Direction control from Module X P7OUT.x Module X OUT 0 Direction 0: Input 1: Output 1 0 1 Bus Keeper P7SEL.x EN P7IN.x EN Module X IN D Note: x = 0, 1, 2, 3 y = 30, 31, 32, 33 88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P7.3/UCA0CLK/S30 P7.2/UCA0SOMI/S31 P7.1/UCA0SIMO/S32 P7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P7 (P7.0 to P7.1) pin functions CONTROL BITS / SIGNALS (P7 X) PIN NAME (P7.X) X P7.0/UCA0STE/S33 0 FUNCTION P7.0 (I/O) USCI_A0.UCA0STE (see Notes 1, 2) S33 (see Note 1) P7.1/UCA0SIMO/S32 P7.2/UCA0SOMI/S31 P7.3/UCA0CLK/S30 1 2 3 P7.1 (I/O) P7DIR.x P7SEL.x LCDS32 I: 0; O: 1 0 0 X 1 0 X X 1 I: 0; O: 1 0 0 USCI_A0.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P7, P7.4 to P7.7, input/output with Schmitt trigger Pad Logic LCDS24/28 Segment Sy DVSS P7DIR.x 0 Direction 0: Input 1: Output 1 P7OUT.x DVSS 0 1 P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29 Bus Keeper P7SEL.x EN P7IN.x Note: x = 4, 5, 6, 7 y = 26, 27, 28, 29 Port P7 (P7.4 to P7.5) pin functions PIN NAME (P7.X) (P7 X) P7.4/S29 CONTROL BITS / SIGNALS X 4 FUNCTION P7.4 (I/O) S29 (see Note 1) P7.5/S28 5 P7.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P8, P8.0 to P8.7, input/output with Schmitt trigger Pad Logic LCDS16/20/24 Segment Sy DVSS P8DIR.x 0 1 P8OUT.x DVSS Direction 0: Input 1: Output 0 1 Bus Keeper P8SEL.x EN P8IN.x P8.7/S18 P8.6/S19 P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23 P8.1/S24 P8.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P8 (P8.0 to P8.1) pin functions (P8 X) PIN NAME (P8.X) P8.0/S18 CONTROL BITS / SIGNALS X 0 FUNCTION P8.0 (I/O) S18 (see Note 1) P8.1/S19 0 P8.0 (I/O) S19 (see Note 1) P8.2/S20 2 P8.2 (I/O) S20 (see Note 1) P8.3/S21 3 P8.4/S22 4 P8.3 (I/O) S21 (see Note 1) P8.4 (I/O) S22 (see Note 1) P8.5/S23 5 P8.5 (I/O) S23 (see Note 1) P8DIR.x P8SEL.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P9, P9.0 to P9.7, input/output with Schmitt trigger Pad Logic LCDS8/12/16 Segment Sy DVSS P9DIR.x 0 1 P9OUT.x DVSS Direction 0: Input 1: Output 0 1 Bus Keeper P9SEL.x EN P9IN.x P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13 P9.3/S14 P9.2/S15 P9.1/S16 P9.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P9 (P9.0 to P9.1) pin functions (P9 X) PIN NAME (P9.X) P9.0/S17 CONTROL BITS / SIGNALS X 0 FUNCTION P9.0 (I/O) S17 (see Note 1) P9.1/S16 1 P9.1 (I/O) S16 (see Note 1) P9.2/S20 2 P9.2 (I/O) S15 (see Note 1) P9.3/S21 3 P9.4/S22 4 P9.3 (I/O) S14 (see Note 1) P9.4 (I/O) S13 (see Note 1) P9.5/S23 5 P9.5 (I/O) S12 (see Note 1) P9.6/S24 6 P9.7/S25 7 P9.6 (I/O) S11 (see Note 1) P9.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P10, P10.0 to P10.5, input/output with Schmitt trigger Pad Logic LCDS4/8 Segment Sy DVSS P10DIR.x 0 Direction 0: Input 1: Output 1 P10OUT.x DVSS 0 1 P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9 Bus Keeper P10SEL.x EN P10IN.x Note: x = 0,1,2,3,4,5 y = 9,8,7,6,5,4 Port P10 (P10.0 to P10.1) pin functions PIN NAME (P10 (P10.X) X) CONTROL BITS / SIGNALS X P10.0/S8 0 P10.1/S7 1 FUNCTION P10.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P10, P10.6, input/output with Schmitt trigger INCH=15# Pad Logic A15# LCDS0 Segment Sy P10DIR.x 0 Direction 0: Input 1: Output 1 P10OUT.x DVSS 0 1 P10.6/S3/A15 Bus Keeper P10SEL.x EN P10IN.x Note: x = 6 y =3 Port P10 (P10.6) pin functions PIN NAME (P10 (P10.X) X) P10.6/S3/A15 CONTROL BITS / SIGNALS X 6 FUNCTION P10DIR.x P10SEL.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 port P10, P10.7, input/output with Schmitt trigger INCH=14# Pad Logic A14# LCDS0 Segment Sy P10DIR.x 0 1 P10OUT.x DVSS Direction 0: Input 1: Output 0 1 Bus Keeper P10SEL.x P10.7/S2/A14/OA2I1 EN P10IN.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Port P10 (P10.7) pin functions CONTROL BITS / SIGNALS PIN NAME (P10.X) X FUNCTION P10.7/S2/A14/OA2I1 7 P10.7 (I/O) (see Note 1) P10DIR.x P10SEL.x INCHx OAPx (OA1) OANx (OA1) LCDS0 I: 0; O: 1 0 X X 0 A14 (see Notes 1, 3) X 1 14 X 0 OA2I1 (see Notes 1, 3) 0 X X 1 0 S2 enabled (see Note 1) X 0 X X 1 S2 disabled (see Note 1) X 1 X X 1 NOTES: 1. X: Don’t care 2.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 VeREF+/DAC0 DAC12.0OPS 0 DAC0_2_OA P6.6/A6/DAC0/OA2I0 1 Reference Voltage to DAC1 Reference Voltage to ADC12 Reference Voltage to DAC0 # Ve REF+ /DAC0 ’0’, if DAC12CALON = 0 DAC12AMPx>1 AND DAC12OPS=1 + − 1 0 ’1’, if DAC12AMPx>1 ’1’, if DAC12AMPx=1 DAC12OPS # If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled by JTAG DVCC TDI Burn and Test Fuse TDI/TCLK Test and Emulation DVCC TMS Module TMS DVCC TCK TCK RST/NMI Tau ~ 50 ns Brownout TCK 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 G D U S G D U S
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 Data Sheet Revision History Literature Number SLAS508 Summary Preliminary Product Preview datasheet release SLAS508A Production Data data sheet release SLAS508B Changed power consumption values in features (page 1) SLAS508C Changed tVALID,MO, tHD,SI, and tVALID,SO values (page 43) SLAS508D Changed I(AM) values for CG461x (page 29) SLAS508E Added ZQW package information Changed power consumption values for Standb
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430FG4616IPZR Package Package Pins Type Drawing LQFP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430FG4616IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 MSP430FG4616IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OR MSP430FG4618IZQWT MSP430FG4619IPZR BGA MI CROSTA R JUNI OR ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430FG4619IZQWR BGA MI CROSTA R JUNI OR LQFP ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430FG4617IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430FG4617IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.6 MSP430FG4618IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430FG4618IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336.6 336.6 28.6 MSP430FG4618IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336.6 336.6 28.
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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