MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Mixed Signal Microcontroller FEATURES 1 • 23 • Embedded Microcontroller – 16-Bit RISC Architecture up to 24-MHz Clock – Wide Supply Voltage Range (2 V to 3.6 V) – -40°C to 85°C Operation Optimized Ultralow-Power Modes Mode Active Mode Consumption (Typical) 81.4 µA/MHz Standby (LPM3 With VLO) 6.3 µA Real-Time Clock (LPM3.5 With Crystal) 1.5 µA Shutdown (LPM4.5) 0.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com APPLICATIONS • • • • Home Automation Security Sensor Management Data Acquisition CAUTION These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 1. Family Members(1)(2) (continued) eUSCI Device FRAM (KB) SRAM (KB) System Clock (MHz) MSP430FR5733 8 1 24 MSP430FR5732 MSP430FR5731 MSP430FR5730 8 4 4 1 1 1 24 24 16 1 8 MSP430FR5728 16 1 8 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 16 16 8 8 8 8 4 4 1 1 1 1 1 1 1 1 10 ch. 12 ch. 12 ext, 2 int ch. 16 ch.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Functional Block Diagram – MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA, MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA PJ.4/XIN DVCC DVSS VCORE PJ.5/XOUT AVCC AVSS P1.x 16 KB Clock System ACLK 8 KB SMCLK 4 KB FRAM MCLK CPUXV2 and Working Registers 1 KB (’5731, ‘5721) Power Management Boot ROM SYS Watchdog P3.x I/O Ports P1/P2 2×8 I/Os (’5739, ’5729) (’5735, ‘5725) PA P2.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Pin Designation – MSP430FR5721IRHA, MSP430FR5723IRHA, MSP430FR5725IRHA, MSP430FR5727IRHA, MSP430FR5729IRHA, MSP430FR5731IRHA, MSP430FR5733IRHA, MSP430FR5735IRHA, MSP430FR5737IRHA, MSP430FR5739IRHA RHA PACKAGE (TOP VIEW) P2.4/TA1.0/UCA1CLK/A7*/CD11 P2.3/TA0.0/UCA1STE/A6*/CD10 P2.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Functional Block Diagram – MSP430FR5721IDA, MSP430FR5725IDA, MSP430FR5729IDA, MSP430FR5731IDA, MSP430FR5735IDA, MSP430FR5739IDA PJ.4/XIN DVCC DVSS VCORE PJ.5/XOUT AVCC AVSS P1.x 16 KB Clock System ACLK (’5739, ’5729) 8 KB (’5735, ‘5725) SMCLK 4 KB CPUXV2 and Working Registers Boot ROM (’5731, ‘5721) FRAM MCLK 1 KB Power Management SYS Watchdog PA P2.x PB P3.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Pin Designation – MSP430FR5721IDA, MSP430FR5723IDA, MSP430FR5725IDA, MSP430FR5727IDA, MSP430FR5729IDA, MSP430FR5731IDA, MSP430FR5733IDA, MSP430FR5735IDA, MSP430FR5737IDA, MSP430FR5739IDA DA PACKAGE (TOP VIEW) PJ.4/XIN PJ.5/XOUT AVSS AVCC 1 38 2 37 3 36 4 35 P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-* P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+* P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2 P3.0/A12*/CD12 P3.1/A13*/CD13 P3.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Functional Block Diagram – MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE, MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE, MSP430FR5738IYQD PJ.4/XIN DVCC DVSS VCORE PJ.5/XOUT AVCC AVSS P1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Pin Designation – MSP430FR5720IRGE, MSP430FR5722IRGE, MSP430FR5724IRGE, MSP430FR5726IRGE, MSP430FR5728IRGE, MSP430FR5730IRGE, MSP430FR5732IRGE, MSP430FR5734IRGE, MSP430FR5736IRGE, MSP430FR5738IRGE RGE PACKAGE (TOP VIEW) PJ.4/XIN DVCC DVSS 1 20 21 23 19 18 17 16 15 14 13 VCORE P1.7/UCB0SOMI/UCB0SCL/TA1.0 P1.6/UCB0SIMO/UCB0SDA/TA0.0 P2.2/UCB0CLK P2.1/UCA0RXD/UCA0SOMI/TB0.0 P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK 12 7 PJ.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Pin Designation – MSP430FR5738IYQD YQD PACKAGE (TOP VIEW) P2.0 P2.2 P1.7 P1.6 VCORE VCORE P1.6 P1.7 P2.2 P2.0 E5 E4 E3 E2 E1 E1 E2 E3 E4 E5 P2.1 DVSS DVCC DVCC DVSS D1 D2 PJ.4 AVSS PJ.0 PJ.2 PJ.3 C1 C2 C3 C4 C5 TEST RST/NMI D YQD PACKAGE (BALL-SIDE VIEW) P2.1 RST/NMI TEST D3 D5 D4 D5 D4 D3 D2 D1 PJ.3 PJ.2 PJ.0 AVSS PJ.4 C5 C4 C3 C2 C1 PJ.1 P1.4 P1.0 AVCC PJ.5 PJ.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Functional Block Diagram – MSP430FR5720IPW, MSP430FR5724IPW, MSP430FR5728IPW, MSP430FR5730IPW, MSP430FR5734IPW, MSP430FR5738IPW PJ.4/XIN DVCC DVSS VCORE PJ.5/XOUT AVCC AVSS P1.x 16 KB Clock System ACLK (’5734, ‘5724) SMCLK 4 KB CPUXV2 and Working Registers 1 KB (’5730, ‘5720) FRAM MCLK I/O Ports P1/P2 1×8 I/Os 1×7 I/Os (’5738, ’5728) 8 KB Power Management Boot ROM SYS Watchdog PA P2.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Pin Designation – MSP430FR5720IPW, MSP430FR5722IPW, MSP430FR5724IPW, MSP430FR5726IPW, MSP430FR5728IPW, MSP430FR5730IPW, MSP430FR5732IPW, MSP430FR5734IPW, MSP430FR5736IPW, MSP430FR5738IPW PW PACKAGE (TOP VIEW) PJ.4/XIN PJ.5/XOUT AVSS AVCC P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-* P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+* P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2 P1.3/TA1.2/UCB0STE/A3*/CD3 P1.4/TB0.1/UCA0STE/A4*/CD4 P1.5/TB0.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 3. Terminal Functions TERMINAL NAME P1.0/TA0.1/DMAE0/ RTCCLK/A0/CD0/VeREF- P1.1/TA0.2/TA1CLK/ CDOUT/A1/CD1/VeREF+ P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2 P3.0/A12/CD12 P3.1/A13/CD13 P3.2/A14/CD14 P3.3/A15/CD15 (1) NO.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME P1.3/TA1.2/UCB0STE/ A3/CD3 P1.4/TB0.1/UCA0STE/ A4/CD4 P1.5/TB0.2/UCA0CLK/ A5/CD5 PJ.0/TDO/TB0OUTH/ SMCLK/CD6 (2) PJ.1/TDI/TCLK/TB1OUTH/ MCLK/CD7 (2) NO. RHA 8 9 10 11 12 RGE 4 5 6 7 8 DA 12 13 14 15 16 I/O PW 8 9 10 11 12 (1) DESCRIPTION YQD A4 B4 A5 C3 B5 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 3. Terminal Functions (continued) TERMINAL NO. NAME RHA P2.5/TB0.0/UCA1TXD/ UCA1SIMO 17 P2.6/TB1.0/UCA1RXD/ UCA1SOMI TEST/SBWTCK (2) (3) RST/NMI/SBWTDIO (2) (3) P2.0/TB2.0/UCA0TXD/ UCA0SIMO/TB0CLK/ACLK (3) P2.1/TB2.1/UCA0RXD/ UCA0SOMI/TB0.0 (4) P2.2/TB2.2/UCB0CLK/ TB1.0 P3.4/TB1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME P3.5/TB1.2/CDOUT P3.6/TB2.1/TB1CLK P3.7/TB2.2 P1.6/TB1.1/UCB0SIMO/ UCB0SDA/TA0.0 P1.7/TB1.2/UCB0SOMI/ UCB0SCL/TA1.0 VCORE (5) NO. RHA 25 26 27 28 RGE N/A N/A N/A 16 DA 27 28 29 30 I/O PW N/A N/A N/A 22 29 17 31 23 (1) DESCRIPTION YQD N/A N/A N/A E2 E3 I/O General-purpose digital I/O with port interrupt and wake up from LPMx.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 3. Terminal Functions (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION RHA RGE DA PW YQD AVSS 36 N/A 38 N/A N/A PJ.4/XIN 37 21 1 1 C1 I/O General-purpose digital I/O Input terminal for crystal oscillator XT1 PJ.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Development Tools Support All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools. Hardware Features See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Command-Line Programmer MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE. Community Resources The following links connect to TI community resources.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Short-Form Description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 4.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Memory Organization Table 5. Memory Organization (1) (2) MSP430FR5726 MSP430FR5727 MSP430FR5728 MSP430FR5729 MSP430FR5736 MSP430FR5737 MSP430FR5738 MSP430FR5739 MSP430FR5722 MSP430FR5723 MSP430FR5724 MSP430FR5725 MSP430FR5732 MSP430FR5733 MSP430FR5734 MSP430FR5735 MSP430FR5720 MSP430FR5721 MSP430FR5730 MSP430FR5731 15.5 KB 00FFFFh–00FF80h 00FF7Fh–00C200h 8.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Bootstrap Loader (BSL) The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in Table 6. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com FRAM The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Real-Time Clock (RTC_B) The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode integrates an internal calendar which compensates for months with fewer than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in LPM3.5 mode to minimize power consumption.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 9. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI ADDRESS 019Eh 019Ch INTERRUPT EVENT No interrupt pending 00h Brownout (BOR) 02h RSTIFG RST/NMI (BOR) 04h PMMSWBOR software BOR (BOR) 06h LPMx.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Enhanced Universal Serial Communication Interface (eUSCI) The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI module contains two portions, A and B.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 12. TA1 Signal Connections RHA RGE, YQD INPUT PIN NUMBER DA PW DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 2-P1.1 2-P1.1, A2‑P1.1 6-P1.1 6-P1.1 TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK 2-P1.1 2-P1.1, A2‑P1.1 6-P1.1 6-P1.1 TA1CLK TACLK 29-P1.7 17-P1.7, E3‑P1.7 31-P1.7 23-P1.7 TA1.0 CCI0A 35-P2.4 N/A 37-P2.4 28-P2.4 TA1.0 CCI0B DVSS GND 3-P1.2 8-P1.3 3-P1.2, N/A 4-P1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com TB0, TB1, TB2 TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. Each can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 13.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 14. TB1 Signal Connections RHA RGE, YQD INPUT PIN NUMBER DA PW DEVICE INPUT SIGNAL MODULE INPUT SIGNAL 26-P3.6 N/A (DVSS), N/A (DVSS) 28-P3.6 N/A (DVSS) TB1CLK TBCLK ACLK (internal) ACLK SMCLK (internal) SMCLK 26-P3.6 N/A (DVSS), N/A (DVSS) 28-P3.6 N/A (DVSS) TB1CLK TBCLK 23-P2.2 N/A (DVSS), N/A (DVSS) 25-P2.2 N/A (DVSS) TB1.0 CCI0A 18-P2.6 N/A (DVSS), N/A (DVSS) 20-P2.6 N/A (DVSS) TB1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com ADC10_B The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and a conversion result buffer. A window comparator with a lower limit and an upper limit allows CPU-independent result monitoring with three window comparator interrupt flags.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Peripheral File Map Table 16.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 17. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h Table 18. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM Control 0 PMMCTL0 00h PMM interrupt flags PMMIFG 0Ah PM5 Control 0 PM5CTL0 10h Table 19.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 23.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 26.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 28.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 31.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 33.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 34.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 35.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 37.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 39.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE) (2) –0.3 V to VCC + 0.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) Frequency (fMCLK = fSMCLK) (4) PARAMETER EXECUTION MEMORY VCC 1 MHz TYP IAM, FRAM_UNI (6) IAM,0% (7) FRAM 3V 0.27 FRAM 0% cache hit ratio 3V 0.42 4 MHz MAX TYP MAX 0.58 0.73 1.2 16 MHz (5) 8 MHz TYP MAX 1.0 1.6 2.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Typical Active Mode Supply Current, No Wait States 2.50 IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724 2.00 IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669 IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646 IAM, mA 1.50 IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708 1.00 0.50 IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150 IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708 0.00 0 1 2 3 4 5 6 7 8 9 fMCLK = f SMCLK , MHz Figure 2.
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MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Schmitt-Trigger Inputs – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Outputs – General Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Typical Characteristics – Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 16 V CC = 2.0 V Px.y TA = -40 ° C IOL - Typical Low-Level Output Current - mA 14 TA = 25 ° C 12 TA = 85 ° C 10 8 6 4 2 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Typical Characteristics – Outputs (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 IOH - Typical High-Level Output Current - mA V CC = 3.0 V Px.y -5 -10 -15 -20 -25 TA = 85 ° C -30 TA = 25 ° C -35 TA = -40 ° C -40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Crystal Oscillator, XT1, Low-Frequency (LF) Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ΔIVCC.
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MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.
MSP430FR573x MSP430FR572x www.ti.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE(AM) Core voltage, active mode 2 V ≤ DVCC ≤ 3.6 V 1.5 V VCORE(LPM) Core voltage, low-current mode 2 V ≤ DVCC ≤ 3.6 V 1.
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MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tSTE,DIS tVALID,MO tSTE,ACC SIMO Figure 7. SPI Master Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tSTE,ACC tVALID,MO tSTE,DIS SIMO Figure 8.
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MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tACC tDIS tVALID,SOMI SOMI Figure 9. SPI Slave Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tACC tVALID,SO tDIS SOMI Figure 10.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.
MSP430FR573x MSP430FR572x www.ti.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN (1) TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VeREF– (2) 1.4 AVCC V VeREF– Negative external reference voltage input VeREF+ > VeREF– (3) 0 1.2 V VeREF+ > VeREF– (4) 1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 REF, Temperature Sensor and Built-In VMID over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VSENSOR See TEST CONDITIONS (1) TCSENSOR VCC MIN ADC10ON = 1, INCH = 0Ah, TA = 0°C 2 V, 3 V ADC10ON = 1, INCH = 0Ah 2 V, 3 V MAX mV 2.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Comparator_D over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Overdrive = 10 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV) Propagation delay, AVCC = 2 V to 3.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2 V, 3 V 0.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.2, Input/Output With Schmitt Trigger Pad Logic External ADC reference (P1.0, P1.1) To ADC From ADC To Comparator From Comparator CDPD.x P1REN.x P1DIR.x 00 01 10 Direction 0: Input 1: Output 11 P1OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREFP1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ P1.2/TA1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 42. Port P1 (P1.0 to P1.2) Pin Functions PIN NAME (P1.x) P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- x 0 FUNCTION P1.0 (I/O) 1 (1) (2) (3) 2 P1SEL0.x I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 0 TA0.1 1 DMAE0 0 RTCCLK 1 (2) P1.1 (I/O) TA0.CCI2A 0 TA0.2 1 TA1CLK 0 CDOUT 1 A1 (1) (2) CD1 (1) (3) VeREF+ (1) P1.2/TA1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CDPD.x P1REN.x P1DIR.x 00 01 From module 2 10 Direction 0: Input 1: Output 11 P1OUT.x 00 From module 1 01 From module 2 10 DVSS 11 DVSS 0 DVCC 1 1 P1.3/TA1.2/UCB0STE/A3/CD3 P1.4/TB0.1/UCA0STE/A4/CD4 P1.5/TB0.2/UCA0CLK/A5/CD5 P1SEL0.x P1SEL1.x P1IN.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 43. Port P1 (P1.3 to P1.5) Pin Functions PIN NAME (P1.x) P1.3/TA1.2/UCB0STE/A3/CD3 x 3 FUNCTION P1.3 (I/O) P1.4 (I/O) 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 X (1) 0 1 X (5) A4 (2) (3) CD4 (2) (4) X 1 1 P1.5(I/O) I: 0; O: 1 0 0 0 1 1 0 1 1 TB0.CCI2A 0 TB0.2 1 A5 CD5 (5) 0 TB0.1 (2) (3) (2) (4) (3) (4) 0 TB0.CCI1A UCA0CLK (1) (2) 0 1 UCA0STE 5 I: 0; O: 1 TA1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger Pad Logic DVSS P1REN.x P1DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P1OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 From module 3 11 P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0 P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0 P1SEL0.x P1SEL1.x P1IN.x Bus Keeper EN To modules D Table 44. Port P1 (P1.6 to P1.7) Pin Functions PIN NAME (P1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger Pad Logic DVSS P2REN.x P2DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 From module 3 11 P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 P2.2/TB2.2/UCB0CLK/TB1.0 P2SEL0.x P2SEL1.x P2IN.x Bus Keeper EN D To modules Table 45. Port P2 (P2.0 to P2.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P2, P2.3 to P2.4, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CDPD.x P2REN.x P2DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P2.3/TA0.0/UCA1STE/A6/CD10 P2.4/TA1.0/UCA1CLK/A7/CD11 P2SEL0.x P2SEL1.x P2IN.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 46. Port P2 (P2.3 to P2.4) Pin Functions PIN NAME (P2.x) x P2.3/TA0.0/UCA1STE/A6/CD10 3 FUNCTION P2.3 (I/O) 0 0 0 1 1 0 X 1 1 I: 0; O: 1 0 0 0 1 1 0 1 1 1 P2.4 (I/O) X (1) TA1.CCI0B 0 TA1.0 1 UCA1CLK A7 (2) CD11 (3) (4) I: 0; O: 1 TA0.0 A6 CD10 (1) (2) P2SEL0.x 0 (2) (3) (2) (4) 4 P2SEL1.x TA0.CCI0B UCA1STE P2.4/TA1.0/UCA1CLK/A7/CD11 CONTROL BITS/SIGNALS P2DIR.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 00 From module 2 10 01 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 From module 2 10 DVSS 11 P2.5/TB0.0/UCA1TXD/UCA1SIMO P2.6/TB1.0/UCA1RXD/UCA1SOMI P2SEL0.x P2SEL1.x P2IN.x Bus Keeper EN To modules D Table 47. Port P2 (P2.5 to P2.6) Pin Functions PIN NAME (P2.x) P2.5/TB0.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Port P2, P2.7, Input/Output With Schmitt Trigger Pad Logic P2REN.x P2DIR.x 00 01 10 Direction 0: Input 1: Output 11 P2OUT.x DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 P2.7 P2SEL0.x P2SEL1.x P2IN.x Bus Keeper EN To modules D Table 48. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) P2.7 (1) x 7 FUNCTION P2.7(I/O) (1) CONTROL BITS/SIGNALS P2DIR.x P2SEL1.x P2SEL0.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger Pad Logic To ADC From ADC To Comparator From Comparator CDPD.x P3REN.x P3DIR.x 00 01 10 Direction 0: Input 1: Output 11 P3OUT.x 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 P3.0/A12/CD12 P3.1/A13/CD13 P3.2/A14/CD14 P3.3/A15/CD15 P3SEL0.x P3SEL1.x P3IN.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 49. Port P3 (P3.0 to P3.3) Pin Functions PIN NAME (P3.x) P3.0/A12/CD12 x 0 FUNCTION P3.0 (I/O) A12 (1) (2) CD12 (1) (3) P3.1/A13/CD13 1 P3.1 (I/O) (1) (2) (1) (3) A13 CD13 P3.2/A14/CD14 2 P3.2 (I/O) (1) (2) (1) (3) A14 CD14 P3.3/A15/CD15 3 P3.3 (I/O) A15 (1) (2) CD15 (1) (3) (1) (2) (3) CONTROL BITS/SIGNALS P3DIR.x P3SEL1.x P3SEL0.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P3, P3.4 to P3.6, Input/Output With Schmitt Trigger Pad Logic DVSS P3REN.x P3DIR.x 00 01 10 Direction 0: Input 1: Output 11 P3OUT.x DVSS 0 DVCC 1 1 00 From module 1 01 DVSS 10 From module 2 11 P3.4/TB1.1/TB2CLK/SMCLK P3.5/TB1.2/CDOUT P3.6/TB2.1/TB1CLK P3SEL0.x P3SEL1.x P3IN.x Bus Keeper EN To modules D Table 50. Port P3 (P3.4 to P3.6) Pin Functions PIN NAME (P3.x) P3.4/TB1.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Port P3, P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 00 01 10 Direction 0: Input 1: Output 11 P3OUT.x 00 From module 1 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 P3.7/TB2.2 P3SEL0.x P3SEL1.x P3IN.x Bus Keeper EN To modules D Table 51. Port P3 (P3.7) Pin Functions PIN NAME (P3.x) P3.7/TB2.2 x 7 FUNCTION P3.7 (I/O) (1) TB2.CCI2B TB2.2 (1) (1) (1) CONTROL BITS/SIGNALS P3DIR.x P3SEL1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port P4, P4.0, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 00 01 10 Direction 0: Input 1: Output 11 P4OUT.x 00 From module 1 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 P4.0/TB2.0 P4SEL0.x P4SEL1.x P4IN.x Bus Keeper EN To modules D Table 52. Port P4 (P4.0) Pin Functions PIN NAME (P4.x) P4.0/TB2.0 x 0 FUNCTION P4.0 (I/O) (1) TB2.CCI0B TB2.0 (1) 84 (1) (1) CONTROL BITS/SIGNALS P4DIR.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Port P4, P4.1, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 00 01 10 Direction 0: Input 1: Output 11 P4OUT.x DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 P4.1 P4SEL0.x P4SEL1.x P4IN.x Bus Keeper EN To modules D Table 53. Port P4 (P4.1) Pin Functions PIN NAME (P4.x) P4.1 (1) x 1 FUNCTION P4.1 (I/O) (1) CONTROL BITS/SIGNALS P4DIR.x P4SEL1.x P4SEL0.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output To Comparator From Comparator CDPD.x Pad Logic From JTAG From JTAG From JTAG 1 PJREN.x 0 00 PJDIR.x 1 01 10 DVSS 0 DVCC 1 0 Direction 0: Input 1: Output 11 1 JTAG enable 00 PJOUT.x From module 1 01 1 DVSS 10 0 DVSS 11 PJ.0/TDO/TB0OUTH/SMCLK/CD6 PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 PJ.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Table 54. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) PJ.0/TDO/TB0OUTH/SMCLK/CD6 x 0 FUNCTION PJ.0 (I/O) TDO (2) (3) 1 2 TDI/TCLK (3) (4) 1 X 1 I: 0; O: 1 0 0 X X X 0 1 1 1 1 X PJ.2 (I/O) (2) I: 0; O: 1 0 0 (3) (4) X X X TB2OUTH 0 ACLK 1 0 1 1 PJ.3 (I/O) CD9 (4) 1 0 TCK (1) (2) (3) 0 MCLK CD8 3 0 X TB1OUTH TMS PJ.3/TCK/CD9 0 X 1 (2) PJSEL0.x X 0 PJ.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger Pad Logic To XT1 XIN PJREN.4 PJDIR.4 00 01 10 Direction 0: Input 1: Output 11 PJOUT.4 DVSS 0 DVCC 1 1 00 DVSS 01 DVSS 10 DVSS 11 PJ.4/XIN PJSEL0.4 PJSEL1.4 PJIN.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 Pad Logic To XT1 XOUT PJSEL0.4 XT1BYPASS PJREN.5 PJDIR.5 00 01 10 Direction 0: Input 1: Output 11 PJOUT.5 00 DVSS 01 DVSS 10 DVSS 11 DVSS 0 DVCC 1 1 PJ.5/XOUT PJSEL0.5 PJSEL1.5 PJIN.5 Bus Keeper EN To modules D Table 55. Port PJ (PJ.4 and PJ.5) Pin Functions CONTROL BITS/SIGNALS PIN NAME (P7.x) PJ.4/XIN x 4 FUNCTION PJ.4 (I/O) XIN crystal mode XIN bypass mode PJ.5/XOUT 5 (2) (2) PJ.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com DEVICE DESCRIPTORS (TLV) The following tables list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 56.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 (1) (continued) FR5739 FR5738 FR5737 FR5736 FR5735 Value Value Value Value Value Table 56. Device Descriptor Table REF Calibration Description Address ADC 2.5-V Reference Temp. Sensor 85°C 01A24h per unit per unit NA NA per unit 01A25h per unit per unit NA NA per unit REF Calibration Tag 01A26h 12h 12h 12h 12h 12h REF Calibration length 01A27h 06h 06h 06h 06h 06h REF 1.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.com (1) (continued) FR5734 FR5733 FR5732 FR5731 FR5730 Value Value Value Value Value Table 57. Device Descriptor Table REF Calibration Description Address ADC 1.5-V Reference Temp. Sensor 85°C 01A1Ch per unit NA NA per unit per unit 01A1Dh per unit NA NA per unit per unit ADC 2.0-V Reference Temp.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 (1) (continued) FR5729 FR5728 FR5727 FR5726 FR5725 Value Value Value Value Value Table 58.
MSP430FR573x MSP430FR572x SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 www.ti.
MSP430FR573x MSP430FR572x www.ti.com SLAS639H – JULY 2011 – REVISED SEPTEMBER 2013 REVISION HISTORY REVISION SLAS639 COMMENTS Product Preview release SLAS639A Updated Product Preview release including preliminary electrical specifications SLAS639B Changes throughout for updated Product Preview SLAS639C Production Data release SLAS639D Changed PW package options from Product Preview to Production Data. Added information for YFF package option throughout as Product Preview.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 26-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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