Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 16-Bit 8 MHz I/O number 48

MSP430FW42x

www.ti.com

SLAS383D –OCTOBER 2003–REVISED JANUARY 2011

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V • Supply Voltage Supervisor/Monitor With

Programmable Level Detection

• Ultra-Low Power Consumption:

• Bootstrap Loader in Flash Devices

– Active Mode: 200 µA at 1 MHz, 2.2 V

• Family Members Include:

– Standby Mode: 0.7 µA

– MSP430FW423:

– Off Mode (RAM Retention): 0.1 µA

8KB + 256B Flash Memory,

• Five Power-Saving Modes

256B RAM

• Wake-Up From Standby Mode in Less Than

– MSP430FW425:

6 µs

16KB + 256B Flash Memory,

• Frequency-Locked Loop, FLL+

512B RAM

• 16-Bit RISC Architecture,

– MSP430FW427:

125-ns Instruction Cycle Time

32KB + 256B Flash Memory,

• Scan IF for Background Water, Heat, and Gas

1KB RAM

Volume Measurement

– MSP430FW428:

• 16-Bit Timer_A With Three Capture/Compare

48KB + 256B Flash Memory,

Registers

2KB RAM

• 16-Bit Timer_A With Five Capture/Compare

– MSP430FW429:

Registers

60KB + 256B Flash Memory,

• Integrated LCD Driver for Up to 96 Segments 2KB RAM

• On-Chip Comparator • Available in 64-Pin Quad Flat Pack (QFP)

• Serial Onboard Programming, No External • For Complete Module Descriptions, See the

Programming Voltage Needed Programmable MSP430x4xx Family User's Guide, Literature

Code Protection by Security Fuse Number SLAU056

• Brownout Detector

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs.

The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96

LCD segment drive capability, a scan interface, and 48 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and

process the data and transmit them to a host system. The comparator and timers make the configurations ideal

for gas, heat, and water meters, industrial meters, counter applications, hand-held meters, etc.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (61 pages)

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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption: – Active Mode: 200 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 AVCC DVSS AVSS P6.2/SIFCH2 P6.1/SIFCH1 P6.0/SIFCH0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 Pin Designation 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 MSP430xW42x 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1.5/TA0CLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA0.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Functional Block Diagram XIN DVCC XOUT DVSS AVCC AVSS P1 P2 P4 P3 8 8 Port 1 Port 2 8 I/O Interrupt Capability 8 I/O Interrupt Capability P6 P5 8 8 8 8 Port 3 Port 4 Port 5 Port 6 8 I/O 8 I/O 8 I/O 8 I/O ACLK Oscillator FLL+ MCLK 8 MHz CPU incl.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Table 2. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF AFE, port 6, and LCD resistive divider circuitry; must not power up prior to DVCC. AVSS 62 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF AFE. and port 6. Must be externally connected to DVSS.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION COM0 36 O Common output. COM0-3 are used for LCD backplanes P5.2/COM1 37 I/O General-purpose digital I/O/common output. COM0-3 are used for LCD backplanes P5.3/COM2 38 I/O General-purpose digital I/O/common output. COM0-3 are used for LCD backplanes P5.4/COM3 39 I/O General-purpose digital I/O/common output.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 5.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Special Function Registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Memory Organization Table 6.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: • • • • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User's Guide (SLAU056).
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Scan Interface The scan interface is used to measure linear or rotational motion and supports LC and resistive sensors such as GMR sensors. The scan IF incorporates a VCC/2 generator, a comparator, and a 10-bit DAC and supports up to four sensors. Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Timer1_A5 Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 8. Timer1_A5 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 32 - P2.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Peripheral File Map Table 9.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Table 9.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Table 10.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Electrical Characteristics Supply Current Into AVCC + DVCC Excluding External Current ('FW423, 'FW425, and 'FW427 devices) (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TA TYP MAX 2.2 V 200 250 3V 300 350 2.2 V 57 70 3V 92 100 2.2 V 11 14 3V 17 22 -40°C 0.95 1.4 -10°C 0.8 1.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Supply Current Into AVCC + DVCC Excluding External Current ('FW428 and 'FW429 devices) (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TA TYP MAX 2.2 V 210 290 3V 320 390 2.2 V 60 75 3V 95 110 2.2 V 11 14 3V 17 22 -40°C 0.95 1.4 -10°C 0.8 1.3 0.7 1.5 60°C 1.0 1.9 85°C 1.7 2.9 -40°C 1.1 1.7 -10°C 1.0 1.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Schmitt-Trigger Inputs − Ports (P1, P2, P3, P4, P5, P6), RST/NMI, JTAG (TCK, TMS, TDI/TCLK) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT- ) MIN TYP MAX VCC = 2.2 V 1.1 1.5 VCC = 3 V 1.5 1.9 VCC = 2.2 V 0.4 0.9 VCC = 3 V 0.9 1.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Outputs − Ports (P1, P2, P3, P4, P5, P6) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH High-level output voltage VOL (1) (2) Low-level output voltage TEST CONDITIONS MIN TYP MAX IOH(max) = -1.5 mA, VCC = 2.2 V (1) IOH(max) = -6 mA, VCC = 2.2 V (2) IOH(max) = -1.5 mA, VCC = 3 V (1) IOH(max) = -6 mA, VCC = 3 V (2) VCC - 0.6 VCC IOL(max) = 1.5 mA, VCC = 2.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE 40 TA = 25°C VCC = 2.2 V P2.4 IOL − Typical Low-Level Output Current − mA IOL − Typical Low-Level Output Current − mA 25 20 TA = 85°C 15 10 5 0 0.0 nd 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 35 TA = 85°C 30 25 20 15 10 5 0 0.0 2.5 TA = 25°C VOL − Low-Level Output Voltage − V 0.5 1.0 Figure 2.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Wake-UP LPM3 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX f = 1 MHz td(LPM3) Delay time UNIT 6 f = 2 MHz VCC = 2.2 V/3 V 6 f = 3 MHz µs 6 RAM over recommended operating free-air temperature range (unless otherwise noted) PARAMETER (1) TEST CONDITIONS MIN CPU halted (1) VRAMh TYP MAX 1.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Comparator_A (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC I(CC) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.6/CA0 and P1.7/CA1 TYP MAX 2.2 V MIN 25 40 3V 45 60 2.2 V 30 50 3V 45 71 V(Ref025) Voltage @ 0.25 VCC node VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 V(RefVT) − Reference Voltage − mV VCC = 2.2 V 600 Typical 550 500 450 400 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 7. 0V 0 VCC CAF 1 CAON To Internal Modules Low Pass Filter V+ V− + _ 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2 µs Figure 8. Block Diagram of Comparator_A Module VCAOUT Overdrive V− 400 mV V+ t (response) Figure 9.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com POR/Brownout Reset (BOR) (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP td(BOR) V(B_IT-) Brownout (2) dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) Vhys(B_IT-) dVCC/dt ≤ 3 V/s (see Figure 10) t(reset) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V (1) (2) UNIT 2000 µs 0.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 VCC VCC (drop) − V 2 1.5 t pw 3V V cc = 3 V Typical Conditions 1 VCC(drop) 0.5 t f = tr 0 0.001 1 1000 tf tr t pw − Pulse Width − µs t pw − Pulse Width − µs Figure 12.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Software Sets VLD>0: SVS is Active VCC Vhys(SVS_IT−) V (SVS_IT−) V(SVSstart) Vhys(B_IT−) V(B_IT−) VCC(start) Brownout Region Brownout Brownout Region 1 0 SVS out t d(BOR) t d(BOR) SVS Circuit is Active From VLD > to V CC < V (B_IT−) 1 0 t d(SVSon) Set POR 1 t d(SVSR) Undefined 0 Figure 13. SVS Reset (SVSR) vs Supply Voltage VCC t pw 3V 2 Rectangular Drop VCC(drop) − V 1.5 VCC(drop) Triangular Drop 1 1 ns 0.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 DCO over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2; DCOPLUS = 0, fCrystal = 32.
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MSP430FW42x Sn - Stepsize Ratio between DCO T aps SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com 1.17 Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 16.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Crystal Oscillator, LFXT1 Oscillator (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN OSCCAPx = 0h CXIN CXOUT Integrated input capacitance (3) Integrated output capacitance (3) OSCCAPx = 1h OSCCAPx = 2h 10 2.2 V/3 V 18 OSCCAPx = 0h 0 OSCCAPx = 2h VIH (1) (2) (3) (4) Input levels at XIN (4) UNIT pF 14 OSCCAPx = 3h OSCCAPx = 1h MAX 0 10 2.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Scan IF, Port Drive, Port Timing over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOL(SIFCHx) Voltage drop due to excitation transistor's on-resistance (see Figure 18) I(SIFCHx) = 2 mA, SIFTEN = 1 3V 0.3 V VOH(SIFCHx) Voltage drop due to damping transistor’s on-resistance (1) (see Figure 18) I(SIFCHx) = -200 µA, SIFTEN = 1 3V 0.1 V 0 0.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Scan IF, Sample Capacitor/Ri Timing (1) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CSHC(SIFCHx) Sample capacitance at SIFCHx pin SIFEx(tsm) = 1, SIFSH = 1 Ri(SIFCHx) Serial input resistance at the SIFCHx pin SIFEx(tsm) = 1, SIFSH = 1 tHold Maximum hold time (2) ΔVsample < 3 mV (1) (2) VCC MIN TYP MAX 2.2 V/3 V 5 7 pF 2.2 V/3 V 1.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Scan IF, 10-bit DAC over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS AVCC Analog supply voltage AVCC = DVCC (connected together) AVSS = DVSS (connected together) AICC Scan IF 10-bit DAC operating supply current into AVCC terminal CL at SIFCOM pin = 470 nF ±20%, frefresh(SIFCOM) = 32768 Hz VCC MIN 2.2 MAX 3.6 2.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Scan IF, SIFCLK Oscillator over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC = DVCC (connected together), AVSS = DVSS (connected together) MIN TYP 2.2 MAX 3.6 UNIT AVCC Analog supply voltage AICC Scan IF oscillator operating supply current into AVCC terminal fSIFCLKG = 0 Scan IF oscillator at minimum setting TA = 25ºC, SIFCLKFQ = 0000 SIFNOM = 0 1.8 3.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 JTAG Interface over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fTCK TCK input frequency (1) RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK (2) (1) (2) MAX UNIT 2.2 V VCC MIN 0 TYP 5 MHz 3V 0 10 MHz 2.2 V/3 V 25 60 90 kΩ MIN TYP MAX fTCK may be restricted to meet the timing requirements of the module selected.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger Pad Logic CAPD.x P1SEL.x 0: Input 1: Output 0 P1DIR.x Direction Control From Module P1OUT.x 1 0 1 Module X OUT Bus keeper P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 P1.5/TA0CLK/ACLK P1IN.x EN D Module X IN P1IE.x P1IRQ.x P1IFG.x EN Q Interrupt Edge Select Set P1IES.x P1SEL.x NOTE: 0 ≤ x ≤ 5.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Port P1, P1.6, P1.7 Input/Output With Schmitt Trigger Pad Logic Note: Port Function Is Active if CAPD.6 = 0 CAPD.6 P1SEL.6 0: Input 1: Output 0 P1DIR.6 1 P1DIR.6 P1.6/ CA0 0 P1OUT.6 1 DVSS Bus Keeper P1IN.6 EN D unused P1IE.7 P1IRQ.07 EN Interrupt Edge Select Q P1IFG.7 Set P1IES.x P1SEL.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger P2.0, P2.1 LCDM.5 LCDM.6 P2.2 to P2.5 LCDM.7 P2.6, P2.7 0: Port Active 1: Segment xx Function Active Pad Logic Segment xx P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module P2OUT.x 1 0 P2.x 1 Module X OUT Bus keeper P2.0/TA0.2 P2.1/TA1.1 P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21 P2.5/TA1CLK/S20 P2.6/CAOUT/S19 P2.7/SIFCLKG/S18 P2IN.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger LCDM.5 P3.2 to P3.7 LCDM.6 LCDM.7 P3.0, P3.1 0: Port Active 1: Segment xx Function Active Pad Logic Segment xx P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module P3OUT.x 1 0 1 Module X OUT P3.x Bus keeper P3.0/S17 P3.1/S16 P3.2/S15 P3.3/S14 P3.4/S13 P3.5/S12 P3.6/S11 P3.7/S10 P3IN.x EN D Module X IN NOTE: 0 ≤ x ≤ 7 PnSEL.x PnDIR.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger LCDM.5 LCDM.6 LCDM.7 0: Port Active 1: Segment xx Function Active Pad Logic Segment xx P4SEL.x 0: Input 1: Output 0 P4DIR.x Direction Control From Module P4OUT.x 1 0 P4.x 1 Module X OUT Bus keeper P4.0/S9 P4.1/S8 P4.2/S7 P4.3/S6 P4.4/S5 P4.5/S4 P4.6/S3 P4.7/S2 P4IN.x EN D Module X IN NOTE: 0 ≤ x ≤ 7 44 PnSEL.x PnDIR.x Direction Control From Module PnOUT.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Port P5, P5.0, P5.1, Input/Output With Schmitt Trigger LCDM.5 0: Port Active 1: Segment Function Active LCDM.6 LCDM.7 Pad Logic Segment xx or COMx or Rxx P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module P5OUT.x 1 0 1 Module X OUT P5.x Bus keeper P5.0/S1 P5.1/S0 P5IN.x EN D Module X IN NOTE: x = 0, 1 PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger 0: Port Active 1: COMx Function Active Pad Logic COMx P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module P5OUT.x Module X OUT 1 0 P5.x 1 Bus keeper P5.2/COM1 P5.3/COM2 P5.4/COM3 P5IN.x EN D Module X IN NOTE: 2 ≤ x ≤ 4 46 PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN COMx P5SEL.2 P5DIR.2 P5DIR.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger 0: Port Active 1: Rxx Function Active Pad Logic Rxx P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module P5OUT.x Module X OUT 1 0 P5.x 1 Bus keeper P5.5/R13 P5.6/R23 P5.7/R33 P5IN.x EN D Module X IN NOTE: 5 ≤ x ≤ 7 PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN Rxx P5SEL.5 P5DIR.5 P5DIR.5 P5OUT.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Port P6, P6.0, P6.1, P6.2, P6.4, P6.5, Input/Output With Schmitt Trigger P6SEL.x 0 P6DIR.x Direction Control From Module 0: Input 1: Output 1 Pad Logic 0 P6OUT.x Module X OUT P6.X 1 P6.0/SIFCH0 P6.1/SIFCH1 P6.2/SIFCH2 P6.4/SIFCI0 P6.5/SIFCI1 Bus Keeper P6IN.x EN Module X IN D To/From Scan I/F P6SEL.x must be set if the corresponding pins are used by the Scan IF .
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 NOTE The signal at pins P6.x/SIFCHx and P6.x/SIFCIx are shared by Port P6 and the Scan IF module. P6SEL.x must be set if the corresponding pins are used by the Scan IF. Port P6, P6.3 Input/Output With Schmitt Trigger P6SEL.3 0 P6DIR.3 1 0: Input 1: Output Pad Logic 0 P6OUT.x SIFCAOUT P6.3/SIFCH3/SIFCAOUT 1 Bus Keeper P6IN.3 EN Module X IN D To/From Scan I/F P6SEL.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Port P6, P6.6 Input/Output With Schmitt Trigger P6SEL.6 0 P6DIR.6 0: Input 1: Output 1 Pad Logic 0 P6OUT.6 DVss P6.6/SIFCI2/DACOUT 1 Bus Keeper P6IN.6 EN Module X IN D 1 From Scan I/F DAC To Scan I/F comparator input mux P6SEL.x must be set if the corresponding pins are used by the Scan IF . NOTE Analog signals applied to digital gates can cause current flow from the positive to the negative terminal.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 Port P6, P6.7 Input/Output With Schmitt Trigger SVS VLDx=15 P6SEL.7 P6DIR.7 0 0: Input 1: Output 1 Pad Logic 0 P6OUT.7 DVss P6.7/SIFCI3/SVSIN 1 Bus Keeper P6IN.7 EN Module X IN D SVS VLDx=15 1 To SVS To Scan I/F comparator (+) terminal P6SEL.x must be set if the corresponding pins are used by the Scan IF . NOTE Analog signals applied to digital gates can cause current flow from the positive to the negative terminal.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.
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MSP430FW42x www.ti.com SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 JTAG Fuse Check Mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF)) of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
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MSP430FW42x SLAS383D – OCTOBER 2003 – REVISED JANUARY 2011 www.ti.com Table 11.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 29-Nov-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430FW423IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430FW423IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430FW425IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430FW423IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430FW423IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430FW425IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430FW427IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430FW428IPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430FW429IPMR LQFP PM 64 1000 336.6 336.6 41.
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MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.