Datasheet

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MSP430G22x0

www.ti.com

SLAS753E –JANUARY 2012–REVISED FEBRUARY 2013

MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V

(A/D) Conversion (MSP430G2210 Only)

• Ultra-Low Power Consumption • 10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference, Sample-

– Active Mode: 220 µA at 1 MHz, 2.2 V

and-Hold, and Autoscan (MSP430G2230 Only)

– Standby Mode: 0.5 µA

• Universal Serial Interface (USI) Supports SPI

– Off Mode (RAM Retention): 0.1 µA

and I2C (MSP430G2230 Only)

• Five Power-Saving Modes

• Brownout Detector

• Ultra-Fast Wake-Up From Standby Mode in

• Serial Onboard Programming, No External

Less Than 1 µs

Programming Voltage Needed, Programmable

• 16-Bit RISC Architecture, 62.5-ns Instruction

Code Protection by Security Fuse

Cycle Time

• On-Chip Emulation Logic With Spy-Bi-Wire

• Basic Clock Module Configurations

Interface

– Internal Frequencies up to 16 MHz With

• Family Members:

Four Calibrated Frequencies to ±1%

– MSP430G22x0

– Internal Very-Low-Power Low-Frequency

– 2KB + 256B Flash Memory

Oscillator

– 128B RAM

• 16-Bit Timer_A With Two Capture/Compare

• Available in 8-Pin Plastic Packages (D)

Registers

• For Complete Module Descriptions, See the

• On-Chip Comparator for Analog Signal

MSP430x2xx Family User's Guide (SLAU144)

Compare Function or Slope Analog-to-Digital

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G22x0 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and four

I/O pins. In addition, the MSP430G2230 has a built-in communication capability using synchronous protocols

(SPI or I2C) and a 10-bit A/D converter. The MSP430G2210 has a versatile analog comparator.

Table 1. Available Options

(1)

PACKAGED DEVICES

(2)

PLASTIC 8-PIN (D)

MSP430G2230ID

-40°C to 85°C

MSP430G2210ID

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at

www.ti.com/packaging

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 23 • • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Device Pinout and Functional Block Diagram, MSP430G2210 See Application Information for detailed I/O information. D PACKAGE (TOP VIEW) DVSS DVCC 1 P1.2/TA0.1/CA2 2 8 7 P1.5/TA0.0/CA5 P1.6/TA0.1/CA6 3 6 TEST/SBWTCK RST/NMI/SBWTDIO 4 5 P1.7/CAOUT/CA7 Figure 1. Device Pinout, MSP430G2210 VCC P1.2, P1.5, P1.6, P1.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Device Pinout and Functional Block Diagram, MSP430G2230 See Application Information for detailed I/O information. D PACKAGE (TOP VIEW) DVSS DVCC 1 P1.2/TA0.1/A2 2 8 7 P1.5/TA0.0/A5/SCLK P1.6/TA0.1/A6/SDO/SCL 3 6 TEST/SBWTCK RST/NMI/SBWTDIO 4 5 P1.7/A7/SDI/SDA Figure 3. Device Pinout, MSP430G2230 VCC P1.2, P1.5, P1.6, P1.7 4 VSS XOUT XIN Basic Clock System+ ACLK SMCLK Flash RAM 2kB 128B MCLK 16MHz CPU incl.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Table 2. Terminal Functions, MSP430G2210 (1) TERMINAL NAME NO. D DESCRIPTION I/O P1.2/ TA0.1/ CA2 2 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare Out1 output Comparator_A+, CA2 input P1.5/ TA0.0/ CA5 3 I/O General-purpose digital I/O pin Timer_A, compare Out0 output Comparator_A+, CA5 input P1.6/ TA0.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Table 3. Terminal Functions, MSP430G2230 (1) TERMINAL NAME P1.2/ TA0.1/ A2 P1.5/ TA0.0/ A5/ SCLK P1.6/ TA0.1/ A6/ SDO/ SCL NO.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0x0FFFF to 0x0FFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0x0FFFE) contains 0x0FFFF (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 6.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Memory Organization Table 9.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Watchdog Timer (WDT+) The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 USI (MSP430G2230 Only) The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C. ADC10 (MSP430G2230 Only) The ADC10 module supports fast 10-bit analog-to-digital conversions.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature (3) Tstg (1) ±2 mA Unprogrammed device -55°C to 150°C Programmed device -40°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
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MSP430G22x0 www.ti.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TA VCC Low-power mode 0 (LPM0) current (2) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32,768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Typical Characteristics – Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P1.7 TA = 25°C 25.0 TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 POR and BOR (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP VCC(start) See Figure 12 dVCC/dt ≤ 3 V/s 0.7 × V(B_IT–) V(B_IT–) See Figure 12 through Figure 14 dVCC/dt ≤ 3 V/s 1.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Typical Characteristics – POR and BOR VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns 1 ns t pw − Pulse Width − µs t pw − Pulse Width − µs Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V -3 ±0.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Wake-Up From Lower-Power Modes (LPM3, LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 DCO clock wake-up time from LPM3 or LPM4 (1) BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ (1) (2) UNIT 2 2.2 V, 3 V 1.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC MIN 4 fVLO VLO frequency -40°C to 85°C 3V dfVLO/dT VLO frequency temperature drift (1) -40°C to 85°C 3V dfVLO/dVCC VLO frequency supply voltage drift (2) 25°C 1.8 V to 3.6 V (1) (2) TYP MAX 12 20 UNIT kHz 0.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Comparator_A+ (MSP430G2210 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (1) I(DD) I(Refladder/ RefDiode) TEST CONDITIONS VCC MIN TYP MAX UNIT CAON = 1, CARSEL = 0, CAREF = 0 3V 45 µA CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at CA0 and CA1 3V 45 µA V(IC) Common–mode input voltage CAON = 1 3V V(Ref025) (Voltage at 0.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Typical Characteristics – Comparator_A+ (MSP430G2210 Only) 650 650 VCC = 2.2 V 600 V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 95 600 Typical 550 500 450 400 −45 115 TA − Free-Air Temperature − °C Figure 18. V(RefVT) vs Temperature, VCC = 3 V −25 −5 15 35 55 75 95 115 TA − Free-Air Temperature − °C Figure 19.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 10-Bit ADC, External Reference (MSP430G2230 Only) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VEREF+ TEST CONDITIONS Positive external reference input voltage range (2) 1.4 3 0 1.2 V 1.4 VCC V Differential external reference input voltage range, ΔVEREF = VEREF+ – VEREF– VEREF+ > VEREF– (1) (2) (3) (4) (5) UNIT VEREF– ≤ VEREF+ ≤ VCC – 0.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2230 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR Temperature sensor supply current (1) TCSENSOR TEST CONDITIONS VCC REFON = 0, INCHx = 0Ah, TA = 25°C ADC10ON = 1, INCHx = 0Ah (2) 60 3V 3.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V, 3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V, 3.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com APPLICATION INFORMATION Port (P1.2 and P1.5) Pin Schematics - MSP430G2210 To Comparator from Comparator CAPD.y PxDIR.y 0 1 Direction 0: Input 1: Output PxREN.y DVSS DVCC PxSEL.y PxOUT.y From Module 0 1 1 0 1 Bus Keeper EN P1.2/TA0.1/CA2 P1.5/TA0.0/CA5 PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Figure 21. Table 15. Port P1 (P1.2 to P1.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2210 To Comparator From Comparator CAPD.y PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y From Module DVSS 0 DV CC 1 1 0 1 P1.6/TA0.1/CA6 PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Figure 22.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com To Comparator From Comparator CAPD.y PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y DVSS 0 DV CC 1 1 0 1 From Module P1.7/CAOUT/CA7 PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Figure 23. Table 16. Port P1 (P1.6 and P1.7) Pin Functions - MSP430G2210 PIN NAME (P1.x) x P1.6/ FUNCTION P1.x (I/O) TA0.1/ 6 TA0.1 CA6 CA6 P1.7/ P1.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Port P1 (P1.2 ) Pin Schematics - MSP430G2230 To ADC10 INCHx = y ADC10AE.y PxDIR.y 0 1 Direction 0: Input 1: Output PxREN.y DVSS DVCC PxSEL.y PxOUT.y 0 1 1 0 1 From Module Bus Keeper EN P1.2/TA0.1/A2 PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Figure 24. Table 17. Port P1 (P1.2) Pin Functions - MSP430G2230 CONTROL BITS AND SIGNALS (1) PIN NAME (P1.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Port P1 (P1.5 ) Pin Schematics - MSP430G2230 To ADC10 INCHx = y ADC10AE.y PxDIR.y USI Module Direction 0 1 Direction 0: Input 1: Output USIPE5 PxREN.y PxSEL.y DVSS DVCC PxOUT.y From Module 0 1 1 0 1 Bus Keeper EN P1.5/TA0.0/SCLK/A5 PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Figure 25. Table 18. Port P1 (P1.5) Pin Functions - MSP430G2230 PIN NAME (P1.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2230 To ADC10 INCHx ADC10AE0.y PxDIR.y from USI USIPE6 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y or USIP E6 PxOUT.y From USI DVSS 0 DV CC 1 1 0 1 Bus Keeper EN P1.6/TA0.1/SDO/SCL/A6 PxSEL.y PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select USI in I2C mode: Output driver drives low level only. Figure 26.
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MSP430G22x0 SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 www.ti.com To ADC10 INCHx ADC10AE0.y USIPE7 PxDIR.y 1 Direction 0: Input 1: Output 0 from USI PxSEL.y PxREN.y PxSEL.y or USIPE7 PxOUT.y 0 From USI 1 DVSS 0 DVCC 1 1 Bus Keeper EN P1.7/SDI/SDA/A7 PxSEL.y PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y USI in I2C mode: Output driver drives low level only. Figure 27. Table 19. Port P1 (P1.6 and P1.
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MSP430G22x0 www.ti.com SLAS753E – JANUARY 2012 – REVISED FEBRUARY 2013 REVISION HISTORY Literature Number Comments SLAS753 Production Data release SLAS753A Changed Table 11. Added Table 12. SLAS753B Corrected "Basic Clock Module Configurations" list in Features. Added note to TCREF+ in 10-Bit ADC, Built-In Voltage Reference (MSP430G2230 Only). SLAS753C Added Flash Memory. SLAS753D Table 15, Removed ADC10AE.x column and removed A2 and A5 rows (no ADC on this device). Table 18, Added USIP.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.