MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 23 • • • • • Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 1.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 DEVICE PINOUTS PW PACKAGE (TOP VIEW) DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/A1 P1.2/TA0.1/A2 P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK P1.5/TA0.0/SCLK/A5/TMS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/SDI/SDA/A7/TDO/TDI P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK NOTE: ADC10 pin functions are available only on MSP430G2x32.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAMS Functional Block Diagram, MSP430G2x32 XIN XOUT DVCC DVSS P1.x P2.x up to 8 8 ACLK Clock System Flash RAM ADC 8KB 4KB 2KB 1KB 256B 256B 256B 128B 10-Bit 8 Ch. Autoscan 1 ch DMA SMCLK MCLK 16MHz CPU MAB incl.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 TERMINAL FUNCTIONS Table 2. Terminal Functions TERMINAL NO. NAME N14, PW14 RSA1 6 I/O DESCRIPTION N20, PW20 P1.0/ General-purpose digital I/O pin TA0CLK/ 2 ACLK/ 1 2 I/O Timer0_A, clock signal TACLK input ACLK signal output ADC10 analog input A0 (1) A0 P1.1/ General-purpose digital I/O pin TA0.0/ 3 2 3 I/O Timer0_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1 (1) A1 P1.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME I/O DESCRIPTION N14, PW14 RSA1 6 N20, PW20 P2.4 - - 12 I/O General-purpose digital I/O pin P2.5 - - 13 I/O General-purpose digital I/O pin 13 12 19 I/O XIN/ Input terminal of crystal oscillator P2.6/ TA0.1 General-purpose digital I/O pin Timer0_A, compare: Out1 output XOUT/ 12 P2.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 SHORT-FORM DESCRIPTION CPU The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Operating Modes The MSP430 devices have one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 5.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Memory Organization Table 8.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Main DCO Characteristics • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. • DCO control bits DCOx have a step size as defined by parameter SDCO. • Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 11.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Peripheral File Map Table 12.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 13.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Absolute Maximum Ratings (1) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (2) –0.3 V to VCC + 0.3 V Diode current at any device pin Storage temperature range, Tstg (1) ±2 mA (3) Unprogrammed device –55°C to 150°C Programmed device –55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TA VCC Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Schmitt-Trigger Inputs – Ports Px (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) MIN RPull Pullup/pulldown resistor CI Input capacitance VIN = VSS or VCC TYP MAX 0.45 VCC 0.75 VCC 1.35 2.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Typical Characteristics – Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE 50.0 VCC = 2.2 V P1.7 TA = 25°C 25.0 TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Pin-Oscillator Frequency – Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER foP1.x Port output oscillation frequency foP2.x Port output oscillation frequency foP2.6/7 Port output oscillation frequency (1) (2) TEST CONDITIONS P1.y, CL = 10 pF, RL = 100 kΩ VCC MIN (1) (2) 3V P1.y, CL = 20 pF, RL = 100 kΩ (1) (2) P2.0 to P2.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 POR, BOR (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 12 dVCC/dt ≤ 3 V/s V(B_IT–) See Figure 12 through Figure 14 dVCC/dt ≤ 3 V/s 1.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Typical Characteristics – POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns 1 ns t pw − Pulse Width − µs t pw − Pulse Width − µs Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V RSELx = 14 2.2 3.6 V RSELx = 15 3 3.6 V 0.14 MHz 0.17 MHz fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3V 0.06 fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3V 0.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Calibrated DCO Frequencies – Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature (1) BCSCTL1= CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V -3 ±0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Wake-Up From Lower-Power Modes (LPM3. LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tDCO,LPM3/4 DCO clock wake-up time from LPM3 or LPM4 (1) tCPU,LPM3/4 CPU wake-up time from LPM3 or LPM4 (2) (1) (2) VCC BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ MIN 3V TYP MAX 1.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 USI, Universal Serial Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fUSI USI module clock frequency External: SCLK, Duty cycle = 50% ± 10% f(SCLK) Serial clock frequency, slave mode SPI slave mode Low-level output voltage on SDA and SCL USI module in I2C mode, I(OLmax) = 1.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.
MSP430G2x32 MSP430G2x02 www.ti.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com 10-Bit ADC, External Reference (1) (MSP430G2x32 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VEREF+ TEST CONDITIONS Positive external reference input voltage range (2) 1.4 3 0 1.2 V 1.4 VCC V Differential external reference input voltage range, ΔVEREF = VEREF+ – VEREF– VEREF+ > VEREF– (1) (2) (3) (4) (5) UNIT VEREF– ≤ VEREF+ ≤ VCC – 0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x32 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR Temperature sensor supply current (1) TCSENSOR TEST CONDITIONS VCC REFON = 0, INCHx = 0Ah, TA = 25°C ADC10ON = 1, INCHx = 0Ah (2) 60 3V 3.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX 1.6 UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 PIN SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 1 0 Direction 0: Input 1: Output 2 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y PxOUT.y DVSS DVCC 0 1 1 0 From Module 1 0 3 2 Bus Keeper EN P1.0/TA0CLK/ACLK/A0* P1.1/TA0.0/A1* P1.2/TA0.1/A2* TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 14. Port P1 (P1.0 to P1.2) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.y=1) (2) P1.0/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0CLK/ TA0.TACLK 0 1 0 0 ACLK 1 1 0 0 A0 (2)/ A0 X X X 1 (y = 0) Pin Osc Capacitive sensing P1.1/ P1.x (I/O) TA0.0/ ACLK/ 0 x 0 1 0 I: 0; O: 1 0 0 0 TA0.0 1 1 0 0 TA0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger SREF2 * VSS 0 1 To ADC10 VREF- * To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0,2,3 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y PxOUT.y From ADC10 * 0 1 DVSS DVCC 0 1 1 0 1 2 Bus Keeper EN 3 P1.3/ADC10CLK*/A3*/ VREF-*/VEREF-* TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 15. Port P1 (P1.3) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x=1) (2) 0 P1.3/ P1.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger From/To ADC10 Ref+ * To ADC10 * INCHx = y * ADC10AE0.y * PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y PxOUT.y SMCLK 0 1 from Timer 2 3 0 1 DVSS 0 DVCC 1 Bus Keeper EN 1 P1.4/SMCLK/TA0.2/A4*/ VREF+*/VEREF+*/TCK TAx.y TAxCLK PxIN.y EN To Module D PxIE.y EN Q Set PxIRQ.y PxIFG.y PxSEL.y PxIES.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 16. Port P1 (P1.4) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x=1) (2) JTAG Mode P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0 0 SMCLK/ SMCLK 1 1 0 0 0 TA0.2/ TA0.2 1 1 1 0 0 TA0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Module 1 Direction 0: Input 1: Output 2 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y PxOUT.y DVSS DVCC 0 1 1 0 From Module 1 0 3 2 Bus Keeper EN P1.5/TA0.0/SCLK/A5*/TMS P1.6/TA0.1/SDO/SCL/A6*/TDI/TCLK P1.7//SDI/SDA/A7*/TDO/TDI TAx.y TAxCLK PxIN.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 17. Port P1 (P1.5 to P1.7) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x USIP.x JTAG Mode ADC10AE.x (INCH.x=1) (2) I: 0; O: 1 0 0 0 0 0 1 1 0 0 0 0 from USI 1 0 1 0 0 A5 X X X 0 0 1 (y = 5) TMS/ TMS X X X 0 1 0 Pin Osc Capacitive sensing X 0 1 0 0 0 P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0 0 0 TA0.1/ TA0.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y PxOUT.y 0 1 DVSS 0 DVCC 1 1 0 1 2 0 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Table 18. Port P2 (P2.0 to P2.5) Pin Functions PIN NAME (P2.x) P2.0/ Pin Osc P2.1/ Pin Osc P2.2/ Pin Osc P2.3/ Pin Osc P2.4/ Pin Osc P2.5/ Pin Osc (1) 44 x 0 1 2 3 4 5 FUNCTION P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing P2.x (I/O) Capacitive sensing CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x P2SEL2.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger XOUT/P2.7 LF off PxSEL.6 & PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y PxOUT.y From Module DVSS DVCC 0 1 1 0 1 2 0 XIN/P2.6/TA0.1 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.
MSP430G2x32 MSP430G2x02 SLAS723H – DECEMBER 2010 – REVISED MAY 2013 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger XIN/P2.6/TA0.1 LF off PxSEL.6 & PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK from P2.6 PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 1 1 0 1 From Module 2 XOUT/P2.7 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.
MSP430G2x32 MSP430G2x02 www.ti.com SLAS723H – DECEMBER 2010 – REVISED MAY 2013 REVISION HISTORY REVISION SLAS723 (1) DESCRIPTION Initial release SLAS723A Page 1, Changed Internal Frequencies up to 16 MHz With One Calibrated Frequency to Four Calibrated Frequencies SLAS723B Added note concerning pulldown resistor to PW14 and RSA16 pinout drawings. Removed reference to CAOUT from N20, PW20 pinout drawing and Table 11 (there is no comparator module on this device).
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
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