MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • Low Supply-Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 230 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 1.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Device Pinout, MSP430G2x03 and MSP430G2x33, 20-Pin Devices, TSSOP and PDIP DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2 P1.3/ADC10CLK/VREF-/VEREF-/A3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 1 20 2 19 3 18 4 5 6 17 N20 PW20 (TOP VIEW) 16 15 7 14 8 13 9 12 10 11 DVSS XIN/P2.6/TA0.1 XOUT/P2.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com NC P1.0/TA0CLK/ACLK/A0/CA0 DVCC AVCC DVSS AVSS XIN/P2.6/TA0.1 XOUT/P2.7 Device Pinout, MSP430G2x03 and MSP430G2x33, 32-Pin Devices, QFN 32 31 30 29 28 27 26 25 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2 P1.3/ADC10CLK/VREF-/VEREF-/A3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS P3.1/TA1.0 P3.0/TA0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Functional Block Diagram, MSP430G2x33 XIN XOUT DVCC DVSS P1.x 8 P2.x 8 P3.x 8 Port P1 Port P2 Port P3 8 I/O Interrupt capability pullup/down resistors 8 I/O Interrupt capability pullup/down resistors 8 I/O ACLK Clock System Flash SMCLK 16KB 8KB 4KB 2KB MCLK 16MHz CPU incl. 16 Registers ADC RAM 512B 256B 10-Bit 8 Ch.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME PW20, N20 PW28 I/O DESCRIPTION RHB32 P1.0/ General-purpose digital I/O pin TA0CLK/ ACLK/ 2 2 31 I/O Timer0_A, clock signal TACLK input ACLK signal output A0 ADC10 analog input A0 (1) P1.1/ General-purpose digital I/O pin TA0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Table 2. Terminal Functions (continued) TERMINAL NO. NAME P2.0/ TA1.0 P2.1/ TA1.1 P2.2/ TA1.1 P2.3/ TA1.0 P2.4/ TA1.2 P2.5/ TA1.2 I/O PW20, N20 PW28 RHB32 8 10 9 I/O 9 11 10 I/O 10 12 11 I/O 11 16 15 I/O 12 17 16 I/O 13 18 17 I/O 19 27 26 I/O XIN/ P2.6/ P2.7 P3.0/ TA0.2 P3.1/ TA1.0 P3.2/ TA1.1 P3.3/ TA1.2 P3.4/ TA0.0 P3.5/ TA0.1 P3.6/ TA0.2 P3.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME QFN Pad 8 I/O PW20, N20 PW28 RHB32 NA NA Pad Submit Documentation Feedback NA DESCRIPTION QFN package pad connection to VSS recommended.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Operating Modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power-up. Table 5.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Memory Organization Table 8.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Digital I/O Up to three 8-bit I/O ports are implemented: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible. • Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available). • Read/write access to port-control registers is supported by all instructions.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 13. Timer1_A3 Signal Connections INPUT PIN NUMBER PW20, N20 PW28 RHB32 DEVICE INPUT SIGNAL - P3.7-21 P3.7-20 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER PW20, N20 PW28 RHB32 - P3.7-21 P3.7-20 TACLK INCLK P2.0-8 P2.0-10 P2.0-9 TA1.0 CCI0A P2.0-8 P2.0-10 P2.0-9 P2.3-11 P2.3-16 P2.3-12 TA1.0 CCI0B P2.3-11 P2.3-16 P2.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Peripheral File Map Table 14.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 15.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Absolute Maximum Ratings (1) Voltage applied at VCC to VSS –0.3 V to 4.1 V Voltage applied to any pin (2) –0.3 V to VCC + 0.3 V Diode current at any device pin Storage temperature range, Tstg (1) ±2 mA (3) Unprogrammed device –55°C to 150°C Programmed device –55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TA VCC Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Schmitt-Trigger Inputs, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) VCC MIN RPull Pullup/pulldown resistor CI Input capacitance VIN = VSS or VCC MAX 0.45 VCC 0.75 VCC 1.35 2.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Typical Characteristics, Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 VCC = 2.2 V P1.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Pin-Oscillator Frequency – Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS foP1.x Port output oscillation frequency foP2.x Port output oscillation frequency foP2.6/7 Port output oscillation frequency foP3.x (1) (2) Port output oscillation frequency P1.y, CL = 10 pF, RL = 100 kΩ VCC MIN (1) (2) 3V P1.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 POR, BOR (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 12 dVCC/dt ≤ 3 V/s 0.7 × V(B_IT--) V(B_IT–) See Figure 12 through Figure 14 dVCC/dt ≤ 3 V/s 1.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Typical Characteristics, POR and BOR VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns 1 ns t pw − Pulse Width − µs t pw − Pulse Width − µs Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Calibrated DCO Frequencies, Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V -3 ±0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Wake-Up From Lower-Power Modes (LPM3, LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tDCO,LPM3/4 DCO clock wake-up time from LPM3 or LPM4 (1) tCPU,LPM3/4 CPU wake-up time from LPM3 or LPM4 (2) (1) (2) VCC BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz MIN 3V TYP MAX UNIT 1.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.
MSP430G2x33 MSP430G2x03 www.ti.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency VCC MIN 3V 0 TYP SMCLK, duty cycle = 50% ± 10% fSCL ≤ 100 kHz MAX UNIT fSYSTEM MHz 400 kHz 4.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.
MSP430G2x33 MSP430G2x03 www.ti.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com 10-Bit ADC, External Reference (1) (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VEREF+ TEST CONDITIONS Positive external reference input voltage range (2) 1.4 3 0 1.2 V 1.4 VCC V Differential external reference input voltage range, ΔVEREF = VEREF+ – VEREF– VEREF+ > VEREF– (1) (2) (3) (4) (5) UNIT VEREF– ≤ VEREF+ ≤ VCC – 0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR TEST CONDITIONS Temperature sensor supply current (1) TCSENSOR VCC REFON = 0, INCHx = 0Ah, TA = 25°C ADC10ON = 1, INCHx = 0Ah (2) 60 3V 3.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX 1.6 UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 PORT SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Timer 1 1 2 Direction 0: Input 1: Output 3 From USCI PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Timer 1 0 3 0 1 2 Bus Keeper EN TAx.y TAxCLK 1 P1.0/TA0CLK/ ACLK/A0* P1.1/TA0.0/ UCA0RXD/UCA0SOMI/A1* P1.2/TA0.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 16. Port P1 (P1.0 to P1.2) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.y = 1) (2) P1.0/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0CLK/ TA0.TACLK 0 1 0 0 ACLK 1 1 0 0 A0 / A0 X X X 1 (y = 0) Pin Osc Capacitive sensing X 0 1 0 P1.1/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0.0/ TA0.0 1 1 0 0 TA0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger SREF2 * To ADC10 VREF- * VSS 0 1 To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0,2,3 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y PxOUT.y From ADC10 * DVSS DVCC 0 1 1 0 1 2 Bus Keeper EN 3 P1.3/ADC10CLK*/ A3*/VREF-*/VEREF-* TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q PxIFG.y PxSEL.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 17. Port P1 (P1.3) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) 0 P1.3/ P1.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger From/To ADC10 Ref+ * To ADC10 * INCHx = y * ADC10AE0.y * PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y 0 1 DVSS 0 1 DVCC PxOUT.y SMCLK 0 1 from Module 2 3 Bus Keeper EN 1 P1.4/SMCLK/UCB0STE/UCA0CLK/ VREF+/VEREF+/A4/TCK TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 18. Port P1 (P1.4) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) JTAG Mode I: 0; O: 1 0 0 0 0 1 1 0 0 0 P1.4/ P1.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Module 1 Direction 0: Input 1: Output 2 From Module 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y 0 1 DVSS DVCC PxOUT.y 0 From Module 1 From Module 3 0 1 1 2 Bus Keeper EN TAx.y TAxCLK P1.5/TA0.0/UCB0CLK/ UCA0STE/A5*/TMS P1.6/TA0.1/UCB0SOMI/ UCB0SCL/A6*/TDI/TCLK P1.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 19. Port P1 (P1.5 to P1.7) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) JTAG Mode I: 0; O: 1 0 0 0 0 1 1 0 0 0 UCB0CLK from USCI 1 1 0 0 UCA0STE from USCI 1 1 0 0 x FUNCTION P1.5/ P1.x (I/O) TA0.0/ TA0.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y PxOUT.y 0 From Timer 1 1 DVSS 0 DVCC 1 1 2 0 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P2.3/TA1.0 P2.4/TA1.2 P2.5/TA1.2 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 20. Port P2 (P2.0 to P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x P2SEL2.x P2.0/ P2.x (I/O) I: 0; O: 1 0 0 TA1.0/ Timer1_A3.CCI0A 0 1 0 Timer1_A3.TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.1/ P2.x (I/O) I: 0; O: 1 0 0 TA1.1/ Timer1_A3.CCI1A 0 1 0 Timer1_A3.TA1 1 1 0 0 1 Pin Osc Capacitive sensing P2.2/ P2.x (I/O) TA1.1/ Timer1_A3.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger XOUT/P2.7 LF off PxSEL.6, PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Module 1 0 1 1 2 XIN/P2.6/TA0.1 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 21. Port P2 (P2.6) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x FUNCTION XIN XIN P2.6 P2.x (I/O) P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.7 0 1 1 0 0 I: 0; O: 1 0 X 0 0 6 TA0.1 Timer0_A3.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger XIN LF off PxSEL.6, PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK from P2.6 PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Module 1 0 1 1 2 XOUT/P2.7 3 TAx.y TAxCLK PxIN.y EN D To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 22. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x XOUT/ XOUT P2.7/ 7 Pin Osc (1) 52 FUNCTION P2.x (I/O) Capacitive sensing P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB Package Only) PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y PxOUT.y From Module 0 1 DVSS DVCC 0 1 1 0 1 2 P3.0/TA0.2 P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P3.5/TA0.1 P3.6/TA0.2 P3.7/TA1CLK/CAOUT 3 TAx.y TAxCLK PxIN.
MSP430G2x33 MSP430G2x03 SLAS734F – APRIL 2011 – REVISED MAY 2013 www.ti.com Table 23. Port P3 (P3.0 to P3.7) Pin Functions (RHB Package Only) PIN NAME (P3.x) x FUNCTION CONTROL BITS / SIGNALS (1) P3DIR.x P3SEL.x P3SEL2.x P3.0/ P3.x (I/O) I: 0; O: 1 0 0 TA0.2/ Timer0_A3.CCI2A 0 1 0 Timer0_A3.TA2 1 1 0 Capacitive sensing X 0 1 0 Pin Osc P3.1/ P3.x (I/O) TA1.0/ 1 Pin Osc P3.2/ I: 0; O: 1 0 0 Timer1_A3.TA0 1 1 0 Capacitive sensing X 0 1 P3.x (I/O) TA1.
MSP430G2x33 MSP430G2x03 www.ti.com SLAS734F – APRIL 2011 – REVISED MAY 2013 REVISION HISTORY REVISION SLAS734 (1) DESCRIPTION Production Data release SLAS734A Corrections to Control Bits / Signals column in Table 18 Corrections to Pin Name and Function columns in Table 23 SLAS734B Changed Storage temperature range limit in Absolute Maximum Ratings Added BSL functions to P1.1 and P1.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.