- Texas Instraments Mixed-Signal Processor Model MSP50C6xx User's Guide

Individual Instruction Descriptions
4-108
4.14.24 INTE Interrupt Enable
Syntax
[label] name Clock, clk Word, w With RPT, clk Class
INTE 1 1 N/R 9d
Execution STAT.IM ⇐ 1 (IM is STAT bit 4)
PC ⇐ PC + 1
Flags Affected None
Opcode
Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTE 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0
Description Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register
(STAT) to 1.
See Also INTD, IRET
Example 4.1 INTE
Enables interrupts. Any maskable interrupts occurring after this instruction is serviced.