User manual

1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's Guide
SPRUF89 – October 2007
VLYNQ Port
The VLYNQ™ communications interface port is a serial interface with a low pin count, high-speed
point-to-point serial interface in the device for connecting to host processors and other VLYNQ compatible
devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur
separately and simultaneously without interference.
VLYNQ enables the extension of an internal bus segment to one or more external physical devices. The
external devices are mapped to local physical address space and appear as if they are on the internal bus
of the device. The external devices must also have a VLYNQ interface.
VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that no
extra terminals are needed to indicate that overflow conditions might occur.
The VLYNQ module on the device serializes a write transaction to the remote/external device and
transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes the transaction
on the other side.
The read transactions to the remote/external device follow the same process, but the remote device's
VLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The read
return data is finally deserialized and released to the device internal bus.
The external device can also initiate read and write transactions.
The general features of the VLYNQ port are:
• Low pin count (10 pin interface, scalable to as low as 3 pins) .
• No tri-state signals:
– All signals are dedicated and driven by only one device.
– Necessary to allow support for high-speed PHYs.
• Simple packet-based transfer protocol for memory-mapped access:
– Write request/data packet.
– Read request packet.
– Read response data packet.
– Interrupt request packet.
• Auto width negotiation.
10 VLYNQ Port SPRUF89 – October 2007
Submit Documentation Feedback