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VLYNQinterrupt
pending/setregister
(INTPENDSET)
VLYNQ
Status/clear
register
(INTSTATCLR)
OR
Transmitserial
interruptpacket
VLQINT
(GEMINTC)
14 0
INTLOCAL
VLYNQcontrolregister(CTRL)
Serialbuserror
(LERROR/RERROR)
CPUwrites
Serialinterrupt
packetfrom
remotedevice
INTLOCAL=1
INTLOCAL=0
2.12.2 Writes to Interrupt Pending/Set Register
Peripheral Architecture
• When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register
(INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line,
causing the VLYNQINT to pulse. If the system writes to INTSTATCLR while interrupts are still pending,
a new VLQINT interrupt is generated.
The VLYNQ interrupt generation mechanism is shown in Figure 8 .
Figure 8. Interrupt Generation Mechanism Block Diagram
For additional flexibility of interrupt handling, there is an interrupt priority vector status/clear register
(INTPRI) that reports the highest priority interrupt asserted in the VLYNQ interrupt pending/set register
(INTPENDSET) when INTLOCAL = 1. VLYNQ interprets bit 0 as the highest priority and it interprets bit 31
as the lowest priority. The value that is returned when read is the vector of the highest priority interrupt.
Software can clear that interrupt by writing back the vector value. Additionally, INTRPRI provides a
read-only status bit (NOINTPEND) to indicate whether or not there are any pending interrupts in the
interrupt status/clear register (INTSTATCLR).
As previously discussed, if the GEM CPU writes to the VLYNQ interrupt pending/set register
(INTPENDSET), then depending on the value of the INTLOCAL bit in the VLYNQ control (CTRL) register,
this will result in a local interrupt (to the device interrupt controller) or an interrupt packet transmitted over
the serial interface to the remote device.
VLYNQ Port22 SPRUF89 – October 2007
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