User manual

www.ti.com
3.21 Interrupt Vector 3-0 Register (INTVEC0)
VLYNQ Port Registers
The INTVEC0 is shown in Figure 29 and described in Table 27 .
Figure 29. Interrupt Vector 3-0 Register (INTVEC0)
31 30 29 28 24 23 22 21 20 16
INTEN3 INTTYPE3 INTPOL3 INTTVEC3 INTEN2 INTEN2 INTPOL2 INTVEC2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 8 7 6 5 4 0
INTEN1 INTTYPE1 INTPOL1 INTTVEC1 INTEN0 INTTYPE0 INTPOL0 INTVEC0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 27. Interrupt Vector 3-0 Register (INTVEC0) Field Description
Bit Field Value Description
31 INTEN3 Interrupt Enable 3. When set, this bit indicates that interrupts detected should be written to the
0-1 Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the
status of the intlocal bit in the Control Register.
30 INTTYPE3 Interrupt Type 3
0 Interrupt Vector 3 is level sensitive
1 Interrupt Vector 3 is Pulse
29 INTPOL3 Interrupt Polarity 3
0 Interrupt Vector 3 is active high
1 Interrupt Vector 3 is active low
28-24 INTVEC3 0-1Fh Interrupt Vector 3. This field maps the vlynq_int_i[3] pin to a bit in the Interrupt Pending/Set
Register.
23 INTEN2 Interrupt Enable 2. When set, this bit indicates that interrupts detected should be written to the
0-1 Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the
status of the intlocal bit in the Control Register.
22 INTTYPE2 Interrupt Type 2
0 Interrupt Vector 2 is level sensitive
1 Interrupt Vector 2 is Pulse
21 INTPOL2 Interrupt Polarity 2
0 Interrupt Vector 2 is active high
1 Interrupt Vector 2 is active low
20-16 INTVEC2 0-1Fh Interrupt Vector 2. This field maps the vlynq_int_i[2] pin to a bit in the Interrupt Pending/Set
Register.
15 INTEN1 Interrupt Enable 1. When set, this bit indicates that interrupts detected should be written to the
0-1 Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the
status of the intlocal bit in the Control Register.
14 INTTYPE1 Interrupt Type 1
0 Interrupt Vector 1 is level sensitive
1 Interrupt Vector 1 is Pulse
13 INTPOL1 Interrupt Polarity 1
0 Interrupt Vector 1 is active high
1 Interrupt Vector 1 is active low
12-8 INTVEC1 0-1Fh Interrupt Vector 1. This field maps the vlynq_int_i[1] pin to a bit in the Interrupt Pending/Set
Register.
7 INTEN0 Interrupt Enable 0. When set, this bit indicates that interrupts detected should be written to the
0-1 Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the
status of the intlocal bit in the Control Register.
40 VLYNQ Port SPRUF89 – October 2007
Submit Documentation Feedback