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VLYNQ Port Registers

Table 28. Interrupt Vector 7-4 Register (INTVEC1) Field Description (continued)

Bit Field Value Description

12-8 INTVEC5 0-1Fh Interrupt Vector 5. This field maps the vlynq_int_i[5] pin to a bit in the Interrupt Pending/Set

7 INTEN4 Interrupt Enable 4. When set, this bit indicates that interrupts detected should be written to the

0-1 Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the

status of the intlocal bit in the Control Register.

6 INTTYPE4 Interrupt Type 4

0 Interrupt Vector 4 is level sensitive

1 Interrupt Vector 4 is Pulse

5 INTPOL4 Interrupt Polarity 4

0 Interrupt Vector 4 is active high

1 Interrupt Vector 4 is active low

4-0 INTVEC4 0-1Fh Interrupt Vector 4. This field maps the vlynq_int_i[4] pin to a bit in the Interrupt Pending/Set

SPRUF89 – October 2007 VLYNQ Port 43

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