User manual

List of Tables
1 VLYNQ Port Pins ........................................................................................................... 13
2 Serial Interface Width ...................................................................................................... 17
3 Address Translation Example (Single Mapped Region) .............................................................. 19
4 Address Translation Example (Single Mapped Region) .............................................................. 19
5 VLYNQ Register Address Space ......................................................................................... 25
6 VLYNQ Port Controller Registers ........................................................................................ 25
7 Revision Register (REVID) Field Descriptions ......................................................................... 26
8 Control Register (CTRL) Field Descriptions ............................................................................ 27
9 Status Register (STAT) Field Descriptions ............................................................................. 29
10 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 31
11 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions .................................................. 31
12 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 32
13 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 32
14 Address Map Register (XAM) Field Descriptions ...................................................................... 33
15 Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................ 33
16 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 34
17 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 34
18 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions .............................................. 35
19 Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................ 35
20 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 36
21 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 36
22 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions .............................................. 37
23 Chip Version Register (CHIPVER) Field Descriptions................................................................. 37
24 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 38
25 Manual Negotiation Register (MANNGO) Field Descriptions ......................................................... 38
26 Negotiation Status Register (NGOSTAT) Field Descriptions ......................................................... 39
27 Interrupt Vector 3-0 Register (INTVEC0) Field Description ........................................................... 40
28 Interrupt Vector 7-4 Register (INTVEC1) Field Description ........................................................... 42
29 VLYNQ Port Remote Controller Registers .............................................................................. 44
A-1 Special 8b/10b Code Groups ............................................................................................. 45
A-2 Supported Ordered Sets .................................................................................................. 45
A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 47
B-1 Scaling Factors ............................................................................................................. 50
B-2 Expected Throughput (VLYNQ Interface Running at 99 MHz) ....................................................... 51
B-3 Expected Throughput (VLYNQ Interface Running at 76.5 MHz)..................................................... 52
B-4 Relative Performance with Various Latencies .......................................................................... 53
6 List of Tables SPRUF89 – October 2007
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