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TMS320C6452 DSP
SPRUF86 — TMS320C6452 Peripheral Component Interconnect (PCI) User's Guide describes the
peripheral component interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP).
The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI
master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA)
controller. This architecture allows for both PCI master and slave transactions, while keeping the
EDMA channel resources available for other applications.
SPRUF87 — TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port
interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port
through which a host processor can directly access the CPU memory space. The host device
functions as a master to the interface, which increases ease of access. The host and CPU can
exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the
enhanced direct memory access (EDMA) controller.
SPRUF89 — TMS320C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the
TMS320C6452 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point
serial interface for connecting to host processors and other VLYNQ compatible devices. It is a
full-duplex serial bus where transmit and receive operations occur separately and simultaneously
without interference.
SPRUF90 — TMS320C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer
in the TMS320C6452 Digital Signal Processor (DSP). The timer can be configured as a
general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer.
SPRUF91 — TTMS320C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes
the multichannel audio serial port (McASP) in the TMS320C6452 Digital Signal Processor (DSP).
The McASP functions as a general-purpose audio serial port optimized for the needs of
multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream,
Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
SPRUF92 — TMS320C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port
Interface (SPI) in the TMS320C6452 Digital Signal Processor (DSP). This reference guide provides
the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a
programmable-length shift register, used for high speed communication between external
peripherals or other DSPs.
SPRUF93 — TMS320C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's
Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the
TMS320C6452 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel
conversion on data received from a peripheral device, and parallel-to-serial conversion on data
received from the CPU.
SPRUF94 — TMS320C6452 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the
inter-integrated circuit (I2C) peripheral in the TMS320C6452 Digital Signal Processor (DSP). The
I2C peripheral provides an interface between the DSP and other devices compliant with the
I2C-bus specification and connected by way of an I2C-bus. External components attached to this
2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the
I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification.
SPRUF95 — TMS320C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes the
general-purpose input/output (GPIO) peripheral in the TMS320C6452 Digital Signal Processor
(DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as
either inputs or outputs. When configured as an input, you can detect the state of the input by
reading the state of an internal register. When configured as an output, you can write to an internal
register to control the state driven on the output pin.
8 Read This First SPRUF89 – October 2007
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