User manual

www.ti.com
VLYNQ Port Registers
Table 9. Status Register (STAT) Field Descriptions (continued)
Bit Field Value Description
8 RERROR Remote Error. Write a 1 to this bit to clear it.
0 No error
This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is
1
set when an error indication, /E/, is received from the serial interface. See Appendix A .
If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
the VLYNQ interrupt (VLQINT).
7 LERROR Local error. Write a 1 to this bit to clear it.
0 No error.
This bit indicates that an inbound packet contains an error that is detected by the local
1
VLYNQ module.
If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
the VLYNQ interrupt (VLQINT).
6 NFEMPTY3 FIFO 3 is not empty.
0 Indicates that the slave command FIFO is empty.
1 Indicates that the slave command FIFO is not empty.
5 NFEMPTY2 FIFO 2 is not empty.
0 Indicates that the slave data FIFO is empty.
1 Indicates that the slave data FIFO is not empty.
4 NFEMPTY1 FIFO 1 is not empty.
0 Indicates that the master command FIFO is empty.
1 Indicates that the master command FIFO is not empty.
3 NFEMPTY0 FIFO 0 is not empty.
0 Indicates that the master data FIFO is empty.
1 Indicates that the master data FIFO is not empty.
2 SPEND Pending slave request.
0 No pending slave requests.
Indicates detection of a transfer request initiated by the VLYNQ module to the off-chip
1
peripheral (TX slave configuration bus interface).
1 MPEND Pending master requests.
0 No pending master requests.
Indicates detection of a transfer request initiated by an off-chip peripheral to the VLYNQ
1
module (RX master configuration bus interface).
0 LINK Link
0 Indicates that the serial interface initialization sequence has not yet completed or the link
has timed out.
1 Indicates that the serial interface initialization sequence has completed successfully.
30 VLYNQ Port SPRUE36A – September 2007
Submit Documentation Feedback