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2.2.2.2 Changing PLL Multiplier
PLL Controller
9. If necessary, program PLLDIV1, PLLDIV2, and PLLDIV3 registers to change the SYSCLK1, SYSCLK2,
and SYSCLK3 divide values:
a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
b. Program the RATIO field in PLLDIV1, PLLDIV2, and PLLDIV3 with the desired divide factors. Note
that the dividers must maintain a 1:3:6 ratio to satisfy the CLKDIV1, CLKDIV3, CLKDIV6 clock
domain requirements. See the device-specific data manual for more details on Clock Domains. In
addition, in this step make sure you leave the PLLDIV1.D1EN, PLLDIV2.D2EN, and
PLLDIV3.D3EN bits set (default).
c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition,
SYSCLK1, SYSCLK2, and SYSCLK3 are paused momentarily.
d. Wait for N number of PLLDIV n source clock cycles to ensure divider changes have completed. See
Section 2.2.2.3 for the formula on calculating the number of cycles N.
e. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
10. Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.
11. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
12. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
13. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time
is previously met (step 7 in Section 2.2.2.1 ), follow this procedure to change PLL1 multiplier. The
recommendation is to stop all peripheral operation before changing the PLL multiplier, with the exception
of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to program the PLL controller. DDR2
operates off of the clock from PLLC2.
1. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 MXI cycles to ensure PLLC switches to bypass mode properly.
2. Clear the PLLRST bit in PLLCTL to 0 (reset PLL).
3. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
4. Program the required multiplier value in PLLM.
5. If necessary, program PLLDIV1, PLLDIV2, and PLLDIV3 registers to change the SYSCLK1, SYSCLK2,
and SYSCLK3 divide values:
a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
b. Program the RATIO field in PLLDIV1, PLLDIV2, and PLLDIV3 with the desired divide factors. Note
that the dividers must maintain a 1:3:6 ratio to satisfy the CLKDIV1, CLKDIV3, CLKDIV6 clock
domain requirements. See the device-specific data manual for more details on Clock Domains. In
addition, in this step make sure you leave the PLLDIV1.D1EN, PLLDIV2.D2EN, and
PLLDIV3.D3EN bits set (default).
c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition,
SYSCLK1, SYSCLK2, and SYSCLK3 are paused momentarily.
d. Wait for N number of PLLDIV n source clock cycles to ensure divider changes have completed. See
Section 2.2.2.3 for the formula on calculating the number of cycles N.
e. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
6. Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.
7. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
8. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
Phase-Locked Loop Controller (PLLC)14 SPRUES0B – December 2007
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