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2.3.2.4 Changing SYSCLK Dividers
PLL Controller
This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider
change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in
PLLCMD) to initiate the divider change.
1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in
progress.
2. Program the RATIO field in PLLDIV1 with the desired divide factor. In this step make sure you leave
the PLLDIV1.D1EN bit set (default).
3. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition, SYSCLK1
is paused momentarily.
4. Wait for N number of PLLDIV n source clock cycles to ensure divider changes have completed. See the
following formula for calculating the number of cycles N.
5. Wait for the GOSTAT bit in PLLSTAT to clear to 0.
The following formula should be used to calculate the number of PLLDIV n source clock cycles:
N = (2 × old SYSCLK1 divide value) + 50 cycles overhead
Example 4. Calculating Number of Clock Cycles N
This example calculates the number of clock cycles N.
• Settings before divider change:
– PLLDIV1.RATIO = 1 (divide-by-2)
• New divider settings:
– PLLDIV1.RATIO = 2 (divide-by-3)
Therefore, the number of cycles N is:
N = (2 × 2) + 50 cycles overhead = 54 PLLDIV n source clock cycles
If PLLC2 is in PLL mode (PLLCTL.PLLEN = 1), the PLLDIV n source clock is the PLL2 output clock. If
PLLC2 is in PLL bypass mode (PLLCTL.PLLEN = 0), the PLLDIV n source clock is the device clock
source MXI/CLKIN.
20 Phase-Locked Loop Controller (PLLC) SPRUES0B – December 2007
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