Datasheet

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FEATURES

D PACKAGE

(TOP VIEW)

GND

P PACKAGE

(TOP VIEW)

GND

DGK PACKAGE

(TOP VIEW)

GND

PW PACKAGE

(TOP VIEW)

GND

DESCRIPTION/ORDERING INFORMATION

P82B96

DUAL BIDIRECTIONAL BUS BUFFER

SCPS144B – MAY 2006 – REVISED JULY 2007

• Operating Power-Supply Voltage Range Forward (Tx/Ty) and Reverse (Rx/Ry) Signals

of 2 V to 15 V for Interface With Optoelectrical Isolators and

Similar Devices That Need Unidirectional

• Can Interface Between I

C Buses Operating at

Input and Output Signal Paths

Different Logic Levels (2 V to 15 V)

• 400-kHz Fast I

C Bus Operation Over at Least

• Supports Bidirectional Data Transfer of I

20 Meters of Wire

Bus Signals

• Low Standby Current Consumption

• Allows Bus Capacitance of 400 pF on the Main

C Bus (Sx/Sy Side) and 4000 pF on the • Latch-Up Performance Exceeds 100 mA Per

Transmission Side (Tx/Ty) JESD 78, Class II

• Outputs on the Transmission Side (Tx/Ty) • ESD Protection Exceeds JESD 22

Have High Sink Capability for Driving

– 3500-V Human-Body Model (A114-A)

Low-Impedance or High-Capacitive Buses

– 200-V Machine Model (A115-A)

• I

C Bus Signals Can Be Split Into Pairs of

– 1000-V Charged-Device Model (C101)

The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I

C bus and a range

of other bus configurations with different voltage and current levels. It can function as the interface without any

limitations on the normal I

C operation and clock speed.

ORDERING INFORMATION

PACKAGE

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

PDIP – P Tube of 50 P82B96P P82B96P

Reel of 2000 P82B96DR

SOIC – D PG96

Tube of 75 P82B96D

–40 ° C to 85 ° C

Reel of 2000 P82B96PWR

TSSOP – PW PG96

Tube of 150 P82B96PW

VSSOP – DGK Reel of 2500 P82B96DGKR 7DS

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.
PAGE 2
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). This device also adds minimal loading to I2C node where it is positioned.
PAGE 3
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 FUNCTIONAL BLOCK DIAGRAM VCC (2–15 V) 8 Sx (SDA) 3 1 2 Sy (SCL) 5 7 6 Tx (TxD, SDA) Rx (RxD, SDA) Ty (TxD, SCL) Ry (RxD, SCL) P82B96 4 GND Functional Description Sx and Sy The I2C pins, Sx and Sy, are designed to interface with a normal I2C bus. The logic threshold-voltage levels on the I2C bus are independent of the supply VCC.
PAGE 4
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX –0.3 18 Sx or Sy (SDA or SCL) –0.3 18 Rx or Ry –0.3 18 Sx or Sy (SDA or SCL) –0.3 18 Tx or Ty –0.
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P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics VCC = 2.3 V to 2.
PAGE 6
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics VCC = 3 V to 3.
PAGE 7
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics (continued) VCC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN TYP (1) ΔV/ΔTREL Temperature coefficient of release voltage –4 Cin Input capacitance 2.
PAGE 8
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics VCC = 4.5 V to 5.
PAGE 9
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics (continued) VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN TYP (1) ΔV/ΔTREL Temperature coefficient of release voltage –4 Cin Input capacitance Rx, Ry 2.
PAGE 10
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.
PAGE 11
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Electrical Characteristics (continued) VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS Sx, Sy are low, VCC ramping, voltage on Tx, Ty lowered until released TA = 25°C MIN TYP (1) VIOrel VCC voltage at which all buses are released ΔV/ΔTREL Temperature coefficient of release voltage –4 Cin Input capacitance Rx, Ry 2.
PAGE 12
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS VOL AT Sx vs JUNCTION TEMPERATURE IOL = 0.
PAGE 13
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION VCC VIN VCC VOUT PULSE GENERATOR RL = 160 to 1500 W S1 DUT GND CL = Probe and jig capacitance (see Note A) RT TEST S1 tPLZ/tPZL VCC TEST CIRCUIT FOR OPEN-DRAIN OUTPUT VCC 0.6 V 0V Sx or Sy tPZL tPLZ VCC 0.5 ´ VCC Tx or Ty VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES A. CL includes probe and jig capacitance. B.
PAGE 14
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 APPLICATION INFORMATION Typical Applications Figure 2 through Figure 4 show typical applications for the P82B96. VCC (2–15V) 5V R1 Tx (SDA) 2 IC SDA SDA (New Levels) Rx (SDA) 1/2 PB2B96 Figure 2. Interfacing I2C Bus With Different Logic Levels VCC1 VCC R4 R2 R5 R3 I2C SDA 5V Rx (SDA) R1 2 IC SDA Tx (SDA) 1/2 P82B96 Figure 3.
PAGE 15
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 APPLICATION INFORMATION (continued) Figure 5 shows how a master I2C bus can be protected against short circuits or failures in applications that involve plug/socket connections and long cables that may become damaged. A simple circuit is added to monitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus.
PAGE 16
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 APPLICATION INFORMATION (continued) end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way propagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are between 20 ns and 50 ns, so their delay contributions are small.
PAGE 17
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Note that, in both the 100-m and 250-m examples, the capacitive loading on the I2C buses at each end is within the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard mode bus loadings with rise times that contribute significantly to the system delays.
PAGE 18
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Buffered Expansion Bus Local Master Bus VCCM Remote Slave Bus VCCS VCCB MASTER SDA Rm Rs Rb Sx P82B96 Tx/Rx Tx/Rx P82B96 SDA SLAVE Sx I2C I2C Cm = Master Bus Capacitance Cb = Buffered Bus Wiring Capacitance Cs = Slave Bus Capacitance GND Rising edge of SDA at slave is delayed by the buffers and bus rise times. Effective delay of SDA at master = 270 + 0.2RsCs + 0.
PAGE 19
P82B96 DUAL BIDIRECTIONAL BUS BUFFER www.ti.com SCPS144B – MAY 2006 – REVISED JULY 2007 Sample Calculations The master bus has an RmCm product of 100 ns and VCCM = 5 V. The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns. The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to ≥1662.5 ns.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 20-May-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device P82B96DGKR Package Package Pins Type Drawing VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 P82B96DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 P82B96PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 4-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) P82B96DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 P82B96DR SOIC D 8 2500 367.0 367.0 35.0 P82B96PWR TSSOP PW 8 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.