PC16550D PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs† Literature Number: SNLS378B
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs ² General Description Features The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode)* the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead.
Table of Contents 8.0 REGISTERS (Continued) 1.0 ABSOLUTE MAXIMUM RATINGS 8.3 Programmable Baud Generator 2.0 DC ELECTRICAL CHARACTERISTICS 8.4 Line Status Register 8.5 FIFO Control Register 8.6 Interrupt Identification Register 8.7 Interrupt Enable Register 8.8 Modem Control Register 8.9 Modem Status Register 8.10 Scratchpad Register 8.11 FIFO Interrupt Mode Operation 8.12 FIFO Polled Mode Operation 3.0 AC ELECTRICAL CHARACTERISTICS 4.0 TIMING WAVEFORMS 5.0 BLOCK DIAGRAM 6.0 PIN DESCRIPTIONS 7.
1.0 Absolute Maximum Ratings Temperature Under Bias b 65§ C to a 150§ C All Input or Output Voltages with Respect to VSS b 0.5V to a 7.0V Power Dissipation 2.0 Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics.
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4.0 Timing Waveforms (Continued) Write Cycle TL/C/8652 – 5 *Applicable Only When ADS is Tied Low. Read Cycle TL/C/8652 – 6 *Applicable Only When ADS is Tied Low.
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4.0 Timing Waveforms (Continued) RCVR FIFO First Byte (This Sets RDR) TL/C/8652 – 10 RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) TL/C/8652 – 11 Receiver Ready (Pin 29) FCR0 e 0 or FCR0 e 1 and FCR3 e 0 (Mode 0) TL/C/8652 – 12 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, then tSINT e 3 RCLKs. For a timeout interrupt, tSINT e 8 RCLKs.
4.0 Timing Waveforms (Continued) Receiver Ready (Pin 29) FCR0 e 1 and FCR3 e 1 (Mode 1) TL/C/8652 – 13 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, tSINT e 3 RCLKs.
5.0 Block Diagram TL/C/8652 – 16 Note: Applicable pinout numbers are included within parenthesis.
6.0 Pin Descriptions The following describes the function of all UART pins. Some of these descriptions reference internal circuits. In the following descriptions, a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( a 2.4V nominal). A0, A1, A2, Register Select, Pins 26–28: Address signals connected to these 3 inputs select a UART register for the CPU to read from or write to during data transfer. A table of registers and their addresses is shown below.
6.0 Pin Descriptions (Continued) OUT 2, Output 2, Pin 31: This user-designated output that can be set to an active low by programming bit 3 (OUT 2) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. In the XMOS parts this will achieve TTL levels. RCLK, Receiver Clock, Pin 9: This input is the 16 c baud rate clock for the receiver section of the chip.
7.0 Connection Diagrams (Continued) Chip Carrier Package TQFP Package TL/C/8652 – 26 TL/C/8652 – 18 Order Number PC16550DVEF See NS Package Number VEF44A Top View Order Number PC16550DV See NS Package Number V44A TABLE I.
14 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 4 5 6 7 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 0 0 0 0 Enable MODEM Status Interrupt (EDSSI) Enable Receiver Line Status Interrupt (ELSI) Enable Transmitter Holding Register Empty Interrupt (ETBEI) IER Enable Received Data Available Interrupt (ERBFI) Interrupt Enable Register 1 DLAB e 0 2 FIFOs Enabled (Note 2) FIFOs Enabled (Note 2) 0 0 Interrupt ID Bit (2) (Note 2) Interrupt ID Bit (1) Interrupt ID Bi
8.0 Registers Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is used to produce an even or odd number of 1s when the data word bits and the Parity bit are summed.) Bit 4: This bit is the Even Parity Select bit.
8.0 Registers (Continued) Bit 7: This bit is the Divisor Latch Access Bit (DLAB). It must be set high (logic 1) to access the Divisor Latches of the Baud Generator during a Read or Write operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. 8.2 8.4 TYPICAL CLOCK CIRCUITS TL/C/8652–19 TL/C/8652–20 Typical Crystal Oscillator Network (Note) CRYSTAL RP RX2 C1 C2 3.1 MHz 1 MX 1.5k 10-30 pF 40-60 pF 1.
8.0 Registers (Continued) TABLE IV.
8.0 Registers (Continued) Bit 3: This bit controls the Output 2 (OUT 2) signal, which is an auxiliary user-designated output. Bit 3 affects the OUT 2 output in a manner identical to that described above for bit 0. Bit 4: This bit provides a local loopback feature for diagnostic testing of the UART.
8.0 Registers (Continued) B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE e 1 and there have not been at least two bytes at the same time in the transmit FIFO, since the last THRE e 1. The first transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
This shows the basic connections of an PC16550D to an 8088 CPU TL/C/8652 – 22 9.
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PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs 10.0 Physical Dimensions inches (millimeters) (Continued) 44-Lead Package (TQEF) Order Number PC16550DVEF NS Package Number VEF44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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