NS16C552,PC16552D PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs† Literature Number: SNLS387B
PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs ² General Description Features The PC16552D is a dual version of the PC16550D Universal Asynchronous Receiver/Transmitter (UART). The two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450*. Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead.
Table of Contents 8.0 REGISTERS (Continued) 1.0 ABSOLUTE MAXIMUM RATINGS 8.3 Programmable Baud Generator 2.0 DC ELECTRICAL CHARACTERISTICS 8.4 Line Status Register 8.5 FIFO Control Register 8.6 Interrupt Identification Register 8.7 Interrupt Enable Register 8.8 Modem Control Register 8.9 Modem Status Register 8.10 Alternate Function Register 8.11 Scratchpad Register 3.0 AC ELECTRICAL CHARACTERISTICS 4.0 TIMING WAVEFORMS 5.0 BLOCK DIAGRAM OF A SINGLE SERIAL CHANNEL 6.0 PIN DESCRIPTIONS 6.
1.0 Absolute Maximum Ratings Temperature under Bias Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics. 0§ C to a 70§ C Storage Temperature b 65§ C to a 150§ C All Input or Output Voltages with Respect to VSS b 0.5V to a 7.0V Power Dissipation 1W 2.
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4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Read Cycle TL/C/9426 – 6 Write Cycle TL/C/9426 – 5 Transmitter Timing TL/C/9426 – 8 Note 1: See Write Cycle Timing. Note 2: See Read Cycle Timing.
4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Receiver Timing TL/C/9426 – 7 MODEM Control Timing TL/C/9426 – 9 Note 1: See Write Cycle Timing. Note 2: See Read Cycle Timing.
4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) RCVR FIFO First Byte (This Sets RDR) TL/C/9426 – 10 RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) TL/C/9426 – 11 Receiver Ready FCR0 e 0 or FCR0 e 1 and FCR3 e 0 (Mode 0) TL/C/9426 – 12 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, then tSINT e 3 RCLKs. For a timeout interrupt, tSINT e 8 RCLKs.
4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Receiver Ready FCR0 e 1 and FCR3 e 1 (Mode 1) TL/C/9426 – 13 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, tSINT e 3 RCLKs.
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6.0 Pin Descriptions The following describes the function of all DUART pins. Some of these descriptions reference internal circuits. In the following descriptions, a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( a 2.4V nominal). appropriate channel. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has changed state since the previous reading of the MODEM Status Register.
6.0 Pin Descriptions (Continued) RI1, RI2 (Ring Indicator), pins 43, 31: When low, this indicates that a telephone ringing signal has been received by the MODEM or data set. The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI) of the MODEM Status Register for the appropriate channel. Bit 6 is the complement of the RI signal.
8.0 Registers TABLE I.
14 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 4 5 6 7 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 0 DLAB e 0 Transmitter Holding Register (Write Only) THR Data Bit 0 0 0 0 IER Enable Received Data Available Interrupt (ERDAI) Enable Transmitter Holding Register Empty Interrupt (ETHREI) Enable Receiver Line Status Interrupt (ELSI) Enable MODEM Status Interrupt (EMSI) 0 Interrupt Enable Register 1 DLAB e 0 FIFOs Enabled (Note 2) FIFOs Enabled (Note 2) 0
8.0 Registers (Continued) Two identical register sets, one for each channel, are in the DUART. All register descriptions in this section apply to the register sets in both channels. Note: This feature enables the CPU to alert a terminal in a computer communications system. If the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 8.
8.0 Registers (Continued) TABLE III.
8.0 Registers (Continued) Bit 7: In the 16450 Mode this is a 0. In the FIFO Mode LSR7 is set when there is at least one parity error, framing error or break indication in the FIFO. LSR7 is cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO. Bit 4: This bit is the Break Interrupt (BI) indicator.
8.0 Registers (Continued) RXRDY Mode 1: In the FIFO Mode (FCR0 e 1) when the FCR3 e 1 and the trigger level or the timeout has been reached, the RXRDY pin will go low active. Once it is activated it will go inactive when there are no more characters in the FIFO. TXRDY Mode 0: In the 16450 Mode (FCR0 e 0) or in the FIFO Mode (FCR0 e 1, FCR3 e 0) when there are no characters in the XMIT FIFO or XMIT Holding Register, the TXRDY pin will go low active.
8.0 Registers (Continued) In this diagnostic mode, the receiver and transmitter interrupts are fully operational. Their sources are external to the part. The MODEM Control Interrupts are also operational, but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the four MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7: These bits are permanently set to logic 0. 8.
The maximum time between a received character and a timeout interrupt will be 160 ms at 300 baud with a 12-bit receive character (i.e. 1 START, 8 DATA, 1 PARITY and 2 STOP BITS). 8.0 Registers (Continued) Bits 1 and 2: These select the output signal that will be present on the multi-function pin, MF. These bits are individually programmable for each channel, so that different signals can be selected on each channel. Table VI associates the signal present at the multi-function pin with the bit code. B.
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PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs Physical Dimensions inches (millimeters) 44-Lead Plastic Chip Carrier (V) Order Number PC16552DV NS Package Number V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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