Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional, Open Drain X2SON 8 (1.4x1.0)

DCT OR DCU PACKAGE

(TOP VIEW)

GND

REF1

3 6

SCL1

SDA1

REF2

SCL2

SDA2

DQE PACKAGE

(TOP VIEW)

SCL2

SDA2

SCL1

SDA1

GND

REF1

REF2

3 6

GND

REF1

SCL1

SDA1

REF2

SCL2

SDA2

YZT PACKAGE

(BOTTOM VIEW)

PCA9306

www.ti.com

SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010

DUAL BIDIRECTIONAL I

C BUS AND SMBus

VOLTAGE-LEVEL TRANSLATOR

Check for Samples: PCA9306

FEATURES

• 2-Bit Bidirectional Translator for SDA and SCL • Latch-Up Performance Exceeds 100 mA Per

Lines in Mixed-Mode I

C Applications JESD 78, Class II

• I

C and SMBus Compatible • ESD Protection Exceeds JESD 22

• Less Than 1.5-ns Maximum Propagation Delay – 2000-V Human-Body Model (A114-A)

to Accommodate Standard-Mode and

– 200-V Machine Model (A115-A)

Fast-Mode I

C Devices and Multiple Masters

– 1000-V Charged-Device Model (C101)

• Allows Voltage-Level Translator Between

– 1.2-V V

REF1

and 1.8-V, 2.5-V, 3.3-V,

or 5-V V

REF2

– 1.8-V V

REF1

and 2.5-V, 3.3-V, or 5-V V

REF2

– 2.5-V V

REF1

and 3.3-V or 5-V V

REF2

– 3.3-V V

REF1

and 5-V V

REF2

• Provides Bidirectional Voltage Translation

With No Direction Pin

• Low 3.5-Ω ON-State Connection Between Input

and Output Ports Provides Less Signal

Distortion

• Open-Drain I

C I/O Ports (SCL1, SDA1, SCL2,

and SDA2)

• 5-V Tolerant I

C I/O Ports to Support

Mixed-Mode Signal Operation

• High-Impedance SCL1, SDA1, SCL2, and SDA2

Pins for EN = Low

• Lock-Up-Free Operation for Isolation When

EN = Low

• Flow-Through Pinout for Ease of Printed

Circuit Board Trace Routing

DESCRIPTION/ORDERING INFORMATION

This dual bidirectional I

C and SMBus voltage-level translator, with an enable (EN) input, is operational from

1.2-V to 3.3-V V

REF1

and 1.8-V to 5.5-V V

REF2

The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin.

The low ON-state resistance (r

) of the switch allows connections to be made with minimal propagation delay.

When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2

I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and

a high-impedance state exists between ports.

In I

C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the

PCA9306 enables the system designer to isolate two halves of a bus; thus, more I

C devices or longer trace

length can be accommodated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
PCA9306 www.ti.com SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 2 DUAL BIDIRECTIONAL I C BUS AND SMBus VOLTAGE-LEVEL TRANSLATOR Check for Samples: PCA9306 FEATURES 1 • • • • • • • • • • • 2-Bit Bidirectional Translator for SDA and SCL Lines in Mixed-Mode I2C Applications I2C and SMBus Compatible Less Than 1.5-ns Maximum Propagation Delay to Accommodate Standard-Mode and Fast-Mode I2C Devices and Multiple Masters Allows Voltage-Level Translator Between – 1.2-V VREF1 and 1.8-V, 2.5-V, 3.
PAGE 2
PCA9306 SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 www.ti.com The PCA9306 also can be used to run two buses, one at 400-kHz operating frequency and the other at 100-kHz operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated when the 400-kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
PAGE 3
PCA9306 www.ti.com SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 FUNCTION TABLE LOGIC DIAGRAM (POSITIVE LOGIC) VREF1 VREF2 2 7 8 SCL1 SDA1 3 4 SW SW 6 5 1 GND INPUT EN (1) TRANSLATOR FUNCTION H SCL1 = SCL2, SDA1 = SDA2 L Disconnect EN SCL2 SDA2 (1) The SCL switch conducts if EN is ≥ 1 V higher than SCL1 or SCL2. The same is true of SDA.
PAGE 4
PCA9306 SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VREF1 DC reference voltage range –0.5 7 V VREF2 DC reference bias voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VI/O Input/output voltage range (2) –0.
PAGE 5
PCA9306 www.ti.com SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 AC PERFORMANCE (TRANSLATING DOWN) (3) Switching Characteristics over recommended operating free-air temperature range, EN = 3.3 V, VIH = 3.3 V, VIL = 0, VM = 1.15 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL (3) FROM (INPUT) TO (OUTPUT) SCL2 or SDA2 SCL1 or SDA1 CL = 50 pF CL = 30 pF CL = 15 pF MIN MAX MIN MAX MIN MAX 0 0.8 0 0.6 0 0.3 0 1.2 0 1 0 0.
PAGE 6
PCA9306 SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION VT RL USAGE SWITCH Translating up Translating down S1 S2 S1 Open From Output Under Test S2 3.3 V Input VM VM VIL CL (see Note A) 5V Output VM VM LOAD CIRCUIT VOL TRANSLATING UP 5V Input VM VM VIL 2V Output VM VM VOL TRANSLATING DOWN NOTES: A. CL includes probe and jig capacitance. B.
PAGE 7
PCA9306 www.ti.com SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 APPLICATION INFORMATION General Applications of I2C In I2C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9306 enables the system designer to isolate two halves of a bus; thus, more I2C devices or longer trace length can be accommodated. The PCA9306 also can be used to run two buses, one at 400-kHz operating frequency and the other at 100-kHz operating frequency.
PAGE 8
PCA9306 SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 www.ti.com VDPU = 3.3 V 3.3-V Enable Signal On Off 200 k Ω PCA9306 EN VREF1 = 1.8 V RPU 2 RPU 8 VREF1 VREF2 SCL1 SCL2 RPU 7 RPU VCC 3 SCL VCC SW 6 SCL I2C Bus Device I2C Bus Master 4 SDA SDA1 SW SDA2 5 SDA GND GND GND 1 Figure 3.
PAGE 9
PCA9306 www.ti.com SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 Sizing Pullup Resistor The pullup resistor value needs to limit the current through the pass transistor, when it is in the on state, to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA, the pullup resistor value is calculated as: R PU + VDPU * 0.35 V 0.
PAGE 10
PCA9306 SCPS113J – OCTOBER 2004 – REVISED OCTOBER 2010 www.ti.com The 3-dB point of the PCA9306 is ≈600 MHz. However, this measurement is an analog type of measurement. For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. As a rule of thumb, the frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very important in determining the overall shape of the digital signal.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCA9306DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 PCA9306DCUR US8 DCU 8 3000 178.0 9.5 2.25 3.35 1.05 4.0 8.0 Q3 PCA9306DCURG4 US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9306DCUR US8 DCU 8 3000 202.0 201.0 28.0 PCA9306DCUR US8 DCU 8 3000 202.0 201.0 28.0 PCA9306DCURG4 US8 DCU 8 3000 202.0 201.0 28.0 PCA9306DCUTG4 US8 DCU 8 250 202.0 201.0 28.0 PCA9306DQER X2SON DQE 8 5000 202.0 201.0 28.0 PCA9306YZTR DSBGA YZT 8 3000 182.0 182.0 17.
PAGE 15
MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
PAGE 21
D: Max = 1.918 mm, Min =1.858 mm E: Max = 0.918 mm, Min =0.
PAGE 22
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.