Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters I²C 400 kHz SOIC 8

D PACKAGE

(TOP VIEW)

CCA

GND

SDAA

SCLA

CCB

SDAB

SCLB

DGK PACKAGE

(TOP VIEW)

CCA

CCB

GND EN

3 6

SDAA SDAB

SCLA SCLB

Not Recommended for New Designs

PCA9517

www.ti.com

SCPS157D –DECEMBER 2007–REVISED MARCH 2012

LEVEL-TRANSLATING I

C BUS REPEATER

Check for Samples: PCA9517

FEATURES

• Two-Channel Bidirectional Buffer Mixed-Mode Signal Operation

• I

C Bus and SMBus Compatible • Lockup-Free Operation

• Operating Supply Voltage Range of • Accommodates Standard Mode and Fast Mode

0.9 V to 5.5 V on A Side I

C Devices and Multiple Masters

• Operating Supply Voltage Range of • Powered-Off High-Impedance I

C Pins

2.7 V to 5.5 V on B Side

• 400-kHz Fast I

C Bus

• Voltage-Level Translation From 0.9 V to 5.5 V

• Latch-Up Performance Exceeds 100 mA Per

and 2.7 V to 5.5 V

JESD 78, Class II

• Footprint and Function Replacement for

• ESD Protection Exceeds JESD 22

PCA9515A

– 2000-V Human-Body Model (A114-A)

• Active-High Repeater-Enable Input

– 200-V Machine Model (A115-A)

• Open-Drain I

C I/O

– 1000-V Charged-Device Model (C101)

• 5.5-V Tolerant I

C and Enable Input Support

DESCRIPTION/ORDERING INFORMATION

This dual bidirectional I

C buffer is operational at 2.7 V to 5.5 V.

The PCA9517 is a BiCMOS integrated circuit intended for I

C bus and SMBus systems. It can also provide

bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and

higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I

C and similar bus systems to

be extended, without degradation of performance even during level shifting.

The PCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I

C bus, thus allowing

two buses of 400-pF bus capacitance to be connected in an I

C application. This device can also be used to

isolate two halves of a bus for voltage and capacitance.

The PCA9517 has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage

tolerant to 5.5 V, even when the device is unpowered (V

CCB

and/or V

CCA

= 0 V).

The PCA9517 doesnot support clock stretching and arbitration across the repeater.

ORDERING INFORMATION

PACKAGES

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

SOIC – D Tape and reel PCA9517DR PD517

–40°C to 85°C

MSOP – DGK Tape and reel PCA9517DGKR 7E_

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

PAGE 1
Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 LEVEL-TRANSLATING I2C BUS REPEATER Check for Samples: PCA9517 FEATURES 1 • • • • • • • • • Two-Channel Bidirectional Buffer I2C Bus and SMBus Compatible Operating Supply Voltage Range of 0.9 V to 5.5 V on A Side Operating Supply Voltage Range of 2.7 V to 5.5 V on B Side Voltage-Level Translation From 0.9 V to 5.5 V and 2.7 V to 5.
PAGE 2
Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low.
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Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 TERMINAL FUNCTIONS NO. NAME DESCRIPTION 1 VCCA A-side supply voltage (0.9 V to 5.5 V) 2 SCLA Serial clock bus, A side. Connect to VCCA through a pullup resistor. 3 SDAA Serial data bus, A side. Connect to VCCA through a pullup resistor. 4 GND Supply ground 5 EN 6 SDAB Serial data bus, B side. Connect to VCCB through a pullup resistor. 7 SCLB Serial clock bus, B side.
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Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCB Supply voltage range –0.5 7 V VCCA Supply voltage range –0.5 7 V VI Enable input voltage range (2) –0.5 7 V VI/O I2C bus voltage range (2) –0.
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Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER VIK TEST CONDITIONS Input clamp voltage Low-level output voltage VOL VCCB MIN II = –18 mA 2.7 V to 5.5 V SDAB, SCLB IOL = 100 μA or 6 mA, VILA = VILB = 0 V 2.7 V to 5.5 V SDAA, SCLA IOL = 6 mA VOL – VILc Low-level input voltage below low-level output voltage SDAB, SCLB 2.7 V to 5.
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Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com I2C INTERFACE TIMING REQUIREMENTS VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLZ Propagation delay FROM (INPUT) TO (OUTPUT) SDAB, SCLB (2) (see Figure 5) SDAA, SCLA (2) (see Figure 5) 100 169 255 SDAA, SCLA (3) (see Figure 4) SDAB, SCLB (3) (see Figure 4) 25 67 110 VCCA ≤ 2.7 V (see Figure 3) 15 68 (4) 110 2.
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Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 PARAMETER MEASUREMENT INFORMATION VCC VIN RL (see Note A) VOUT PULSE GENERATOR VCC S1 DUT GND CL = 57 pF (see Note C) RT (see Note B) TEST S1 tPLZ/tPZL VCC TEST CIRCUIT FOR OPEN-DRAIN OUTPUT A. RL = 167 Ω on the A side and 1.35 kΩ on the B side B. RT termination resistance should be equal to ZOUT of pulse generators. C. CL includes probe and jig capacitance. D.
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Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) INPUT SDAB, SCLB 0.5 V 50% is VCCA is less than 2 V 1.5 V if VCCA is greater than 2 V OUTPUT SCLA, SDAA tPLH Figure 5.
PAGE 9
Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 APPLICATION INFORMATION A typical application is shown in Figure 6. In this example, the system master is running on a 3.3-V I2C bus, and the slave is connected to a 1.2-V bus. Both buses run at 400 kHz. Master devices can be placed on either bus. The PCA9517 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9-V to 5.5-V bus voltages and 2.7-V to 5.5-V bus voltages.
PAGE 10
Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com VCCA 10 kΩ VCCB 10 kΩ 10 kΩ 10 kΩ SDA SDAA SDAB SDA SCL SCLA SCLB SCL SLAVE 400 kHz PCA9517 BUS MASTER EN 10 kΩ 10 kΩ SDAA SDAB SDA SCLA SCLB SCL PCA9517 SLAVE 400 kHz EN 10 kΩ 10 kΩ SDAA SDAB SDA SCLA SCLB SCL SLAVE 400 kHz PCA9517 EN Figure 7.
PAGE 11
Not Recommended for New Designs PCA9517 www.ti.com SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 0.5 V/DIV 9th CLOCK PULSE — ACKNOWLEDGE SCL SDA Figure 9. Bus A (0.9-V to 5.5-V Bus) Waveform 2 V/DIV 9th CLOCK PULSE — ACKNOWLEDGE SCL SDA VOL OF PCA9517 VOL OF SLAVE Figure 10. Bus B (2.7-V to 5.
PAGE 12
Not Recommended for New Designs PCA9517 SCPS157D – DECEMBER 2007 – REVISED MARCH 2012 www.ti.com REVISION HISTORY Changes from Revision B (May 2010) to Revision C • Deleted all references to arbitration and clock stretching support. This does not effect min/max specifications. ................ 1 Changes from Revision C (February 2011) to Revision D • 12 Page Page Updated the TOP-SIDE MARKING column of the ORDERING INFORMATION TABLE. ...................................................
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCA9517DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PCA9517DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PCA9517DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9517DGKR VSSOP DGK 8 2500 346.0 346.0 35.0 PCA9517DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 PCA9517DR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.