Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - I/O extensions POR I²C, SMBus 400 kHz TSSOP 16

DB,DBQ,DGV,DW,ORPWPACKAGE

(TOP VIEW)

GND

SDA

SCL

INT

RGVPACKAGE

(TOP VIEW)

6 8

131415

SDA

INT

SCL

GND

RGTPACKAGE

(TOP VIEW)

6 8

131415

SDA

INT

SCL

GND

PCA9534A

www.ti.com

SCPS141H –SEPTEMBER 2006–REVISED AUGUST 2013

REMOTE 8-BIT I

C AND SMBus LOW-POWER I/O EXPANDER

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

Check for Samples: PCA9534A

FEATURES

• Low Standby Current Consumption of • Polarity Inversion Register

1 μA Max

• Internal Power-On Reset

• I

C to Parallel Port Expander

• Power-Up With All Channels Configured as

• Open-Drain Active-Low Interrupt Output Inputs

• Operating Power-Supply Voltage Range of • No Glitch on Power-Up

2.3 V to 5.5 V

• Noise Filter on SCL/SDA Inputs

• 5-V Tolerant I/O Ports

• Latched Outputs With High-Current Drive

• 400-kHz Fast I

C Bus Maximum Capability for Directly Driving LEDs

• Three Hardware Address Pins Allow Up to • Latch-Up Performance Exceeds 100 mA Per

Eight Devices on the I

C/SMBus JESD 78, Class II

• Allows Up to 16 Devices on the I

C/SMBus • ESD Protection Exceeds JESD 22

When Used in Conjunction with the PCA9534

– 2000-V Human-Body Model (A114-A)

See Table 1 for I

C Expander offerings

– 200-V Machine Model (A115-A)

• Input/Output Configuration Register

– 1000-V Charged-Device Model (C101)

DESCRIPTION

This 8-bit I/O expander for the two-line bidirectional bus (I

C) is designed for 2.3-V to 5.5-V V

operation. It

provides general-purpose remote I/O expansion for most microcontroller families via the I

C interface [serial clock

(SCL), serial data (SDA)].

The PCA9534A consists of one 8-bit configuration (input or output selection), input port, output port, and polarity

inversion (active high or active low) register. At power on, the I/Os are configured as inputs. However, the system

master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each

input or output is kept in the corresponding input or output register. The polarity of the input port register can be

inverted with the polarity inversion register. All registers can be read by the system master.

The system master can reset the PCA9534A in the event of a timeout or other improper operation by utilizing the

power-on reset feature, which puts the registers in their default state and initializes the I

C/SMBus state machine.

The PCA9534A open-drain interrupt (INT) output is activated when any input state differs from its corresponding

input port register state and is used to indicate to the system master that an input state has changed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (42 pages)

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PCA9534A www.ti.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9534A can remain a simple slave device. The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current consumption.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 Table 1. I2C Expander Offerings DEVICE MAX FREQUENCY I2C ADDRESS TCA6408 400 0100 00x TCA6408 400 TCA6416 VCC RANGE NO. OF GPIOs INTERRUPT OUTPUT RESET INPUT 1.65 to 5.5 8 Yes Yes 0100 00x 1.65 to 5.5 8 Yes 400 0100 00x 1.65 to 5.5 16 TCA6416A 400 0100 00x 1.65 to 5.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com Table 2. TERMINAL FUNCTIONS NO. QSOP (DBQ), SOIC (DW), SSOP (DB), TSSOP (PW), AND TVSOP (DGV) QFN (RGT) AND QFN (RGV) NAME 1 15 A0 Address input. Connect directly to VCC or ground. 2 16 A1 Address input. Connect directly to VCC or ground. 3 1 A2 Address input. Connect directly to VCC or ground. 4 2 P0 P-port input/output. Push-pull design structure. 5 3 P1 P-port input/output. Push-pull design structure.
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PCA9534A www.ti.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 Table 3. Interface Definition BYTE 2 I C slave address Px I/O data bus BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H H H A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 Device Address Figure 5 shows the address byte of the PCA9534A. Slave Address 0 1 1 1 A2 A1 A0 R/W Hardware Selectable Fixed Figure 5. PCA9534A Address Table 4.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com Table 5.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 Interrupt Output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com Reads The bus master first must send the PCA9534A address with the least-significant bit set to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6 V VI Input voltage range (2) –0.5 6 V VO Output voltage range (2) –0.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = –18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 IOH = –8 mA P-port high-level output voltage (2) VOH IOH = –10 mA SDA VOL = 0.4 V VOL = 0.5 V P port (3) IOL VOL = 0.7 V INT SCL, SDA II A2–A0 VCC MIN 2.3 V to 5.5 V –1.2 VPOR 2.3 V 1.8 3V 2.6 4.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 I2C INTERFACE TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (see Figure 11) STANDARD MODE I2C BUS MIN MAX 100 fscl I2C clock frequency 0 tsch I2C clock high time 4 2 tscl I C clock low time tsp I2C spike time tsds I2C serial-data setup time FAST MODE I2C BUS UNIT MIN MAX 0 400 4.7 μs 1.3 50 50 250 2 100 0 kHz μs 0.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 35 55 50 VCC = 5 V 30 ICC – Supply Current – nA ICC – Supply Current – µA 45 40 f SCL = 400 kHz I/Os unloaded 35 30 25 20 VCC = 3.3 V 15 10 VCC = 2.5 V VCC = 5 V 25 VCC = 3.3 V 20 15 VCC = 2.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS (continued) I/O OUTPUT LOW VOLTAGE vs TEMPERATURE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 30 300 250 VCC = 2.5 V VCC = 2.5 V, ISINK = 10 mA 25 ISINK – I/O Sink Current – mA VOL – Output Low Voltage – mV 275 225 200 175 150 VCC = 5 V, ISINK = 10 mA 125 100 VCC = 2.5 V, ISINK = 1 mA 75 50 VCC = 5 V, ISINK = 1 mA TA = –40°C 20 TA = 25°C 15 TA = 85°C 10 5 25 0 0 -40 -15 10 35 60 0.0 85 0.1 0.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) I/O OUTPUT HIGH VOLTAGE vs TEMPERATURE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 35 275 VCC = 2.5 V VCC = 2.5 V, IOL = 10 mA ISOURCE – I/O Source Current – mA (V CC – V OH ) – Output High Voltage – mV 250 225 200 175 150 125 VCC = 5 V, IOL = 10 mA 100 75 VCC = 2.5 V, IOL = 1 mA 50 VCC = 5 V, IOL = 1 mA 25 30 TA = –40°C 25 TA = 25°C 20 15 10 TA = 85°C 5 0 0 -40 0.0 -15 10 35 60 0.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS (continued) OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE 6 TA = 25°C VOH – Output High Voltage – V 5 4 IOH = –8 mA 3 IOH = –10 mA 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 07 (MSB) Data Bit 10 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tsts tPHL ticf tbuf tPLH tsp 0.7 × VCC SDA 0.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 kΩ INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 0 1 1 1 A2 A1 A0 1 A 1 2 3 4 A 5 6 7 8 Data 1 ACK From Slave Data From Port A Data 2 1 P A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 × VCC INT 0.3 × VCC SCL Data 2 0.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 500 W Pn 2 × VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 × VCC SCL P0 A P3 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 × VCC SCL P0 A tps P3 0.3 × VCC tph 0.7 × VCC Pn 0.3 × VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 PARAMETER MEASUREMENT INFORMATION (continued) VCC Pn RL = 1 kΩ DUT 500 W 2 × VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A. CL includes probe and jig capacitance. B.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com APPLICATION INFORMATION Figure 15 shows an application in which the PCA9534A can be used. A. Device address is configured as 0111100 for this example. B. P0, P2, and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. P6 and P7 are not used and must be configured as outputs. Figure 15.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 Minimizing ICC When the I/O Controls LEDs When the I/Os are used to control LEDs, they normally are connected to VCC through a resistor as shown in Figure 15. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical Characteristics.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 10 specifies the performance of the power-on reset feature for PCA9534A for both types of power-on reset. Table 10.
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PCA9534A www.ti.com SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 VCC VPOR VPORF Time POR Time Figure 21. VPOR Interrupt Requirements The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input register is read or all inputs return to the last read values. INT is also de-asserted when both of the following occur: • The last I2C command byte (register pointer) written was 00h.
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PCA9534A SCPS141H – SEPTEMBER 2006 – REVISED AUGUST 2013 www.ti.com REVISION HISTORY Changes from Revision G (June 2010) to Revision H Page • Removed Ordering Information Table. ................................................................................................................................. 2 • Deleted the 100 kΩ resistor at VCC .....................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 9-Aug-2013 Status (1) PCA9534ARGVRG4 ACTIVE Package Type Package Pins Package Drawing Qty VQFN RGV 16 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-2-260C-1 YEAR (4/5) -40 to 85 PD534A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 PCA9534ADBR SSOP DB 16 2000 330.0 16.4 PCA9534ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 PCA9534ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9534ADBR SSOP DB 16 2000 367.0 367.0 38.0 PCA9534ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 PCA9534ADWR SOIC DW 16 2000 367.0 367.0 38.0 PCA9534APWR TSSOP PW 16 2000 367.0 367.0 35.0 PCA9534ARGTR QFN RGT 16 3000 367.0 367.0 35.0 PCA9534ARGVR VQFN RGV 16 2500 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.