Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - I/O extensions POR I²C, SMBus 400 kHz TSSOP 16

FEATURES

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

RESET

GND

SDA

SCL

INT

RGV PACKAGE

(TOP VIEW)

6 8

131415

SDA

INT

SCL

GND

RESET

RGT PACKAGE

(TOP VIEW)

6 8

131415

SDA

INT

SCL

GND

RESET

DESCRIPTION/ORDERING INFORMATION

PCA9538

www.ti.com

................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008

REMOTE 8-BIT I

C AND SMBus LOW-POWER I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

• Low Standby Current Consumption of • Power-Up With All Channels Configured as

1 µ A Max Inputs

• I

C to Parallel Port Expander • No Glitch on Power Up

• Open-Drain Active-Low Interrupt Output • Noise Filter on SCL/SDA Inputs

• Active-Low Reset Input • Latched Outputs With High-Current Drive

Maximum Capability for Directly Driving LEDs

• Operating Power-Supply Voltage Range of

2.3 V to 5.5 V • Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• 5-V Tolerant I/O Ports

• ESD Protection Exceeds JESD 22

• 400-kHz Fast I

C Bus

– 2000-V Human-Body Model (A114-A)

• Two Hardware Address Pins Allow up to Four

Devices on the I

C/SMBus – 200-V Machine Model (A115-A)

• Input/Output Configuration Register – 1000-V Charged-Device Model (C101)

• Polarity Inversion Register

This 8-bit I/O expander for the two-line bidirectional bus (I

C) is designed for 2.3-V to 5.5-V V

operation. It

provides general-purpose remote I/O expansion for most microcontroller families via the I

C interface [serial clock

(SCL), serial data (SDA)].

The PCA9538 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity

Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the

system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for

each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port

The system master can reset the PCA9538 in the event of a timeout or other improper operation by asserting a

low in the RESET input. The power-on reset puts the registers in their default state and initializes the I

C/SMBus

state machine. The RESET pin causes the same reset/initialization to occur without powering down the part.

The PCA9538 open-drain interrupt ( INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
PCA9538 www.ti.com ................................................................................................................................................
PAGE 2
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus.
PAGE 3
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 FUNCTIONAL BLOCK DIAGRAM INT A0 A1 SCL SDA RESET VCC GND A. 13 Interrupt Logic LP Filter 1 2 P7−P0 14 15 Input Filter I2C Bus Control Shift Register 8 I/O Port Write Pulse 3 16 8 Bits Power-On Reset Read Pulse Pin numbers shown are for the DB, DBQ, DGV, DW, or PW package.
PAGE 4
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.
PAGE 5
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions.
PAGE 6
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3.
PAGE 7
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected while a low (0) selects a write operation.
PAGE 8
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver.
PAGE 9
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 SCL 1 2 3 4 5 6 7 8 9 Slave Address S SDA 1 1 1 0 Command Byte 0 A1 A0 0 A 0 0 0 0 0 0 0 1 Data 1 A A P ACK From Slave ACK From Slave R/W ACK From Slave Start Condition Data to Port Write to Port Data Out From Port Data 1 Valid tpv Figure 6.
PAGE 10
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com Reads The bus master first must send the PCA9538 address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed.
PAGE 11
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6 V VI Input voltage range (2) –0.
PAGE 12
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.
PAGE 13
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 I2C INTERFACE TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.
PAGE 14
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 35 55 50 VCC = 5 V 30 ICC – Supply Current – nA ICC – Supply Current – µA 45 40 f SCL = 400 kHz I/Os unloaded 35 30 25 VCC = 3.3 V 20 15 VCC = 2.
PAGE 15
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O OUTPUT LOW VOLTAGE vs TEMPERATURE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 30 VCC = 2.5 V 250 VCC = 2.
PAGE 16
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O OUTPUT HIGH VOLTAGE vs TEMPERATURE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 35 VCC = 2.5 V 250 VCC = 2.
PAGE 17
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE 6 TA = 25°C VOH – Output High Voltage – V 5 4 IOH = –8 mA 3 IOH = –10 mA 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.
PAGE 18
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.
PAGE 19
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.
PAGE 20
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Pn 500 W 2 × VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 × VCC SCL P0 A P3 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.
PAGE 21
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC Pn RL = 1 kΩ DUT 500 W 2 × VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.
PAGE 22
PCA9538 SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com APPLICATION INFORMATION Figure 14 shows an application in which the PCA9538 can be used. VCC (5 V) 10 kW VCC Master Controller 10 kW 10 kW 2 kW 10 kW 100 kW (y3) VCC SDA SDA SCL SCL INT INT RESET RESET P0 Subsystem 1 (e.g.
PAGE 23
PCA9538 www.ti.com ................................................................................................................................................ SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC.
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 20-May-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 PCA9538DBR SSOP DB 16 2000 330.0 16.4 PCA9538DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 PCA9538DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PCA9538PWR TSSOP PW 16 2000 330.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9538DBR SSOP DB 16 2000 367.0 367.0 38.0 PCA9538DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 PCA9538DWR SOIC DW 16 2000 367.0 367.0 38.0 PCA9538PWR TSSOP PW 16 2000 367.0 367.0 35.
PAGE 28
PAGE 29
PAGE 30
PAGE 31
PAGE 32
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 33
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.