Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - I/O extensions POR I²C, SMBus 400 kHz TSSOP 24

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

INT

RESET

P00

P01

P02

P03

P04

P05

P06

P07

GND

SDA

SCL

P17

P16

P15

P14

P13

P12

P11

P10

24 23 22 21 20

7 8 9 10 11

RGE PACKAGE

(TOP VIEW)

INT

P10

P11 SDA

P06

P07

GND

SCL

P12

P00

P01

P02

P03

P04

P05

P17

P16

P15

P14

P13

RESET

PCA9539

www.ti.com

SCPS130F –AUGUST 2005–REVISED JANUARY 2011

REMOTE 16-BIT I

C AND SMBus LOW-POWER I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

Check for Samples: PCA9539

FEATURES

• Low Standby-Current Consumption of • Address by Two Hardware Address Pins for

1 mA Max Use of up to Four Devices

• I

C to Parallel Port Expander • Latched Outputs With High-Current Drive

Capability for Directly Driving LEDs

• Open-Drain Active-Low Interrupt Output

• Latch-Up Performance Exceeds 100 mA Per

• Active-Low Reset Input

JESD 78, Class II

• 5-V Tolerant I/O Ports

• ESD Protection Exceeds JESD 22

• Compatible With Most Microcontrollers

– 2000-V Human-Body Model (A114-A)

• 400-kHz Fast I

C Bus

– 1000-V Charged-Device Model (C101)

• Polarity Inversion Register

DESCRIPTION/ORDERING INFORMATION

This 16-bit I/O expander for the two-line bidirectional bus (I

C) is designed for 2.3-V to 5.5-V V

operation. It

provides general-purpose remote I/O expansion for most microcontroller families via the I

C interface [serial clock

(SCL), serial data (SDA)].

The PCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity

Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The

system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for

each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register

can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The system master can reset the PCA9539 in the event of a time-out or other improper operation by asserting a

low in the RESET input. The power-on reset puts the registers in their default state and initializes the I

C/SMBus

state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.

The PCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

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PCA9539 www.ti.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9539 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 TERMINAL FUNCTIONS NO. SOIC (DW), SSOP (DB), QSOP (DBQ), TSSOP (PW), AND TVSOP (DGV) QFN (RGE) 1 22 INT Interrupt output. Connect to VCC through a pullup resistor. 2 23 A1 Address input. Connect directly to VCC or ground. 3 24 RESET 4 1 P00 P-port input/output. Push-pull design structure. 5 2 P01 P-port input/output. Push-pull design structure. 6 3 P02 P-port input/output. Push-pull design structure.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) INT A0 A1 SCL SDA PCA9539 1 Interrupt Logic LP Filter 21 2 P07−P00 22 23 Input Filter I2C Bus Control Shift Register 16 Bits I/O Port P17−P10 Write Pulse 3 RESET VCC GND 4 24 12 Power-On Reset Read Pulse A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages. B. All I/Os are set to inputs at reset.
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PCA9539 www.ti.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on I2C Bus Table 1.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com Device Address Figure 4 shows the address byte of the PCA9539. R/W Slave Address 1 1 1 0 Fixed 1 A1 A0 Programmable Figure 4. PCA9539 Address Table 2.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 Register Descriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com RESET Input A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9539 registers and I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a pullup resistor to VCC, if no active connection is used. Interrupt (INT) Output An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid.
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PCA9539 www.ti.com 1 SCL SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 2 3 4 5 6 7 8 9 1 2 3 Slave Address SDA S 1 1 1 0 1 4 5 6 7 8 9 1 2 3 0 R/W Start Condition A 0 0 0 0 0 1 1 5 6 7 8 9 1 2 3 Data to Register Command Byte A1 A0 4 0 A MSB Data 0 5 Data to Register LSB Acknowledge From Slave Acknowledge From Slave 4 A MSB Data 1 LSB A P Acknowledge From Slave Figure 7.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 1 SCL 2 3 4 5 6 7 8 www.ti.com 9 I0.x SDA S 1 1 1 0 1 A1 1 A0 A R/W 7 6 5 4 3 I1.x 2 1 0 A 7 6 5 4 3 Acknowledge From Master Acknowledge From Slave I0.x 2 1 0 A 7 6 5 4 3 I1.x 2 1 0 A 7 6 5 4 3 2 Acknowledge From Master Acknowledge From Master 1 0 1 P No Acknowledge From Master Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 INT tiv tir A.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6 UNIT V (2) –0.5 6 V –0.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = –18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 VCC MIN 2.3 V to 5.5 V –1.2 VPOR IOH = –8 mA P-port high-level output voltage (2) VOH IOH = –10 mA 1.8 3V 2.6 4.75 V 4.1 2.3 V 1.7 3V 2.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11) MIN MAX UNIT 0 400 kHz I2C clock frequency fscl 2 tsch I C clock high time 0.6 tscl I2C clock low time 1.3 tsp I2C spike time tsds I2C serial-data setup time ms ms 50 100 2 ns ns tsdh I C serial-data hold time ticr I2C input rise time 20 + 0.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE STANDBY SUPPLY CURRENT vs TEMPERATURE 55 70 30 SCL = V CC 50 V CC = 5 V ICC – Supply Current – nA 40 f SCL = 400 kHz I/Os Unloaded 35 30 25 V CC = 3.3 V 20 15 10 V CC = 2.5 V 5 0 -50 f SCL = 400 kHz I/Os Unloaded 60 25 ICC – Supply Current – µA 45 ICC – Supply Current – µA SUPPLY CURRENT vs SUPPLY VOLTAGE 20 V CC = 5 V 15 V CC = 3.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE 300 V CC = 5 V 250 V OH – Output High Voltage – mV TA = –40°C 60 55 50 45 40 300 275 TA = 25°C 35 30 25 20 15 TA = 125°C 10 5 0 275 250 V CC = 2.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tsts tPHL ticf tbuf tPLH tsp 0.7 × VCC SDA 0.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 kΩ INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 1 1 1 0 1 1 2 3 4 5 A1 A0 1 6 7 8 Data 1 A ACK From Slave Data From Port A Data 2 1 P A A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 × VCC INT 0.3 × VCC SCL Data 2 0.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 500 W Pn 2 × VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 × VCC SCL P0 A P3 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 × VCC SCL P0 A tps P3 0.3 × VCC tph 0.7 × VCC Pn 0.3 × VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 PARAMETER MEASUREMENT INFORMATION (continued) VCC Pn RL = 1 kΩ DUT 500 W 2 × VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) SDA LOAD CONFIGURATION P-PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A. CL includes probe and jig capacitance. B.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION Figure 15 shows an application in which the PCA9539 can be used. Subsystem 1 (e.g., Temperature Sensor) INT VCC (5 V) 10 kW VCC 10 kW 10 kW 24 10 kW 22 SCL Master Controller SDA 23 SCL SDA Subsystem 2 (e.g., Counter) 100 kW VCC 1 3 INT RESET INT GND 2 kW 4 P00 5 P01 6 P02 7 P03 8 P04 9 P05 100 kW 100 kW RESET A ENABLE B PCA9539 P06 P07 P10 P11 2 A1 P12 P13 21 A0 P14 P15 P16 GND P17 12 A.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 Minimizing ICC When I/O Is Used to Control LED When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 15). Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 8 specifies the performance of the power-on reset feature for PCA9539 for both types of power-on reset. Table 8.
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PCA9539 www.ti.com SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 VCC VPOR VPORF Time POR Time Figure 21. VPOR Interrupt Requirements The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input register is read or all inputs return to the last read values. INT is also de-asserted when both of the following occur: • The last I2C command byte (register pointer) written was 00h.
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PCA9539 SCPS130F – AUGUST 2005 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY Changes from Revision E (May 2008) to Revision F • 26 Page Changed reel quantity to 2000 from 1200 for the PCA9539PWR part. ................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCA9539DBQR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PCA9539DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 PCA9539DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9539DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 PCA9539DBR SSOP DB 24 2000 367.0 367.0 38.0 PCA9539DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 PCA9539DWR SOIC DW 24 2000 367.0 367.0 45.0 PCA9539PWR TSSOP PW 24 2000 367.0 367.0 38.0 PCA9539RGER VQFN RGE 24 3000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.