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FEATURES

DESCRIPTION/ORDERING INFORMATION

PCA9544A

4-CHANNEL I

C AND SMBus MULTIPLEXER

WITH INTERRUPT LOGIC

SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008

www.ti.com

• 1-of-4 Bidirectional Translating Switches • Supports Hot Insertion

• I

C Bus and SMBus Compatible • Low Standby Current

• Four Active-Low Interrupt Inputs • Operating Power-Supply Voltage Range of

2.3 V to 5.5 V

• Active-Low Interrupt Output

• 5.5-V Tolerant Inputs

• Three Address Pins, Allowing up to Eight

Devices on the I

C Bus • 0 to 400-kHz Clock Frequency

• Channel Selection Via I

C Bus • Latch-Up Performance Exceeds 100 mA Per

JESD 78

• Power Up With All Switch Channels

Deselected • ESD Protection Exceeds JESD 22

• Low R

Switches – 2000-V Human-Body Model (A114-A)

• Allows Voltage-Level Translation Between – 200-V Machine Model (A115-A)

1.8-V, 2.5-V, 3.3-V, and 5-V Buses

– 1000-V Charged-Device Model (C101)

• No Glitch on Power Up

The PCA9544A is a quad bidirectional translating switch controlled via the I

C bus. The SCL/SDA upstream pair

fans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this is

determined by the contents of the programmable control register. Four interrupt inputs ( INT3– INT0), one for each

of the downstream pairs, are provided. One interrupt output ( INT) acts as an AND of the four interrupt inputs.

A power-on reset function puts the registers in their default state and initializes the I

C state machine, with no

channel selected.

The pass gates of the switches are constructed such that the V

pin can be used to limit the maximum high

voltage, which will be passed by the PCA9544A. This allows the use of different bus voltages on each pair, so

that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External

pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.

ORDERING INFORMATION

PACKAGE

(1) (2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

QFN – RGW Reel of 3000 PCA9544ARGWR PREVIEW

QFN – RGY Reel of 1000 PCA9544ARGYR PD544A

Tube of 25 PCA9544ADW

SOIC – DW PCA9544A

Reel of 2000 PCA9544ADWR

Tube of 70 PCA9544APW

– 40 ° C to 85 ° C

TSSOP – PW Reel of 2000 PCA9544APWR PD544A

Reel of 250 PCA9544APWT

TVSOP – DGV Reel of 2000 PCA9544ADGVR PD544A

VFBGA – GQN Reel of 1000 PCA9544AGQNR PD544A

VFBGA – ZQN (Pb-free) Reel of 1000 PCA9544AZQNR PD544A

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 FEATURES 1 • • • • • • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Four Active-Low Interrupt Inputs Active-Low Interrupt Output Three Address Pins, Allowing up to Eight Devices on the I2C Bus Channel Selection Via I2C Bus Power Up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 BLOCK DIAGRAM PCA9544A SC0 SC1 SC2 SC3 SD0 SD1 6 9 13 16 5 8 12 SD2 SD3 GND VCC SCL SDA INT0 INT1 INT2 INT3 15 Switch Control Logic 10 20 Power-on Reset 18 19 1 Input Filter I2C 4 7 11 14 2 Bus Control Interrupt Logic 3 Output Filter 17 A0 A1 A2 INT Pin numbers shown are for DGV, DW, PW, and RGY packages.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9544A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 Table 1.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 Power-On Reset When power is applied to VCC, an internal power-on reset holds the PCA9544A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released, and the PCA9544A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 4. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 5).
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR Power-on reset voltage TEST CONDITIONS (2) No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.7 2.1 5V 3.6 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 µA 2.6 3.3 V 3 V to 3.6 V IOH INT VO = VCC 1.6 VOL = 0.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) STANDARD-MODE I2C BUS MIN MAX 100 FAST-MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.
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PCA9544A 4-CHANNEL I C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC 2 www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 kΩ DUT INT CL = 100 pF (See Note A) INTERRUPT LOAD CONFIGURATION INTn (input) 0.5 × VCC INTn (input) tir tiv INT (output) 0.5 × VCC 0.5 × VCC INT (output) VOLTAGE WAVEFORMS (tiv) 0.5 × VCC VOLTAGE WAVEFORMS (tir) NOTES: A. CL includes probe and jig capacitance. B.
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PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC www.ti.com SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008 APPLICATION INFORMATION VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V 20 SDA I2C/SMBus SCL Master 19 18 17 SDA SCL INT See Note A SD0 5 SC0 6 4 INT0 Channel 0 VCC = 2.7 V to 5.5 V See Note A SD1 SC1 INT1 8 9 7 Channel 1 VCC = 2.7 V to 5.5 V PCA9544A See Note A SD2 SC2 INT2 3 A2 2 A1 1 A0 10 GND 12 13 Channel 2 11 VCC = 2.7 V to 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCA9544ADGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PCA9544ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PCA9544APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9544ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 PCA9544ADWR SOIC DW 20 2000 367.0 367.0 45.0 PCA9544APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCA9544APWT TSSOP PW 20 250 367.0 367.0 38.0 PCA9544ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 PCA9544AZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 338.1 338.1 20.
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