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FEATURES

RGY PACKAGE

(TOP VIEW)

SDA

RESET

SCL

INT0

INT

SD0

SC3

SC0

SD3

INT1

INT3

SD1

SC2

SC1

SD2

GND

INT2

6 8 9 10

INT2

SD2

SD1

SC1

GND

RESET

INT0

SD0

SC0

INT1

INT

SC3

SD3

INT3

SC2

RGW PACKAGE

(TOP VIEW)

18 17 16

SCL

DGV, DW, OR PW PACKAGE

(TOP VIEW)

RESET

INT0

SD0

SC0

INT1

SD1

SC1

GND

SDA

SCL

INT

SC3

SD3

INT3

SC2

SD2

INT2

DESCRIPTION/ORDERING INFORMATION

PCA9545A

4-CHANNEL I

C AND SMBus SWITCH

WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006

• 1-of-4 Bidirectional Translating Switches • No Glitch on Power Up

• I

C Bus and SMBus Compatible • Supports Hot Insertion

• Four Active-Low Interrupt Inputs • Low Standby Current

• Active-Low Interrupt Output • Operating Power-Supply Voltage Range of

2.3 V to 5.5 V

• Active-Low Reset Input

• 5.5-V Tolerant Inputs

• Two Address Pins, Allowing up to Four

Devices on the I

C Bus • 0 to 400-kHz Clock Frequency

• Channel Selection Via I

C Bus, In Any • Latch-Up Performance Exceeds 100 mA Per

Combination JESD 78

• Power Up With All Switch Channels • ESD Protection Exceeds JESD 22

Deselected

– 2000-V Human-Body Model (A114-A)

• Low R

Switches

– 200-V Machine Model (A115-A)

• Allows Voltage-Level Translation Between

– 1000-V Charged-Device Model (C101)

1.8-V, 2.5-V, 3.3-V, and 5-V Buses

The PCA9545A is a quad bidirectional translating switch controlled via the I

C bus. The SCL/SDA upstream pair

fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can

be selected, determined by the contents of the programmable control register. Four interrupt inputs ( INT3– INT0),

one for each of the downstream pairs, are provided. One interrupt ( INT) output acts as an AND of the four

interrupt inputs.

An active-low reset ( RESET) input allows the PCA9545A to recover from a situation in which one of the

downstream I

C buses is stuck in a low state. Pulling RESET low resets the I

C state machine and causes all

the channels to be deselected, as does the internal power-on reset function.

The pass gates of the switches are constructed such that the V

pin can be used to limit the maximum high

voltage, which will be passed by the PCA9545A. This allows the use of different bus voltages on each pair, so

that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External

pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 TERMINAL FUNCTIONS NO. DGV, DW, PW, AND RGY RGW GQN AND ZQN NAME DESCRIPTION 1 19 A2 A0 Address input 0. Connect directly to VCC or ground. 2 20 A1 A1 Address input 1. Connect directly to VCC or ground. 3 1 B3 RESET 4 2 B1 INT0 Active-low interrupt input 0. Connect to VCC through a pullup resistor. 5 3 C2 SD0 Serial data 0.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 BLOCK DIAGRAM PCA9545A SC0 SC1 SC2 SC3 6 9 13 16 SD0 5 SD1 8 SD2 12 SD3 15 GND VCC RESET Switch Control Logic 10 20 3 Power-on Reset SCL 18 SDA INT0 INT1 19 1 Input Filter I2C Bus Control A0 A1 4 7 Interrupt Logic INT2 11 INT3 14 Pin numbers shown are for DGV, DW, PW, and RGY packages.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Table 1.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 RESET Input The RESET input can be used to recover the PCA9545A from a bus-fault condition. The registers and the I2C state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL. All channels also are deselected in this case. RESET must be connected to VCC through a pullup resistor.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 4. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S).
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Start Condition Clock Pulse for ACK Figure 7. Acknowledgment on the I2C Bus A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR Power-on reset TEST CONDITIONS voltage (2) No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.6 2.1 5V 3.6 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 µA 2.6 3.3 V 3 V to 3.6 V IOH INT VO = VCC 1.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) PARAMETER MIN tPWRL Low-level pulse duration rejection of INTn inputs 1 µs tPWRH High-level pulse duration rejection of INTn inputs 0.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.
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PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL trst 50% LEDx LED OFF Figure 11. Reset Timing VCC RL = 4.7 kΩ DUT INT CL = 100 pF (See Note A) INTERRUPT LOAD CONFIGURATION INTn (input) 0.5 × VCC INTn (input) tiv INT (output) 0.5 × VCC tir 0.5 × VCC INT (output) VOLTAGE WAVEFORMS (tiv) 0.
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PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION Figure 13 shows an application in which the PCA9545A can be used. VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V 20 SDA I2C/SMBus SCL Master 19 18 17 3 See Note A SDA SD0 SCL SC0 INT RESET INT0 5 6 4 Channel 0 VCC = 2.7 V to 5.5 V See Note A SD1 8 SC1 9 7 INT1 Channel 1 VCC = 2.7 V to 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 20-May-2013 Status (1) PCA9545AZQNR ACTIVE Package Type Package Pins Package Drawing Qty BGA MICROSTAR JUNIOR ZQN 20 1000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) SNAGCU Level-1-260C-UNLIM (4/5) -40 to 85 PD545A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCA9545ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PCA9545APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCA9545APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9545ADWR SOIC DW 20 2000 367.0 367.0 45.0 PCA9545APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCA9545APWT TSSOP PW 20 250 367.0 367.0 38.0 PCA9545ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 PCA9545AZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 338.1 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.