Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - I/O extensions POR I²C, SMBus 400 kHz SOIC 16 N

FEATURES

RGVPACKAGE

(TOP VIEW)

1516

SCL

SDA

RESET

GND

D,DB,DGV,ORPWPACKAGE

(TOP VIEW)

8 9

GND

SCL

SDA

RESET

RGYPACKAGE

(TOP VIEW)

7 10

SDA

SCL

8 9

GND

RESET

DESCRIPTION/ORDERING INFORMATION

PCA9557

www.ti.com

.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008

REMOTE 8-BIT I

C AND SMBus LOW-POWER I/O EXPANDER

WITH RESET AND CONFIGURATION REGISTERS

• Low Standby Current Consumption of • Internal Power-On Reset

1 µ A Max

• High-Impedance Open Drain on P0

• I

C to Parallel Port Expander

• Power Up With All Channels Configured as

• Operating Power-Supply Voltage Range of Inputs

2.3 V to 5.5 V

• No Glitch on Power Up

• 5-V Tolerant I/O Ports

• Noise Filter on SCL/SDA Inputs

• 400-kHz Fast I

C Bus

• Latched Outputs With High Current Drive

• Three Hardware Address Pins Allow for Use of Maximum Capability for Directly Driving LEDs

up to Eight Devices on I

C/SMBus

• Latch-Up Performance Exceeds 100 mA Per

• Lower-Voltage Higher-Performance Migration JESD 78, Class II

Path for PCA9556

• ESD Protection Exceeds JESD 22

• Input/Output Configuration Register

– 2000-V Human-Body Model (A114-A)

• Polarity Inversion Register

– 200-V Machine Model (A115-A)

• Active-Low Reset Input

– 1000-V Charged-Device Model (C101)

This 8-bit I/O expander for the two-line bidirectional bus (I

C) is designed for 2.3-V to 5.5-V V

operation. The

device provides general-purpose remote I/O expansion for most microcontroller families via the I

C interface

[serial clock (SCL) and serial data (SDA)].

The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarity

inversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system master can

enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or

output is kept in the corresponding input or output register. The polarity of the input port register can be inverted

with the polarity inversion register. All registers can be read by the system master.

The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low

current consumption.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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PCA9557 www.ti.com....................................................................................................................................................
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a low in the active-low reset (RESET) input.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 LOGIC DIAGRAM (POSITIVE LOGIC) A0 A1 A2 SCL SDA 3 4 5 1 2 P7−P0 Input Filter I2C-Bus Control Shift Register 8 Bits I/O Port Write Pulse VCC RESET GND Read Pulse 16 15 Power-On Reset 8 A. Pin numbers shown are for the D, DB, DGV, PW, and RGY packages. B.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.
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PCA9557 www.ti.com....................................................................................................................................................
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 Device Address The address of the PCA9557 is shown in Figure 4. Slave Address 0 0 1 1 A2 A1 A0 R/W Fixed Programmable Figure 4.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com Register Descriptions The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. It only acts on read operation. Writes to these registers have no effect.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 Bus Transactions Data is exchanged between the master and PCA9557 through write and read commands. Writes Data is transmitted to the PCA9557 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address).
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com Reads The bus master first must send the PCA9557 address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6 V VI Input voltage range (2) –0.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS FAST MODE I2C BUS MIN MAX 100 UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE STANDBY SUPPLY CURRENT vs TEMPERATURE 20 60 70 SCL = VCC VCC = 5 V ICC - Standby Supply Current - nA 50 f SCL = 400 kHz I/Os unloaded 45 40 35 30 25 VCC = 3.3 V 20 15 10 VCC = 2.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE (P7–P1) OUTPUT HIGH VOLTAGE vs TEMPERATURE (P7–P1) 600 (V CC – V OH ) – Output High Voltage – mV TA = 25°C 5 4 IOH = –4 mA 3 IOH = –8 mA 2 IOH = –10 mA 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Pn 500 W 2 × VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 × VCC SCL P0 A P7 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 1 kΩ DUT 500 W Pn SDA 2 × VCC DUT CL = 50 pF (see Note A) CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A.
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PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com APPLICATION INFORMATION Figure 14 shows an application in which the PCA9557 can be used. VCC (5 V) VCC Master Controller 1.8 kΩ 1.8 kΩ 620 Ω 2 kΩ 2 kΩ 100 kΩ (X 5) VCC SCL SCL SDA SDA P0 Subsystem 1 INT P1 RESET RESET P2 RESET P3 GND Subsystem 2 (e.g.
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PCA9557 www.ti.com.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008 Minimizing ICC When I/O Is Used to Control LED When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 20-May-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 PCA9557DBR SSOP DB 16 2000 330.0 16.4 8.2 PCA9557DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 PCA9557DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9557DBR SSOP DB 16 2000 367.0 367.0 38.0 PCA9557DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 PCA9557DR SOIC D 16 2500 367.0 367.0 38.0 PCA9557DT SOIC D 16 250 367.0 367.0 38.0 PCA9557PWR TSSOP PW 16 2000 367.0 367.0 35.0 PCA9557PWT TSSOP PW 16 250 367.0 367.0 35.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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