Data Manual December 2004 Connectivity Solutions SCPS071E
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Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 3.7 4 iv Title Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 PC Card Functional and Card Status Change Interrupts . 3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . .
Section 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 5 Title I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 7 8 vi Title Page 5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5−14 5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5−15 5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5−15 5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5−16 5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5−16 5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5−17 5.
List of Illustrations Figure 2−1 2−2 2−3 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 5−1 5−2 6−1 Title PCI1510 GGU-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . PCI1510 GVF-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . PCI1510 PGE-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . PCI1510 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 4−1 4−2 4−3 4−4 4−5 4−6 4−7 4−8 4−9 viii Title Signal Names Sorted by PGE Terminal Number . . . . . . . . . . . . . . . . . . . . Signal Names Sorted by GGU Terminal Number . . . . . . . . . . . . . . . . . . . . Signal Names Sorted by GVF Terminal Number . . . . . . . . . . . . . . . . . . . . CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals . . .
Table Title Page 4−10 4−11 4−12 4−13 4−14 4−15 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Capabilities Register Description . . . . . . . . . . . . . . . Power-Management Control/Status Register Description . . . . . . . . . . . . .
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1 Introduction 1.1 Description The Texas Instruments PCI1510 device, a 144-terminal or a 209-terminal single-slot CardBus controller designed to meet the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power high-performance PCI-to-CardBus controller that supports a single PC card socket compliant with the PC Card Standard (rev. 7.2).
• Up to five general-purpose I/Os • Programmable output select for CLKRUN • Five PCI memory windows and two I/O windows available for the 16-bit interface • Two I/O windows and two memory windows available to the CardBus socket • Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space • Intel 82365SL-DF and 82365SL register compatible • Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN • Socket activity LED terminal • PCI bus lock (LOCK) • In
ru – read-only access with updates by the controller internal hardware rw – read and write access rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates by the controller internal hardware. 1.6 Ordering Information ORDERING NUMBER PCI1510 NAME PC Card controller VOLTAGE 3.3 V, 5-V tolerant I/Os PACKAGE 144-terminal LQFP 144-ball PBGA (GGU or ZGU) 209-ball PBGA (GVF or ZVF) 1.
1−4
2 Terminal Descriptions The PCI1510 controller is available in five packages, a 144-terminal quad flatpack (PGE), two 144-terminal MicroStar BGA packages (GGU/ZGU), and two 209-terminal PBGA packages (GVF/ZVF). The GGU and ZGU packages are mechanically and electrically identical, but the ZGU is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only the GGU package designator is used for either the GGU or ZGU package.
19 C C 18 C C 17 C C 16 15 14 Î Î Î Î GVF PACKAGE (TOP VIEW) C C C C C C C ÎÎ ÎÎ C C C N N N N N N ÎÎ ÎÎ N N N N N N C C 13 C C C C C C N N N C C C C C C C N N N C C C C C C C C N N N N N N N N N N N N 12 C C C C C N N N N N 11 C C C C N N N N N 10 Î C C C C C N N N N N 9 C C C C C N P P P P 8 Î Î C C C C P P P P N N N N P P P P N N T N M P P P T T N M M P P
2.1 PCI1510 Terminal Assignments Figure 2−3 and Table 2−1 show the terminal assignments for the PGE package. Table 2−2 and Table 2−3 list the terminal assignments for the GGU and GVF packages, respectively. The signal names for the PC Card slot are given in a CardBus // 16-bit signal format. All tables are arranged in order by increasing terminal designator, which is numeric for the PGE package and alphanumeric for the other packages.
Table 2−1.
Table 2−1.
Table 2−2.
Table 2−2.
Table 2−3.
Table 2−3.
Table 2−3.
Table 2−4.
Table 2−4.
Table 2−5.
Table 2−5.
2.2 Terminal Descriptions The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 2−6.
Table 2−8. PCI System Terminals TERMINAL NUMBER NAME GRST PGE 66 GGU L11 I/O DESCRIPTION GVF H02 I Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST normally is asserted only during initial boot.
Table 2−9.
Table 2−10. PCI Interface Control Terminals TERMINAL NUMBER NAME I/O DESCRIPTION R02 I/O PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the controller terminates the cycle with an initiator abort. J01 N05 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle.
Table 2−11. Multifunction and Miscellaneous Terminals TERMINAL NUMBER NAME CLK_48_RSVD MFUNC0 I/O DESCRIPTION PGE GGU GVF 85 H10 — No connect. These terminals have no connection anywhere within the package. Terminals H10 on the GGU package and 85 on the PGE package will be used as a 48-MHz clock input on future-generation devices. F05 Multifunction terminal 0.
Table 2−12.
Table 2−13. 16-Bit PC Card Interface Control Terminals TERMINAL NUMBER NAME BVD1 (STSCHG/RI) PGE 135 GGU C06 I/O DESCRIPTION GVF A09 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced.
Table 2−13. 16-Bit PC Card Interface Control Terminals (Continued) TERMINAL NUMBER NAME I/O PGE GGU GVF VS1 130 B02 B10 VS2 117 A09 F12 WAIT 133 B06 WE 105 D13 WP (IOIS16) 136 A05 DESCRIPTION I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the PC Card. E10 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O in progress. D19 O Write enable.
Table 2−15.
Table 2−16. CardBus PC Card Interface Control Terminals TERMINAL NUMBER NAME I/O DESCRIPTION F10 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The controller supports the binary audio mode and outputs a binary signal from the card to SPKROUT. A13 E18 I/O 75 L13 L17 138 B05 C09 PGE GGU GVF CAUDIO 134 D06 CBLOCK 101 CCD1 CCD2 CDEVSEL CFRAME 106 111 D11 A10 A16 B15 CardBus lock. CBLOCK is used to gain exclusive access to a target.
3 Feature/Protocol Descriptions The following sections give an overview of the PCI1510 controller. Figure 3−1 shows a simplified block diagram of the controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power-management control signal), and SPKROUT.
2. Remove the clamp voltage. 3. Remove the 3.3-V power from VCC. NOTE: The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The voltage difference between VCC and the clamp voltage must remain within 3.6 V. 3.2 I/O Characteristics Figure 3−2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs.
3.4.2 PCI Bus Lock (LOCK) The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on the controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal by setting the appropriate values in bits 19−16 of the multifunction routing register. See Section 4.30, Multifunction Routing Register, for details.
3.5 PC Card Applications This section describes the PC Card interfaces of the controller. • • • • • 3.5.1 Card insertion/removal and recognition Zoomed video support Speaker and audio applications LED socket activity indicators CardBus socket registers PC Card Insertion/Removal and Recognition The PC Card Standard (release 7.2) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket.
Power Supply 12 V 5V 3.3 V TPS2211A 12V 5V 3.3V AVPP SHDN SHDN Supervisor AVCC VCCD0 VCCD1 VPPD0 VPPD1 PCI1510 (PC Card Controller) VPP1 VPP2 VCC VCC PC Card Figure 3−3. TPS2211A Typical Application 3.5.3 Zoomed Video Support The controller allows for the implementation of zoomed video (ZV) for PC Cards. Zoomed video is supported by setting bit 6 (ZVENABLE) in the card control register (PCI offset 91h, see Section 4.32).
PCI1510 ZVSTAT ZVSEL0 Figure 3−5. Zoomed Video Switching Application Figure 3−5 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled. 3.5.4 Standardized Zoomed-Video Register Model The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC Card controllers across the industry.
There are two types of PC Card controllers to consider. • Legacy controller not using the standardized ZV register model Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to determine if the standardized zoomed-video register model is supported. If the bit returns 0b, then software must use legacy code to enable zoomed video.
3.5.7 SPKROUT and CAUDPWM Usage SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform.
Current Limiting R ≈ 500 Ω LED PCI1510 ApplicationSpecific Delay Current Limiting R ≈ 500 Ω LED PCI1510 Figure 3−7. Two Sample LED Circuits As indicated, the LED signal is driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
transfers, which is the maximum specified frequency for standard-mode I2C. The serial EEPROM must be located at address A0h. Figure 3−8 illustrates an example application implementing the two-wire serial bus. VCC Serial EEPROM 5V PCI1510 A2 VCCD0 A1 VCCD1 A0 SCL MFUNC4 SDA MFUNC1 Figure 3−8. Serial EEPROM Application Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience.
SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3−10. Serial-Bus Protocol Acknowledge The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.
Slave Address S 1 0 1 0 0 Word Address 0 0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 M A = Slave Acknowledgement S 1 0 1 0 0 Data Byte 2 M Data Byte 1 M M = Master Acknowledgement Data Byte 0 0 0 1 A R/W Restart R/W Data Byte 3 A M P S/P = Start/Stop Condition Figure 3−13. EEPROM Interface Doubleword Data Collection 3.6.
This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 3−8) assumes the 1010b high-address nibble.
Table 3−7 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: • • • 16-bit memory card 16-bit I/O card CardBus cards Table 3−7.
The PC Card Standard describes the power-up sequence that must be followed by the controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the interrupt scheme can be used to notify the host system (see Table 3−8), denoted by the power cycle complete event.
PCI1510 MFUNC1 IRQ3 PIC MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ10 MFUNC5 IRQ11 MFUNC6 IRQ15 Figure 3−14. IRQ Implementation Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the controller. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals.
3.8 Power Management Overview In addition to the low-power CMOS technology process used for the controller, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section. 3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) The controller requires 2.5-V core voltage. The core power can be supplied by the controller itself using the internal LDO-VR.
3.8.5 Suspend Mode The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global reset) signal from the controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the controller in order to minimize power consumption. It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock.
3.8.7 Ring Indicate The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT on the controller can be asserted under any of the following conditions: • A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call.
• • • D3hot − Low-power state. Transition state before D3cold D3cold − PME signal-generation capable. Main power is removed and VAUX is available. D3off − No power and completely non-functional NOTE: In the D0-uninitialized state, the controller does not generate PME and/or interrupts. When the IO_EN and MEM_EN bits (bits 0 and 1) of the command register (PCI offset 04h, see Section 4.4) are both set, the controller switches the state to D0-active.
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake up are as follows: • Preservation of device context. The specification states that a reset must occur during the transition from D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME context registers. • Power source in D3cold if wake-up support is required from this state.
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see section 4.38) is asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted, then the PME context bits are cleared with PRST.
4 PC Card Controller Programming Model This chapter describes the PCI1510 PCI configuration registers that make up the 256-byte PCI configuration header. 4.1 PCI Configuration Registers The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99 compliant as well. Table 4−1 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 4−1.
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, which appear in the signal column; a detailed field description, which appears in the function column; and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field access tags. Table 4−2. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field may be read by software.
4.4 Command Register The command register provides control over the controller interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification. See Table 4−3 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Command 04h Read-only, Read/Write 0000h Table 4−3.
4.5 Status Register The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1b is written to that bit location; a 0b written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 4−4 for a complete description of the register contents.
4.7 PCI Class Code Register The class code register recognizes the controller as a bridge device (06h) and a CardBus bridge device (07h), with a 00h programming interface. Bit 23 22 21 0 0 0 Name Default 20 19 18 17 16 15 14 13 1 1 0 0 0 0 Base class Register: Offset: Type: Default: 0 0 12 11 10 9 8 7 6 1 1 1 0 0 Subclass 0 0 5 4 3 2 1 0 0 0 Programming interface 0 0 0 0 PCI class code 09h Read-only 06 0700h 4.
4.11 BIST Register Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when read. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: BIST 0Fh Read-only 00h 4.12 CardBus Socket/ExCA Base-Address Register The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set.
4.14 Secondary Status Register The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates CardBus-related device information to the host system. This register is very similar to the status register (offset 06h, see Section 4.5); status bits are cleared by writing a 1b. See Table 4−5 for a complete description of the register contents.
4.15 PCI Bus Number Register This register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: PCI bus number 18h Read/Write 00h 4.
4.19 Memory Base Registers 0, 1 The memory base registers indicate the lower address of a PCI memory address range. These registers are used by the controller to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h.
4.21 I/O Base Registers 0, 1 The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the upper 16 bits (31−16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31−2 are read/write.
4.23 Interrupt Line Register The interrupt line register communicates interrupt line routing information. Bit 7 6 5 4 3 2 1 0 Default 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: Interrupt line 3Ch Read/Write FFh 4.24 Interrupt Pin Register The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode, selected through bits 2−1 (INTMODE field) of the device control register (PCI offset 92h, see Section 4.33).
4.25 Bridge Control Register The bridge control register provides control over various bridging functions. See Table 4−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 Register: Offset: Type: Default: Bridge control 3Eh Read-only, Read/Write 0340h Table 4−6. Bridge Control Register Description BIT SIGNAL TYPE 15−11 RSVD R 10 POSTEN RW Write posting enable.
4.26 Subsystem Vendor ID Register The subsystem vendor ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29).
4.29 System Control Register System-level initializations are performed by programming this doubleword register. See Table 4−7 for a complete description of the register contents.
Table 4−7. System Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 15 MRBURSTDN RW Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream. 0 = Downstream memory read burst is disabled 1 = Downstream memory read burst is enabled (default) 14 MRBURSTUP RW Memory read burst enable upstream. When bit 14 is set, the controller allows memory read transactions to burst upstream.
4.30 Multifunction Routing Register The multifunction routing register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be configured for various functions. All multifunction terminals default to the general-purpose input configuration. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial bus EEPROM. See Table 4−8 for a complete description of the register contents.
Table 4−8. Multifunction Routing Register Description (Continued) BIT SIGNAL TYPE FUNCTION Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: 7−4 MFUNC1 NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the MFUNC1 terminal provides the SDA signaling.
4.32 Card Control Register The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See Table 4−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Card control 91h Read-only, Read/Write, Read/Clear 00h Table 4−10. Card Control Register Description BIT TYPE FUNCTION 7 RIENB RW Ring indicate output enable.
4.33 Device Control Register The device control register is provided for PCI1130 compatibility. See Table 4−11 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 1 1 0 0 1 1 0 Register: Offset: Type: Default: Device control 92h Read-only, Read/Write 66h Table 4−11. Device Control Register Description BIT SIGNAL TYPE FUNCTION 7 SKTPWR_LOCK RW Socket power lock bit. When this bit is set to 1b, software cannot power down the PC Card socket while in D3.
4.34 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 00h should be written to it. See Table 4−12 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 1 1 0 0 0 0 0 Register: Offset: Type: Default: Diagnostic 93h Read/Write 60h Table 4−12. Diagnostic Register Description BIT SIGNAL TYPE 7 TRUE_VAL RW 6 RSVD R FUNCTION This bit defaults to 0b.
4.37 Power-Management Capabilities Register This register contains information on the capabilities of the PC Card function related to power management. The CardBus bridge supports the D0, D1, D2, and D3 power states. See Table 4−13 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 Register: Offset: Type: Default: Power-management capabilities A2h Read/Write, Read-only FE12h Table 4−13.
4.38 Power-Management Control/Status Register The power-management control/status register determines and changes the current power state of the controller CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3hot to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3hot to D0 state transition.
4.39 Power-Management Control/Status Register Bridge Support Extensions The power-management control/status register bridge support extensions support PCI bridge specific functionality. See Table 4−15 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 1 1 0 0 0 0 0 0 Register: Offset: Type: Default: Power-management control/status register bridge support extensions A6h Read-only C0h Table 4−15.
4.41 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when events occur that are controlled by the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1b to the corresponding bit location. The status bits in this register do not depend upon the states of corresponding bits in the general-purpose enable register. See Table 4−16 for a complete description of the register contents.
4.42 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the multifunction terminals, MFUNC6−MFUNC0, is configured for GPE signaling. See Table 4−17 for a complete description of the register contents.
4.43 General-Purpose Input Register The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5, MFUNC4, and MFUNC2−MFUNC0. See Table 4−18 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 X X X X X Register: Offset: Type: Default: General-purpose input ACh Read-only 00XXh Table 4−18.
4.45 Serial-Bus Data Register The serial-bus data register is for programmable serial-bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial-bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
4.47 Serial-Bus Slave Address Register The serial-bus slave address register is for programmable serial-bus byte read and write transactions. To write a byte, the serial-bus data register must be programmed with the data, the serial-bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit.
4.48 Serial-Bus Control and Status Register The serial-bus control and status register communicates serial-bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial-bus byte reads to indicate when data is valid in the serial-bus data register. See Table 4−23 for a complete description of the register contents.
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5 ExCA Compatibility Registers The ExCA registers implemented in the PCI1510 controller are register-compatible with the Intel 82365SL−DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1).
signaling are the ExCA interrupt and general control register (ExCA offset 03h/43h/803h, see Section 5.4) and the ExCA card status-change interrupt configuration register (05h/45h/805h, see Section 5.6). Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section.
Table 5−1.
5.1 ExCA Identification and Revision Register The ExCA identification and revision register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). See Table 5−2 for a complete description of the register contents.
5.2 ExCA Interface Status Register The ExCA interface status register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete description of the register contents.
5.3 ExCA Power Control Register The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5−4 and Table 5−5 for a complete description of the register contents. The controller supports both the 82365SL and 82365SL-DF register models. Bits 3−0 (365REV) of the ExCA identification and revision register (ExCA offset 00h, see Section 5.
Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA power control—82365SL-DF support CardBus socket address + 802h; ExCA offset 02h Read-only, Read/Write 00h Table 5−5. ExCA Power Control Register Description—82365SL-DF Support BIT SIGNAL TYPE FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller.
5.4 ExCA Interrupt and General Control Register The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA interrupt and general control CardBus socket address + 803h; ExCA offset 03h Read/Write 00h Table 5−6.
5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0b. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active.
5.6 ExCA Card Status-Change Interrupt Configuration Register The ExCA card status-change interrupt configuration register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. See Table 5−8 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA card status-change interrupt configuration CardBus socket address + 805h; ExCA offset 05h Read/Write 00h Table 5−8.
5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The controller does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0b, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 5−9 for a complete description of the register contents.
5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA I/O window control CardBus socket address + 807h; ExCA offset 07h Read/Write 00h Table 5−10.
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the start address.
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the end address.
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
5.19 ExCA Card Detect and General Control Register The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5−14 for a complete description of the register contents.
5.20 ExCA Global Control Register The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5−15 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA global control CardBus socket address + 81Eh; ExCA offset 1Eh Read-only, Read/Write 00h Table 5−15.
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0b.
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6 CardBus Socket Registers The PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1510 controller provides the CardBus socket/ExCA base-address register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Table 6−1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address.
6.1 Socket Event Register The socket event register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present-state register (CB offset 08h, see Section 6.3) for current status. Each bit in this register can be cleared by writing a 1b to that bit.
6.2 Socket Mask Register The socket mask register allows software to control the CardBus card events that generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (CB offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents.
6.3 Socket Present-State Register The socket present-state register reports information about the socket interface. Write transactions to the socket force event register (CB offset 0Ch, see Section 6.4) are reflected here, as well as general socket interface status. Information about PC Card VCC support and card type is only updated at each insertion.
Table 6−4. Socket Present-State Register (Continued) BIT SIGNAL TYPE 10 5VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V. 0 = 5-V VCC is not supported. 1 = 5-V VCC is supported. R Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software R Data lost.
Table 6−5. Socket Force Event Register Description BIT SIGNAL TYPE FUNCTION 31−28 RSVD R Reserved. Bits 31−28 return 0h when read. 27 FZVSUPPORT W Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video. 26−15 RSVD R Reserved. Bits 26−15 return 000h when read. 14 CVSTEST W Card VS test. When bit 14 is set, the controller re-interrogates the PC Card, updates the socket present-state register (CB offset 08h, see Section 6.
6.5 Socket Control Register The socket control register provides control of the voltages applied to the socket and instructions for the CB CLKRUN protocol. The controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6 for a complete description of the register contents.
6.6 Socket Power-Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Clamping voltage range, VCCP, VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Input voltage range, VI: PCI, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
7.2 Recommended Operating Conditions (see Note 3) OPERATION VCC Core voltage Commercial VCCP PCI and miscellaneous I/O clamp voltage Commercial VCCCB PC Card I/O clamp voltage Commercial MIN NOM MAX 3.3 V 3 3.3 3.6 3.3 V 3 3.3 3.6 4.75 5 5.25 5V 3.3 V PCI VIH† High-level input voltage PC Card 3 3.3 3.6 5V 4.75 5 5.25 3.3 V 0.5 VCCP 5V 0.475 VCCCB 5V 2.
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TERMINALS OPERATION PCI VOH High-level output voltage PC Card IOH = −0.15 mA 0.9 VCC 5V IOH = −0.15 mA 2.4 IOH = −4 mA Low-level output voltage PC Card 0.1 VCC IOL = 6 mA 0.55 3.3 V IOL = 0.7 mA 0.1 VCC 5V IOL = 0.7 mA 0.55 3.6 V 5.25 V VI = VCC −1 3.6 V VI = VCC† VI = VCC† 10 Input terminals VI = GND −1 I/O terminals VI = GND −10 Pullup terminals −330 3.
7.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td (ten, tdis) = delay time, tsu = setup time, and th = hold time.
8 Mechanical Information The PCI1510 is packaged in either a 144-ball GGU or ZGU BGA, 209-ball GVF or ZVF BGA, or a 144-pin PGE package. The following shows the mechanical dimensions for the GGU, GVF, PGE, ZGU, and ZVF packages. GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY 12,10 SQ 11,90 9,60 TYP 0,80 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4073221-2/B 08/00 NOTES: A.
GVF (S−PBGA−N209) NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°−ā 7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147 / C 10/96 NOTES: C. All linear dimensions are in millimeters. D. This drawing is subject to change without notice. E.
ZGU (S−PBGA−N144) PLASTIC BALL GRID ARRAY 12,10 SQ 11,90 9,60 TYP 0,80 N M L K J H G F E D C B A A1 Corner 0,80 1 2 3 4 5 6 7 8 9 10 11 12 13 Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,10 4204394/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration D. This package is lead-free.
ZVF (S−PBGA−N209) PLASTIC BALL GRID ARRAY NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. This package is lead-free.
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