Data Manual 2006 PCIBus Solutions
Printed in U.S.A.
PCI2040 PCI-DSP Bridge Controller Data Manual Literature Number: SCPS048A September 2006 Printed on Recycled Paper
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Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
Section 4 5 iv Title PCI2040 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Vendor and Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6 7 8 Title DSP HPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 C54X Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 HPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 HPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure 2−1 3−1 3−2 3−3 3−4 3−5 6−1 6−2 6−3 6−4 6−5 6−6 6−7 vi Title PCI2040 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2040 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2040 Serial ROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2040 Reset Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 3−1 3−2 3−3 3−4 4−1 4−2 4−3 4−4 4−5 4−6 4−7 4−8 4−9 4−10 4−11 4−12 4−13 4−14 4−15 4−16 4−17 4−18 5−1 5−2 5−3 5−4 5−5 5−6 5−7 Title Card Signal Names by GGU/PGE Pin Number . . . . . . . . . . . . . . . . . . . . . Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminal Functions . . . . .
Table 6−1 6−2 6−3 6−4 viii Title Page C54X HPI Registers Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2 C54X HPI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3 HCNTL0 and HCNTL1 in C6X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−10 C6X HPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction 1.1 Description The TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI) port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus. It provides a PCI bus target interface compliant with the PCI Local Bus Specification.
1−2
110 109 114 113 112 111 118 117 116 115 122 121 120 119 124 123 126 125 130 129 128 127 134 133 132 131 138 137 136 135 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 HCNTL0/GPA3 HCNTL1/GPA4 HR/W/GPA5 HCS3 HCS2 HCS1 HCS0 GND HAD15/GPD15 HAD14/GPD14 HAD13/GPD13 HAD12/GPD12 HAD11/GPD11 V CC HAD10/GPD10 HAD9/GPD9 HAD8/GPD8 V CCH HAD7/GPD7 HAD6/GPD6 HAD5/GPD5 GND HAD4/GPD4 HAD3/GPD3 HAD2/GPD2 HAD1/GPD1 HAD0/GPD0 V CC HINT3 HINT2 HIN
Table 2−1 shows the card signal names and their terminal assignments sorted alphanumerically by the associated GGU package terminal number. Table 2−2 shows the card signal names sorted alphabetically by the signal name and its associated terminal numbers. Table 2−1. Card Signal Names by GGU/PGE Pin Number PIN NO. GGU PGE PIN NO. SIGNAL NAME GGU PGE PIN NO. SIGNAL NAME GGU PGE SIGNAL NAME PIN NO.
Table 2−2. Card Signal Names Sorted Alphabetically PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME GGU PGE GGU PGE G4 20 HBE0/GPA0 B11 111 PCI_AD10 GND E3 10 HBE1/GPA1 A12 110 GND H2 22 HCNTL0/GPA3 B12 108 GND K3 31 HCNTL1/GPA4 B13 GND M4 43 HCS0 GND M6 51 HCS1 GND L9 63 GND K10 77 GND H12 GND GND PIN NO.
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 2−3. Power Supply TERMINAL NO. NAME DESCRIPTION PGE GGU GND 10, 22, 31, 43, 51, 63, 77, 87, 101, 118 C9, D13, E3, H2, H12, K3, K10, L9, M4, M6 Device ground terminals VCC 5, 13, 27, 40, 49, 57, 67, 81, 95, 113, 128 D4, D7, D10, F4, F11, J3, J10, K6, L10, N3, N8 Power supply terminal for core logic (3.
Table 2−4. PCI System Terminal Functions TERMINAL NO.
Table 2−5. Miscellaneous Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION G4 I Global reset. This is a power-on reset to PCI2040 that indicates that a power has been applied to the VCC terminals. GRST resets all register bits in PCI2040. N11 O Power management event. This output indicates PCI power management wake-up events to the host, and requires open-drain, fail-safe signaling per the PCI Bus Power Management Interface Specification.
Table 2−6. Host Port Interface Terminal Functions TERMINAL NO. I/O DESCRIPTION E10 E11 E12 E13 F10 F12 F13 G10 G13 G12 H13 H11 H10 J13 J12 J11 I/O Data. A 16-bit parallel, bidirectional, and 3-state data bus used to access registers on external devices controlled by PCI2040. HAD15 is MSB and HAD0 is LSB. 106 C11 O Read/Write. The PCI2040 drives this signal to 0 on a host port interface for a write and to 1 on a host port interface for a read. HDS/GP_CS 112 A11 O Read strobe/data strobe.
Table 2−7. Compact PCI Hot Swap Interface TERMINAL NO. NAME HSENUM HSLED HSSWITCH PGE GGU 71 N12 72 M12 73 N13 I/O DESCRIPTION O Hot swap ENUM. This is an active low open drain signaling output that is asserted when either bit 7 (INS) or bit 6 (EXT) are set and bit 1 (EIM) is cleared in the CPCI hot swap control and status register (see Section 4.35). This output indicates to the system that an insertion event occurred or that a removal event is about to occur. O Hot swap LED.
3 PCI2040 Functional Description This section covers the functional description for PCI2040. The PCI2040 provides a 32-bit PCI host interface and an interface for 8-bit and 16-bit host port interface (HPI) ports for TI’s C54x and C6x families of DSP processors.
3.2 Accessing Internal PCI2040 Registers PCI configuration space is accessed via PCI configuration read and PCI configuration write cycles. These registers may be accessed using byte, word, or double-word transfers. The PCI2040 provides a set of registers specifically for interfacing with the HPI port. These registers are called the HPI control and status registers (HPI CSRs) (see Section 5), and they may be memory- and I/O-mapped. The HPI CSR memory base address register (see Section 4.
• Diagnostic register − Diagnostic • HPI DSP implementation register − HPI_Imp Byte 0 • HPI data width register − HPI_DW Byte 0 SubClass Word Address 0 RSVD Word Address 16 (10h) BaseClass Word Address 1 RSVD Word Address 17 SubSys Byte 0 Word Address 2 RSVD Word Address 18 SubSys Byte 1 Word Address 3 RSVD Word Address 19 SubSys Byte 2 Word Address 4 RSVD Word Address 20 SubSys Byte 3 Word Address 5 RSVD Word Address 21 GPIO Select Word Address 6 RSVD Word Address 22 RSVD
The HPI DSP implementation register and HPI data width register may be loaded from a serial ROM. Also, these registers are implemented as read/write so intelligent software can load them with the proper values. 3.5.2 DSP Chip Selects The PCI2040 provides four chip select outputs (HCS3−HCS0) that uniquely select each HPI port DSP (or other HPI peripheral) per transaction. This section describes how software encodes the chip select in the PCI address to access a particular DSP interfacing with PCI2040.
• HPI CSR memory base address register (see Section 4.11) is programmed to provide a pointer to the HPI control and status registers (see Section 5). HPI CSR I/O base address register (see Section 4.32) can also be programmed to give I/O access. • Control space base address register (see Section 4.12) is programmed and 32K bytes of memory are allocated. • The PCI command register (see Section 4.3) is programmed to allow PCI2040 to respond to memory and I/O cycles.
3.6 General-Purpose I/O Interface The PCI2040 has six general-purpose input/output (GPIO) terminals for design flexibility, and these terminals reside in the VCCP signaling environment. GPIO5−GPIO0 default to inputs, but may be programmed to be outputs via the GPIO direction control register (see Section 4.23). When GPIOx is selected as an input, the logical value of the data input on GPIOx is reported through the GPIO input data register (see Section 4.22).
As a side note, HINT is generated when the HINT bit is set in the HPI control register. See Section 6, DSP HPI Overview, for a description of the DSPs HPI control register. 3.7.3 HPI Error Interrupts and HPI Error Reporting Bit 30 (HPIError) in the interrupt event register (see Section 5.1), set upon serious error conditions on the HPI interface, allows software to gracefully terminate communication with an HPI device. Bit 30 is set when any of the bits in the HPI error report register (see Section 5.
3.8.1 PCI Power Management Register Interface PCI2040 is PCI Bus Power Interface Management Specification Revision 1.0 and 1.1 compliant. By default, PCI2040 provides the PCI power management PM 1.0 register set which is documented in Section 4.30. PCI2040 may be programmed to provide a PCI PM 1.1 register set by setting bit 4 (PM11_EN) of the miscellaneous control register to 1 (see Section 4.26). The PCI power management register changes required to provide PCI PM 1.
• 0x48 – GPIO interrupt type register (all implemented bits) • 0x4C – Miscellaneous control register (all implemented bits) • 0x4C – Diagnostic register (all implemented bits) • 0x52 – Power management capabilities register (D3cold_PMESupport) • 0x54 – Power management control/status register (PMCSR.PME_STS, PMCSR.
and bit 1 (EIM). Since no HSSWITCH status is provided in the CPCI hot swap control and status register, PCI2040 provides bit 8 (HSSWITCH_STS) in the miscellaneous control register (see Section 4.26). HSENUM is an active low open drain output that is asserted when either bit 7 (INS) or bit 6 (EXT) are set and bit 1 (EIM, the HSENUM mask bit) is cleared.
3.11 Example Transactions on the General-Purpose Bus This section describes some example transactions on the GP bus. 3.11.1 General-Purpose Bus Word Write The first diagram, Figure 3−4, depicts a word (16−bits) write to a device residing on the GP bus. The event flow is as follows: 1. All signals are in a deasserted state except for GP_RDY. The PCI2040 is driving the address and data bus to a stable but unknown value. 2. The GP_CS is driven low.
5. The transaction completes by deasserting the GP_CS. The PCI2040 starts driving the GP address and data bus with stable values. 1 2 3 4 5 PCI_CLK GP_RST GP_CS GPD[15:0] GPA[5:0] ZZZZ BBAA 2C GP_WR GP_RD GP_RDY Figure 3−5.
4 PCI2040 Programming Model This section describes the PCI2040 PCI configuration registers that make up the 256-byte PCI configuration header. A brief description is provided for each register, followed by the register offset and a default state for each register. The bit table also has reserved fields that contain read-only reserved bits. These bits return 0s when read. 4.
A bit description table is typically included that indicates bit field names, a detailed field description, and field access tags. Table 4−2 describes the field access tags. Table 4−2. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field may be read by software. W Write Field may be written by software to any value. S Set C Clear U Update MEANING Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of one. Writes of 0 have no effect.
4.3 PCI Command Register The system software accesses the status and command registers for error recovery, diagnostic, and control. This register is provided to enable coarse control over a device’s ability to generate and respond to PCI cycles.
4.4 PCI Status Register The PCI status register provides the host information to the host system. A bit in this register is reset when 1 is written to it. A 0 written to a bit has no effect. Bit 15 14 13 12 11 10 9 8 Name Type Default 7 6 5 4 3 2 1 0 PCI status RC RC R R RC R R R R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Register: Type: Offset: Default: PCI status Read-only, Read/Write to Clear 06h 0210h Table 4−4.
4.6 Class Code The class code register categorizes the function as a bridge device (06h), and another bridge device (80h) with a standard programming interface (00h). Subclass and base class are loaded via serial ROM.
4.9 Header Type Register The header type register returns 00h when read, indicating that the PCI2040 configuration space adheres to the standard PCI header and it is a single function device. Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name Header type Register: Type: Offset: Default: Header type Read-only 0Eh 00h 4.10 BIST Register The PCI2040 does not support built-in-self-test (BIST); therefore, this register returns 00h when read.
4.11 HPI CSR Memory Base Address Register The HPI CSR memory base address register provides a method of allowing the host to map the PCI2040’s HPI CSR registers into host memory space.
4.12 Control Space Base Address Register The control space base address register allows the host to map the PCI2040’s 32K bytes of control space into host memory.
4.13 GP Bus Base Address Register The GP bus base address register is used by the PCI2040 to communicate with a device on the GP bus. This 32−bit register allows software to assign a memory window for the GP bus anywhere in the 4-Gbyte address space. This window has a 256-byte granularity which means the lower 8 bits of this register default to 0 and are read-only. This register is controlled via bit 5 (GP_EN) in the miscellaneous control register (see Section 4.
4.15 Subsystem ID Register The subsystem ID register is used for system identification purposes and may be required for certain operating systems. This register is read-only or read/write depending on the value of bit 0 (SUBSYSRW) in the miscellaneous control register (see Section 4.26). When bit 0 (SUBSYSRW) is 0, this register is read/write and when bit 0 is 1, this register is read-only. This register may be loaded from the serial ROM.
4.18 Interrupt Pin Register The interrupt pin register tells which interrupt the device uses. This register is hardwired to 01h in the PCI2040 to indicate that INTA will be used. Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Name Interrupt pin Register: Type: Offset: Default: Interrupt pin Read-only 3Dh 01h 4.19 MIN_GNT Register This register specifies the length of the burst period for the device needs in 0.25 µsec units.
4.21 GPIO Select Register The GPIO select register is used to program the GPIOx terminal functions. Bit 7 6 5 4 3 2 1 0 Type R R RU RU RW RW RW RW Default 0 0 0 0 0 0 0 0 Name GPIO select Register: Type: Offset: Default: GPIO select Read/Update/Write 44h 00h Table 4−8. GPIO Select Register BIT FIELD NAME TYPE 7−6 RSVD R 5 4 3 4−12 GPIO5Pin GPIO4Pin GPIO3Pin DESCRIPTION Reserved. Bits 7 and 6 return 0s when read. RU GPIO5 pin.
4.22 GPIO Input Data Register The GPIO input data register reflects the state of the GPIO pins, and defaults to an unknown value. Bit 7 6 5 4 Type R R R R Default 0 0 X X Name 3 2 1 0 R R R R X X X X GPIO input data Register: Type: Offset: Default: GPIO input data Read-only 45h XXh Table 4−9. GPIO Input Data Register BIT FIELD NAME TYPE 7−6 RSVD R Reserved. Bits 7 and 6 return 0s when read. DESCRIPTION 5−0 GPIO[5:0] Pin State R GPIO5−GPIO0 pin state.
4.24 GPIO Output Data Register The GPIO output data register contains the output data for any selected output pin. Bit 7 6 5 4 Type R R RW RW Default 0 0 0 0 Name 3 2 1 0 RW RW RW RW 0 0 0 0 2 1 0 GPIO output data Register: Type: Offset: Default: GPIO output data Read-only, Read/Write 47h 00h Table 4−11. GPIO Output Data Register BIT FIELD NAME TYPE 7−6 RSVD R 5−0 GPIO[5:0] Output data RW DESCRIPTION Reserved. Bits 7 and 6 return 0s when read.
4.26 Miscellaneous Control Register The miscellaneous control register controls various miscellaneous functions. Bit 15 14 13 12 11 10 9 RU RCU R R R R R R 0 0 0 0 0 0 0 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R RW RW RW RW RW RW 0 0 0 0 1 1 1 1 Miscellaneous control Register: Type: Offset: Default: Miscellaneous control Read/Clear/Update/Write 4Ch 000Fh Table 4−13.
4.27 Diagnostic Register The diagnostic register is provided for test purposes and should not be accessed during normal operation. Bit 7 6 5 4 3 2 1 0 RW R R RW RW R RW RW 0 0 0 0 0 0 0 0 Name Type Default Diagnostic Register: Type: Offset: Default: Diagnostic Read/Write 4Fh 00h Table 4−14. Diagnostic Register BIT FIELD NAME TYPE 7 TRUE_VAL RW DESCRIPTION 6−5 RSVD R 4 DIAG4 RW Diagnostic RETRY_DIS. Delayed transaction disable.
4.29 PM Next-Item Pointer Register The PM next-item pointer register provides a pointer into the PCI configuration header where the CPCI hot swap control and status register (HS_CSR) resides. The PCI header at 5Ch provides the hot swap register. If bit 3 (HSEN) in the miscellaneous control register (see Section 4.26) is 0, then the PM next-item pointer register returns 00h when read indicating the end of the extended capability list.
4.31 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI2040. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. All PCI registers will be reset as a result of a D3hot-to-D0 state transition. TI specific registers, PCI power management registers, and the legacy base address register are not reset.
4.32 HPI CSR I/O Base Address Register The PCI2040 supports the index/data scheme of accessing the HPI CSR registers. An address written to this register is the address for the index register and the address + 1 is the data address. The base address can be mapped anywhere in 32-bit I/O space on a word boundary except at address 0x0000; hence, bit 0 is read-only, returning 0 when read. The HPI CSR I/O base address is only meaningful when a nonzero value is written into this register.
4.34 HS Next-Item Pointer Register The HS next-item pointer register is used to indicate the next item in the linked list of the PCI extended capabilities. This register returns 00h indicating no additional capabilities are supported. Bit 7 6 5 Name 4 3 2 1 0 HS next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: HS next-item pointer Read-only 5Dh 00h 4.
5 HPI Control and Status Registers This section covers the PCI2040 HPI control and status register (HPI CSR) space. The PCI2040 allows software to access the HPI configuration through either memory or I/O address space. The memory base address is programmable via the HPI CSR base address register (PCI offset 10h). The I/O base address is programmable via the HPI CSR I/O base address register (PCI offset 58h). Table 5−1.
5.1 Interrupt Event Register The interrupt event register reflects the state of the various PCI2040 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register.
5.2 Interrupt Mask Register The interrupt mask register is used to enable the various PCI2040 interrupt sources. Reads from either the set register or the clear register always return interrupt mask. In all cases, except masterIntEnable (bit 31), the enables for each interrupt event align with the event register bits detailed in Table 5−2.
5.3 HPI Error Report Register The HPI error report register reflects the state of errors on the HPI interfaces. If any bits in this register are set, then the PCI2040 sets bit 30 (HPIError) in the interrupt event register (see Section 5.1). Software can set the bits in this register for diagnostics.
5.5 HPI DSP Implementation Register The HPI DSP implementation register is used to indicate the presence of implemented DSPs on the HPI interface and is loaded from the serial ROM. Bit 15 14 13 12 11 10 9 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R RWU RWU RWU RWU 0 0 0 0 0 0 0 HPI DSP implementation Register: Type: Offset: Default: HPI DSP implementation Read/Write/Update 16h 0000h Table 5−6.
5−6
6 DSP HPI Overview This section gives an overview of the DSP host port interface (HPI). Refer to the C54x/C6x data sheets for complete HPI details. 6.1 C54X Host Port Interface The HPI is an 8-bit parallel port used to interface a host device or host processor to a C54x DSP. Information is exchanged between the DSP and the host device through on-chip C54x memory that is accessible by both the host and the DSP.
• HPI data register (HPID). This register is directly accessible by the host and contains the data that was read from the HPI memory if the current access is a read, or the data that will be written to the HPI memory if the current access is a write. The two control inputs, HCNTL1 and HCNTL0, indicate which internal register is being accessed as shown below. Table 6−1. C54X HPI Registers Access Control HCNTL1 HCNTL0 DESCRIPTION 0 0 PCI2040 read/write to HPI control register.
6.2 C54X HPI Control Register Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 C54X HPI control Host Type R R R R R/W W R R/W R R R R R/W W R R/W DSP Type R R R R R/W − R/W − R R R R R/W − R/W − Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6−2.
A C54x interrupt is generated when the host writes a 1 to the DSPINT bit (bit 2) of the HPI control register. This interrupt can be used to wake up DSP from IDLE. The host and C54x always read this bit as 0. Once a 1 is written to DSPINT by the host, a 0 need not be written before generating another interrupt. A DSP write or writing a 0 to this bit has no effect.
6.2.6 HPI Memory Access During Reset The DSP is not operational during reset, but the host can access the HPI hereby allowing the program or data to be downloaded to the HPI memory. However to use this capability, it is convenient for the host to control the DSP’s reset. Initially, the host stops accessing the HPI at least six DSP periods before driving the DSP reset line low. The HPI mode is set to HOM during the reset and the host can start accessing the HPI after four DSP periods.
1 2 3 4 5 6 7 8 PCI_CLK HRST0 HCS0 HAD[15:0] XXAA XXBB HCNTL0 HCNTL1 HWIL HDS HR/W HRDY5X0 Figure 6−2. Word Write To HPID Without Auto-Increment Enabled 6.2.7.2 PCI Word Read The second example outlined in Figure 6−3 shows how the PCI2040 translates a word read on the PCI bus with a PCI address of FFEF5800h. The event flow is as follows: 1. The host port is idle. 2.
1 2 3 4 5 6 7 8 9 PCI_CLK HRST2 HCS2 HAD[15:0] ZZZZ ZZAA ZZBB HCNTL0 HCNTL1 HWIL HDS HR/W HRDY5X2 Figure 6−3. Word Write From HPID Without Auto-Increment Enabled 6.2.7.3 PCI Double Word Write In the third example depicted in Figure 6−4, a PCI write transaction with address FFEF3800, byte enables of 0000b, and a single data phase occurs of the PCI bus. The data is DDCCBBAAh. The PCI2040 takes this PCI transaction and translates it to an 8-bit host port transaction.
12. Same as Step 3. 13. Same as Step 4. 14. Same as Step 5 except the data latched is DDh and the HCS1 is deasserted indicating the end of the transaction. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PCI_CLK HRST1 HCS1 HAD[15:0] XXAA XXBB XXCC XXDD HCNTL0 HCNTL1 HWIL HDS HR/W HRDY5X1 Figure 6−4. Doubleword Write To HPID Without Auto-Increment Enabled 6.2.7.4 PCI Double Word Read The fourth example is very similar to the third example. In this case the transaction is a PCI doubleword read.
6.3.2 Address/Data Bus The HPI provides 32-bit data to the CPU with a 16-bit wide parallel external interface (C54x has 8-bit wide external interface). All transfers with the host consist of two consecutive half-words. On the HPI data register data write access, HBE1 and HBE0 (byte enables) select the bytes in 32-bit word to be written. For the HPI address register, HPI control register, and HPI data register read, byte enables are not used.
6.3.5 C6X HPI Registers C6x contains HPI address, HPI control, and HPI data registers, and these registers have a 32-bit structure as opposed to the 16-bit structure in the C54x HPI interface. The HCNTL0/1 control access to the HPI registers as described below. Note that it is different from C54x. Table 6−3. HCNTL0 and HCNTL1 in C6X Bit 31 HCNTL1 HCNTL0 0 0 PCI2040 read/write to HPI control register 0 1 PCI2040 read/write to HPI address register 1 0 PCI2040 read/write to HPI data register.
Table 6−4. C6X HPI Control Register BIT FIELD NAME 31−21 RSVD HOST TYPE DSP TYPE R R FUNCTION Reserved. Bits 31−21 return 0s when read. 20 FETCH Host fetch request. The value read by the host or the CPU is always 0. Only host can write to this register. When host writes 1 to this bit, it requests a fetch into HPI data register of the word at the word pointed to by HPI address register. Note that the value of 1 is never actually written to this bit. 19 HRDY Ready signal to host.
6.3.7 Host Access Sequence The host access sequence in C6x is similar to C54x except for the HPI data register write. The host begins accessing HPI by initializing the HPI control register, then by initializing the HPI address register, and then by writing data to or reading data from the HPI data register. Reading or writing to the HPI data register initiates an internal cycle that transfers the desired data between the HPI data register and DMA auxiliary channel.
1 2 3 4 5 6 7 8 PCI_CLK HRST0 HCS0 HAD[15:0] BBAA DDCC HCNTL0 HCNTL1 HWIL HDS HR/W HBE0 HBE1 HRDY6X0 Figure 6−6. Double Word Write To HPID Without Auto-Increment Selected 1 2 3 4 5 6 7 8 PCI_CLK HRST0 HCS0 HAD[15:0] BBAA DDCC HCNTL0 HCNTL1 HWIL HDS HR/W HBE0 HBE1 HRDY6X0 Figure 6−7.
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7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Supply voltage range, VCCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Recommended Operating Conditions (see Note 3) OPERATION VCC Core voltage Commercial VCCP PCI I/O voltage Commercial VCCH HPI I/O voltage Commercial VIH† High-level input voltage Low-level input voltage VI Input voltage VO‡ Output voltage tt Input transition time (tr and tf) PCI MAX UNIT V 3 3.3 3.6 3.3 V 3 3.3 3.6 5V 3 5 5.25 3.3 V 3 3.3 3.6 5V 3 5 5.25 5V HPI VIL† NOM 3.3 V 3.3 V PCI MIN 0.5 VCCP 2 2 VCCP VCCP 3.3 V 0 VCCH 0.3 VCCP 5V 0 0.
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER PINS OPERATION 3.3 V PCI VOH High-level output voltage† 5V HPI‡ Miscellaneous§ 3.3 V PCI VOL IOZH Low-level output voltage 3-state output, high-impedance state current TEST CONDITIONS IOH = −0.5 mA MIN IOH = −2 mA 2.4 IOH = −8 mA VCC−0.6 IOH = −4 mA VCC−0.6 IOL = 1.5 mA MAX UNIT 0.9 VCC V 0.1 VCC IOL = 6 mA 0.55 HPI‡ IOL = 8 mA 0.5 Miscellaneous§/ Failsafe¶ IOL = 4 mA 0.
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8 Mechanical Information The PCI2040 is packaged in either a 144-ball GGU BGA or a 144-pin PGE package. The following shows the mechanical dimensions for the GGU and PGE packages. GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY 12,10 SQ 11,90 9,60 TYP 0,80 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4073221/A 11/96 NOTES: A. All linear dimensions are in millimeters. B.
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°−ā 7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
