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2003 PCI Bus Solutions

Data Manual

SCPS053B

Summary of content (75 pages)

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Data Manual 2003 PCI Bus Solutions SCPS053B
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.
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5 iv 3.16.1 Secondary Clock Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Transaction Forwarding Control . . . . . . . . . . . . . . . . . . . . . . . 3.17 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17.1 Behavior in Low-Power States . . . . . . . . . . . . . . . . . . . . . . . . Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor ID Register . . . . . . . . . .
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6 7 5.7 GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Secondary Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 P_SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Power-Management Capability ID Register . . . . . . . . . . . . . . . . . . . . . 5.11 Power-Management Next-Item Pointer Register . . . . . . . . . . . . . . . . . 5.
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List of Illustrations Figure 2–1 2–2 2–3 3–1 3–2 3–3 3–4 3–5 3–6 6–1 6–2 6–3 6–4 vi Title Page PCI2050 GHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 PCI2050 ZHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 PCI2050 PDV Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 3–1 3–2 3–3 3–4 3–5 3–6 4–1 4–2 4–3 4–4 4–5 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 5–13 Title 208-Terminal PDV Signal Names Sorted by Terminal Number . . . . . . . . 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number . . . Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1 Introduction 1.1 Description The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high-performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.
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1.3 Related Documents • Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0) • IEEE Standard Test Access Port and Boundary-Scan Architecture • PCI Local Bus Specification (Revision 2.2) • PCI-to-PCI Bridge Specification (Revision 1.1) • PCI Bus Power Management Interface Specification (Revision 1.1) • PICMG CompactPCI Hot-Swap Specification (Revision 1.0) 1.4 Trademarks CompactPCI is a trademark of PICMG – PCI Industrial Computer Manufacturers Group, Inc.
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2 Terminal Descriptions The PCI2050 device is packaged either in a 209-terminal GHK MicroStar BGA a 209-terminal ZHK MicroStar BGA, or a 208-terminal PDV package. Figure 2–1 is a GHK-package terminal diagram. Figure 2–2 is a ZHK-package terminal diagram. Figure 2–3 is a PDV-package terminal diagram. Table 2–1 lists terminals on the PDV packaged device in increasing numerical order, with the signal name and corresponding GHK terminal number for each.
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157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PCI2050 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VCC S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_GNT0 S_GNT1 GND S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 GND S
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Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number PDV NO. 1 SIGNAL NAME PDV NO. SIGNAL NAME PDV NO. SIGNAL NAME PDV NO.
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Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number (Continued) PDV NO. 2–4 SIGNAL NAME PDV NO. SIGNAL NAME PDV NO. SIGNAL NAME PDV NO.
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Table 2–2. 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number GHK/ZHK NO. A4 SIGNAL NAME GHK/ZHK NO. SIGNAL NAME GHK/ZHK NO. SIGNAL NAME GHK/ZHK NO.
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Table 2–2. 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number (Continued) GHK/ZHK NO. 2–6 SIGNAL NAME GHK/ZHK NO. SIGNAL NAME GHK/ZHK NO. SIGNAL NAME T1 GND U13 P_AD15 V12 P_LOCK T19 VCC GND U14 P_AD12 V13 U5 U15 V14 U6 GND V5 VCC P_AD28 U7 P_C/BE3 V6 P_AD26 U8 P_AD22 V7 P_IDSEL W5 GHK/ZHK NO.
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Table 2–3. Signal Names Sorted Alphabetically SIGNAL NAME PDV NO. GHK/ZHK NO. BPCCE 44 P2 GND 12 GND 20 GND GND SIGNAL NAME PDV NO. GHK/ZHK NO. NC 125 L17 G3 P_AD0 122 J2 P_AD1 121 31 L3 P_AD2 37 M6 P_AD3 GND 48 P6 GND 52 GND 54 GND 59 U6 P_AD7 GND 66 W7 P_AD8 GND 72 V9 P_AD9 107 GND 78 U10 P_AD10 GND 86 W12 P_AD11 GND 94 P13 GND 100 P14 GND 104 SIGNAL NAME PDV NO. GHK/ZHK NO.
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Table 2–3. Signal Names Sorted Alphabetically (Continued) SIGNAL NAME PDV NO. GHK/ZHK NO. S_VCCP TCK 135 J17 133 J19 TDI 129 K18 TDO 130 K17 TMS 132 K14 TRST 134 J18 VCC VCC 1 D1 26 K3 34 M1 40 N2 VCC VCC 2–8 SIGNAL NAME PDV NO. GHK/ZHK NO. VCC VCC 51 R3 53 W4 VCC VCC 56 P7 62 W6 VCC VCC 69 V8 75 P9 VCC VCC 81 W11 91 W13 VCC VCC 97 R13 103 U15 SIGNAL NAME PDV NO. GHK/ZHK NO. VCC VCC 105 T19 108 N14 VCC VCC 114 P19 SIGNAL NAME PDV NO.
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The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see Table 2–4 through Table 2–12). The terminal numbers are listed for convenient reference. Table 2–4. Primary PCI System Terminals TERMINAL NAME PDV NO. GHK/ZHK NO. I/O DESCRIPTION P_CLK 45 N5 I Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals are sampled at rising edge of P_CLK. I PCI reset.
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Table 2–6. Primary PCI Interface Control Terminals TERMINAL NAME PDV NO. GHK/ZHK NO. I/O DESCRIPTION P_DEVSEL 84 P11 I/O Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI master on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target responds before time-out occurs, then the bridge terminates the cycle with a master abort. P_FRAME 80 P10 I/O Primary cycle frame.
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Table 2–7. Secondary PCI System Terminals TERMINAL I/O DESCRIPTION N6 N3 N1 M5 M3 M2 L5 L6 L2 L1 O Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each secondary bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input. 21 J3 I Secondary PCI bus clock input. This input synchronizes the PCI2050 to the secondary bus clocks. S_CFN 23 J6 I Secondary external arbiter enable.
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Table 2–8. Secondary PCI Address and Data Terminals TERMINAL NAME PDV NO. GHK/ZHK NO.
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Table 2–9. Secondary PCI Interface Control Terminals TERMINAL NAME PDV NO. GHK/ZHK NO. I/O DESCRIPTION S_IRDY 177 C11 I/O Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted. S_LOCK 172 C12 I/O Secondary PCI bus lock.
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Table 2–10. Miscellaneous Terminals TERMINAL PDV NO. NAME GHK/ZHK NO. I/O DESCRIPTION Bus/power clock control management terminal. When signal BPCCE is tied high and when the PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When tied low, placing the PCI2050 in the D3 power state has no effect on the secondary bus clocks.
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3 Feature/Protocol Descriptions The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3–1 shows a simplified block diagram of a typical system implementation using the PCI2050. Host Bus CPU Memory Host Bridge PCI Device PCI Device PCI Bus 0 PCI Option Card PCI2050 PCI Option Card PCI Bus 2 PCI Bus 1 PCI2050 PCI Device PCI Device (Option) PCI Option Slot Figure 3–1. System Block Diagram 3.
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3.2 PCI Commands The bridge responds to PCI bus cycles as a PCI target device based on internal register settings and on the decoding of each address phase. Table 3–1 lists the valid PCI bus cycles and their encoding on the command/byte enable (C/BE) bus during the address phase of a bus cycle. Table 3–1.
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bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL, and the configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles by accessing internal registers from the bridge configuration header (see Table 4–1). Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles based on the bus number of the destination bus.
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Table 3–2.
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PCI2050 S_CLK S_CLKOUT9 S_CLKOUT8 PCI Device S_CLKOUT2 PCI Device S_CLKOUT1 PCI Device S_CLKOUT0 PCI Device Figure 3–5. Secondary Clock Block Diagram 3.6 Bus Arbitration The PCI2050 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus arbitration. Nine secondary bus requests and nine secondary bus grants are provided on the secondary of the PCI2050. Ten potential initiators, including the bridge, can be located on the secondary bus.
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bus grant terminals. Including the bridge, there are a total of ten potential secondary bus masters. These request and grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ8–S_REQ1 and S_GNT8–S_GNT1 are placed in a high-impedance mode. 3.6.3 External Secondary Bus Arbitration An external secondary bus arbiter can be used instead of the PCI2050 internal bus arbiter.
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3.8.4 Master Abort on Posted Writes If bit 4 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and a posted write transaction results in a master abort, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 4 of the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.5 Master Delayed Write Time-Out If bit 5 in the P_SERR event disable register (PCI offset 64h, see Section 5.
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30 µs and 993 µs, respectively). The PCI Local Bus Specification recommends that a bridge wait 215 PCI clocks before discarding the transaction data or status. The PCI2050 implements a discard timer for use in delayed transactions. After a delayed transaction is completed on the destination bus, the bridge may discard it under two conditions.
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Table 3–3. Configuration via MS0 and MS1 MS0 MS1 MODE 0 0 CompactPCI hot-swap friendly PCI Bus Power Management Interface Specification Revision 1.1 HSSWITCH/GPIO(3) functions as HSSWITCH 0 1 CompactPCI hot-swap disabled PCI Bus Power Management Interface Specification Revision 1.1 HSSWITCH/GPIO(3) functions as GPIO(3) 1 X Intel compatible No cPCI hot swap PCI Bus Power Management Interface Specification Revision 1.0 3.
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3.15 JTAG Support The PCI2050 implements a JTAG test port based on IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The JTAG test port consists of the following: • • • • • A 5-wire test access port A test access port controller An instruction register A bypass register A boundary-scan register 3.15.
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Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO.
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Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO.
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Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO.
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3.16 GPIO Interface The PCI2050 implements a four-terminal general-purpose I/O interface. Besides functioning as a general-purpose I/O interface, the GPIO terminals can be used to read in the secondary clock mask and to stop the bridge from accepting I/O and memory transactions. 3.16.1 Secondary Clock Mask The PCI2050 uses GPIO0, GPIO2, and MSK_IN to shift in the secondary clock mask from an external shift register. A secondary clock mask timing diagram is shown in Figure 3–6.
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3.17 PCI Power Management The PCI Power Management Specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power management states, which result in varying levels of power savings.
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4 Bridge Configuration Header The PCI2050 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Specification 1.1. Table 4–1 shows the PCI configuration header, which includes the predefined portion of the bridge configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading. Table 4–1.
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4.1 Vendor ID Register This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this device. The vendor ID assigned to TI is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Type: Offset: Default: Vendor ID Read-only 00h 104Ch 4.
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4.3 Command Register The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4–2 describes the bit functions in the command register.
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4.4 Status Register The status register provides device information to the host system. Bits in this register are cleared by writing a 1 to the respective bit; writing a 0 to a bit location has no effect. Table 4–3 describes the status register.
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4.5 Revision ID Register The revision ID register indicates the silicon revision of the PCI2050. Bit 7 6 5 4 Name 3 2 1 0 Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Revision ID Read-only 08h 00h (reflects the current revision of the silicon) 4.6 Class Code Register This register categorizes the PCI2050 as a PCI-to-PCI bridge device (0604h) with a 00h programming interface.
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4.8 Primary Latency Timer Register The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is deasserted.
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4.11 Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read.
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4.14 Secondary Bus Number Register The secondary bus number register indicates the secondary bus number to which the bridge is connected. The PCI2050 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the secondary bus are converted to type 0 configuration cycles.
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4.17 I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15–AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of the defined I/O address range is aligned on a 4K-byte boundary.
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4.19 Secondary Status Register The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective bit.
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4.20 Memory Base Register The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 0s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
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4.23 Prefetchable Memory Limit Register The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
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4.25 Prefetchable Limit Upper 32 Bits Register The prefetchable limit upper 32 bits register plus the prefetchable memory limit register defines the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The prefetchable limit upper 32 bits register should be programmed to all zeros when 32-bit addressing is being used.
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4.28 Capability Pointer Register The capability pointer register provides the pointer to the PCI configuration header where the PCI power management register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The capability pointer register is read-only and returns DCh when read, indicating the power management registers are located at PCI header offset DCh.
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4.31 Interrupt Pin Register The bridge default state does not implement any interrupt terminals. Reads from bits 7–0 of this register return 0s. Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name Interrupt pin Register: Type: Offset: Default: Interrupt pin Read-only 3Dh 00h 4.
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Table 4–5. Bridge Control Register Description (continued) BIT TYPE FUNCTION 5 R/W Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. If this bit is set, the posted write transaction has completed on the requesting interface, and SERR enable (bit 8) of the command register (offset 04h, see Section 4.3) is 1, then P_SERR is asserted when a master abort occurs.
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5 Extension Registers The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h–FFh in PCI configuration space in the PCI2050). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge. Mapping of the extension registers is contained in Table 4–1. 5.
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5.2 Extended Diagnostic Register The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset both the PCI2050 and the secondary bus. Bit 7 6 5 Name 4 3 2 1 0 Extended diagnostic Type R R R R R R R W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Extended diagnostic Read-only, Write-only 41h 00h Table 5–2. Extended Diagnostic Register Description 5–2 BIT TYPE FUNCTION 7–1 R Reserved.
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5.3 Arbiter Control Register The arbiter control register is used for the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The PCI2050 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier.
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5.4 P_SERR Event Disable Register The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events are enabled by default. Bit 7 6 5 Name 4 3 2 1 0 P_SERR event disable Type R R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: P_SERR event disable Read-only, Read/Write 64h 00h Table 5–4. P_SERR Event Disable Register Description 5–4 BIT TYPE FUNCTION 7 R 6 R/W Master delayed read time-out.
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5.5 GPIO Output Data Register The GPIO output data register controls the data driven on the GPIO terminals configured as outputs. If both an output-high bit and an output-low bit are set for the same GPIO terminal, the output-low bit takes precedence. The output data bits have no effect on a GPIO terminal that is programmed as an input.
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5.7 GPIO Input Data Register The GPIO input data register returns the current state of the GPIO terminals when read. Bit 7 6 5 Name 4 3 2 1 0 GPIO input data Type R R R R R R R R Default X X X X 0 0 0 0 Register: Type: Offset: Default: GPIO input data Read-only 67h X0h Table 5–7. GPIO Input Data Register Description 5–6 BIT TYPE FUNCTION 7–4 R GPIO3–GPIO0 input data. These four bits return the current state of the GPIO terminals. 3–0 R Reserved.
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5.8 Secondary Clock Control Register The secondary clock control register is used to control the secondary clock outputs. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Secondary clock control Type R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Secondary clock control Read-only, Read/Write 68h 0000h Table 5–8.
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5.9 P_SERR Status Register The P_SERR status register indicates what caused a SERR event on the primary interface. Bit 7 6 5 4 Name 3 2 1 0 P_SERR status Type R R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: P_SERR status Read-only Read/Write 6Ah 00h Table 5–9. P_SERR Status Register Description BIT TYPE FUNCTION 7 R 6 R/W Master delayed read time-out.
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5.11 Power-Management Next-Item Pointer Register The power-management next-item pointer register is used to indicate the next item in the linked list of PCI power-management capabilities. The next-item pointer returns E4h in CompactPCI mode, indicating that the PCI2050 supports more than one extended capability, but in all other modes returns 00h, indicating that only one extended capability is provided.
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5.13 Power-Management Control/Status Register The power-management control/status register determines and changes the current power state of the PCI2050. The contents of this register are not affected by the internally generated reset caused by the transition from D3hot to D0 state.
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5.14 PMCSR Bridge Support Register The PMCSR bridge support register is required for all PCI bridges and supports PCI-bridge-specific functionality. Bit 7 6 5 4 Type R R R R Default X X 0 0 Name 3 2 1 0 R R R R 0 0 0 0 PMCSR bridge support Register: Type: Offset: Default: PMCSR bridge support Read-only E2h X0h Table 5–12. PMCSR Bridge Support Register Description BIT 7 6 TYPE FUNCTION Bus power control enable. This bit returns the value of the MS1/BCC input.
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5.16 HS Capability ID Register The HS capability ID register identifies the linked list item as the register for cPCI hot-swap capabilities. The register returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and the value. In Intel-compatible mode, this register is read-only and defaults to 00h.
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5.18 Hot-Swap Control Status Register The hot-swap control status register contains control and status information for cPCI hot swap resources. Bit 7 6 5 Name 4 3 2 1 0 Hot swap control status Type R R R R R/W R R/W R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Hot-swap control status Read-only, Read/Write E6h 00h Table 5–13. Hot-Swap Control Status Register Description BIT TYPE FUNCTION 7 R ENUM insertion status.
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6 Electrical Characteristics 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.6 V S_VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V P_VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.
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6.3 Recommended Operating Conditions for PCI Interface OPERATION VCC Core voltage Commercial P_V P VCCP PCI supply voltage Commercial S_V S VCCP PCI supply voltage Commercial VI Input voltage VO† Output voltage VIH‡ High le el input inp t voltage oltage High-level CMOS compatible VIL‡ Low level input voltage Low-level CMOS compatible MIN NOM MAX 3 3.3 3.6 3.3 V 3.3 V 5V 3 3.3 3.6 4.75 5 5.25 3 3.3 3.6 4.75 5 5.25 3.3 V 5V 3.3 V 0 5V 0 3.3 V 0 5V 0 3.
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6.
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6.7 Parameter Measurement Information LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL From Output Under Test Test Point VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.
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6.8 PCI Bus Parameter Measurement Information twH twL 2V 2 V min Peak-to-Peak 0.8 V tf tr tc Figure 6–2. PCLK Timing Waveform PCLK tw RSTIN tsu Figure 6–3. RSTIN Timing Waveforms PCLK 1.5 V tpd PCI Output tpd 1.5 V Valid ton PCI Input toff Valid tsu th Figure 6–4.
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7 Mechanical Data GHK (S-PBGA-N209) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 0,80 W V U T R P N M L K J H G F E D C B A 1 3 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4145273–2/B 12/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments.
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ZHK (S-PBGA-N257) PLASTIC BALL GRID ARRAY 16,10 15,90 SQ 14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A A1 Corner 0,80 3 1 2 0,95 0,85 5 4 7 6 9 11 13 15 17 19 8 10 12 14 16 18 Bottom View 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,12 4204905/A 01/03 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar BGA configuration. This package is lead-free. MicroStar is a trademark of Texas Instruments.
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PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK 156 105 157 104 0,27 0,17 0,08 M 0,50 0,13 NOM 208 53 1 52 Gage Plane 25,50 TYP 28,05 SQ 27,95 0,25 0,05 MIN 0°–ā7° 30,20 SQ 29,80 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4087729/D 11/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.