Data Manual 1999 PCIBus Solutions
Printed in U.S.A.
PCI2250 PCI-to-PCI Bridge Data Manual Literature Number: SCPS051 December 1999 Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.
4 5 iv Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 7 5.11 Buffer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 5.12 Port Decode Map Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 5.13 Clock Run Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 5.14 Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 5.15 Diagnostic Status Register . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure 2–1 2–2 3–1 3–2 3–3 3–4 3–5 6–1 6–2 6–3 6–4 vi Title Page PCI2250 PGF LQFP Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 PCI2250 PCM PQFP Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 3–1 4–1 4–2 4–3 4–4 4–5 4–6 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 5–13 5–14 5–15 5–16 5–17 5–18 Title PGF LQFP Signal Names Sorted by Terminal Number . . . . . . . . . . . . . . . PCM LQFP Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphabetically to PGF Terminal Number . . . . . . . . Signal Names Sorted Alphabetically to PCM Terminal Number . . . . . . . .
5–19 5–20 5–21 5–22 viii Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Swap Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction 1.1 Description The Texas Instruments PCI2250 PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2250 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.
• Fully compliant with PCI-to-PCI Bridge Architecture Specification • Packaged in 160-pin QFP (PCM) and 176-pin thin QFP (PGF) 1.3 Related Documents • Advanced Configuration and Power Interface (ACPI) Revision 1.0 • PCI Local Bus Specification Revision 2.2 • PCI Mobile Design Guide, Revision 1.0 • PCI-to-PCI Bridge Architecture Specification Revision 1.1 • PCI Power Management Interface Specification Revision 1.1 • PICMG Compact-PCI Hot Swap Specification Revision 1.0 1.
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 V CC NC MS1/BPCC NC S_C/BE1 GND S_AD15 S_AD14 V CC S_AD13 S_AD12 GND S_AD11 S_AD10 S_AD9 V CC S_AD8 S_C/BE0 S_AD7 GND S_AD6 S_AD5 S_AD4 V CC S_AD3 S_AD2 S_AD1 GND S_AD0 P_AD0 P_AD1 V CC P_AD2 P_AD3 GND P_AD4 P_AD5 V CC P_AD6 P_AD7 NC P_C/BE0 NC GND 2 Terminal Descriptions 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118
P_C/BE0 GND P_AD2 P_AD3 GND P_AD4 P_AD5 V CC P_AD6 P_AD7 S_C/BE1 GND S_AD15 S_AD14 V CC S_AD13 S_AD12 GND S_AD11 S_AD10 S_AD9 V CC S_AD8 S_C/BE0 S_AD7 GND S_AD6 S_AD5 S_AD4 V CC S_AD3 S_AD2 S_AD1 GND S_AD0 P_AD0 P_AD1 V CC V CC MS1/BPCC 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND S_AD25 S_AD26 V CC S_AD27 S_AD28 S_AD29 90 89 88 87 86 85 84 83 82 81 40 GND S_REQ3 S_GNT0 S_GNT1 S_GNT2
Table 2–1. PGF LQFP Signal Names Sorted by Terminal Number TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO.
Table 2–2. PCM LQFP Signals Sorted by Terminal Number TERM. NO. 2–4 SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO.
Table 2–3. Signal Names Sorted Alphabetically to PGF Terminal Number SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO.
Table 2–4. Signal Names Sorted Alphabetically to PCM Terminal Number SIGNAL NAME TERM. NO. SIGNAL NAME GND 1 P_AD13 GND 12 GND 19 GND TERM. NO. SIGNAL NAME TERM. NO. SIGNAL NAME TERM. NO.
Table 2–5. Primary PCI System TERMINAL NAME PCM NUMBER PGF NUMBER I/O DESCRIPTION P_CLK 66 72 I Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals are sampled at rising edge of P_CLK. I PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers in a high-impedance state and reset all internal registers. When asserted, the device is completely nonfunctional.
Table 2–7. Primary PCI Interface Control TERMINAL NAME PCM NUMBER PGF NUMBER I/O DESCRIPTION P_DEVSEL 100 110 I/O Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target responds before a time-out occurs, then the bridge terminates the cycle with a master abort. P_FRAME 96 106 I/O Primary cycle frame.
Table 2–8. Secondary PCI System TERMINAL I/O DESCRIPTION 67 65 63 61 59 O Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each secondary bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input. 57 I Secondary PCI bus clock input. This input syncronizes the PCI2250 to the secondary bus clocks.
Table 2–9.
Table 2–10. Secondary PCI Interface Control TERMINAL NAME PCM NUMBER PGF NUMBER I/O DESCRIPTION S_DEVSEL 7 9 I/O Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target responds before a timeout occurs, then the bridge terminates the cycle with a master abort. S_FRAME 11 13 I/O Secondary cycle frame.
Table 2–11. Miscellaneous Terminals TERMINAL NAME PCM NUMBER PGF NUMBER I/O DESCRIPTION GOZ 63 69 I NO/HSLED 62 68 I/O NAND tree enable pin. MS0 120 132 I Mode select 0 MS1/BPCC 159 174 I Mode select 1 when mode select 0 is low, bus power clock control when mode select 0 is high. P_MFUNC 102 112 I/O Primary multifunction terminal. This terminal can be configured as P_CLKRUN, P_LOCK, or HS_ENUM depending on the values of MS0 and MS1.
3 Feature/Protocol Descriptions The following sections give an overview of the PCI2250 PCI-to-PCI bridge features and functionality. Figure 3–1 shows a simplified block diagram of a typical system implementation using the PCI2250. Host Bus CPU Memory Host Bridge PCI Device PCI Device PCI Bus 0 PCI Option Card PCI2250 PCI Option Card PCI Bus 2 PCI Bus 1 PCI2250 PCI Device PCI Device (Option) PCI Option Slot Figure 3–1. System Block Diagram 3.
3.2 PCI Commands The bridge responds to PCI bus cycles as a PCI target device based on the decoding of each address phase and internal register settings. Table 3–1 lists the valid PCI bus cycles and their encoding on the command/byte enables (C/BE) bus during the address phase of a bus cycle. Table 3–1.
The bridge claims only type 0 configuration cycles when its P_IDSEL terminal is asserted during the address phase of the cycle and the PCI function number encoded in the cycle is 0. If the function number is 1 or greater, the bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL and the configuration transaction results in a master abort.
PCI Bus 0 PCI2250 Primary Bus Secondary Bus Subordinate Bus PCI2250 00h 01h 02h Primary Bus Secondary Bus Subordinate Bus PCI Bus 1 00h 03h 03h PCI Bus 3 PCI2250 Primary Bus Secondary Bus Subordinate Bus 01h 02h 02h PCI Bus 2 Figure 3–4. Bus Hierarchy and Numbering 3.4 Special Cycle Generation The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion.
PCI2250 S_CLK S_CLKOUT4 S_CLKOUT3 PCI Device S_CLKOUT2 PCI Device S_CLKOUT1 PCI Device S_CLKOUT0 PCI Device Figure 3–5. Secondary Clock Block Diagram 3.6 Bus Arbitration The PCI2250 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary bus arbitration. Four secondary bus requests and four secondary bus grants are provided on the secondary of the PCI2250. Five potential initiators, including the bridge, can be located on the secondary bus.
bus grant terminals. Including the bridge, there are a total of five potential secondary bus masters. These request and grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ3–S_REQ0 and S_GNT3–S_GNT0 are placed in a high impedance mode. 3.6.3 External Secondary Bus Arbitration An external secondary bus arbiter can be used instead of the PCI2250 internal arbiter.
P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled in the P_SERR event disable register. When the bridge signals SERR, bit 14 of the secondary status register (offset 1Eh, see Section 4.19) is set. 3.9.1 Posted Write Parity Error If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.18) is 0, then parity errors on the target bus during a posted write are passed to the initiating bus as an SERR.
3.10.2 Data Parity Error If the parity error response bit (bit 6) in the command register (offset 04h, see Section 4.3) is set, then the PCI2250 signals PERR when it receives bad data. When the bridge detects bad parity, bit 15 (detected parity error) in the status register (offset 06h, see Section 4.4) is set.
destination bus. If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries the initial request. During the third phase, the initiator rearbitrates for the bus. When the bridge sees the initiator retry the transaction, it compares the second request to the first request.
3.14.2 PCI Clock Run Feature The PCI2250 supports the PCI clock run protocol when in clock run mode, as defined in the PCI Mobile Design Guide. When the system’s central resource signals to the system that it wants to stop the PCI clock (P_CLK) by driving the primary clock run (P_CLKRUN) signal high, the bridge either signals that it is OK to stop the PCI clock by leaving P_CLKRUN deasserted (high) or signals to the system to keep the clock running by driving P_CLKRUN low.
4 Bridge Configuration Header The PCI2250 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Architecture Specification. Table 4–1 shows the PCI configuration header, which includes the predefined portion of the bridge’s configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading. Table 4–1.
A bit description table is typically included that indicates bit field names, a detailed field description, and field access tags. Table 4–2 describes the field access tags. Table 4–2. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field may be read by software. W Write Field may be written by software to any value. S Set C Clear U Update MEANING Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of one. Writes of 0 have no effect.
4.3 Command Register The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4–3 describes the bit functions in the command register.
4.4 Status Register The status register provides device information to the host system. This register is read-only. Bits in this register are cleared by writing a 1 to the respective bit; writing a 0 to a bit location has no effect. Table 4–4 describes the status register.
4.5 Revision ID Register The revision ID register indicates the silicon revision of the PCI2250. Bit 7 6 5 4 Name 3 2 1 0 Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Revision ID Read-only 08h 01h (reflects the current revision of the silicon) 4.6 Class Code Register This register categorizes the PCI2250 as a PCI-to-PCI bridge device (0604h) with a 01h or 00h programming interface.
4.8 Primary Latency Timer Register The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is deasserted.
4.11 Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read.
4.14 Secondary Bus Number Register The secondary bus number register indicates the secondary bus number to which the bridge is connected. The PCI2250 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the secondary bus are converted to type 0 configuration cycles.
4.17 I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15–AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of the defined I/O address range is aligned on a 4K-byte boundary.
4.19 Secondary Status Register The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective bit.
4.20 Memory Base Register The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 0s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
4.23 Prefetchable Memory Limit Register The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
4.26 I/O Base Upper 16 Bits Register The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
4.29 Expansion ROM Base Address Register The PCI2250 does not implement the expansion ROM remapping feature. The expansion ROM base address register returns all 0s when read.
4.32 Bridge Control Register The bridge control register provides many of the same controls for the secondary interface that are provided by the command register (offset 04h, see Section 4.3) for the primary interface. Some bits affect the operation of both interfaces.
Table 4–6. Bridge Control Register (Continued0) BIT TYPE FUNCTION R/W ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary, addressing the last 768 bytes in each 1K-byte block. This applies only to the addresses (defined by the I/O window registers) that are located in the first 64K bytes of PCI I/O address space.
5 Extension Registers The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h–FFh in PCI configuration space in the PCI2250). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge. The TI extension registers are not reset on the transition from D3 to D0. 5.
5.2 Extended Diagnostic Register The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset both the PCI2250 and the secondary bus. Bit 7 6 5 Name 4 3 2 1 0 Extended diagnostic Type R R R R R R R W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Extended diagnostic Read-only, Write-only 41h 00h Table 5–2. Extended Diagnostic Register 5–2 BIT TYPE FUNCTION 7–1 R Reserved. Bits 7–1 return 0s when read.
5.3 Arbiter Control Register The arbiter control register is used for the bridge’s internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The PCI2250 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier.
5.4 Extension Window Base 0, 1 Registers The bridge supports two extension windows that define an address range decoded as described in the window enable register and window map register. The extension window base registers define the 32-bit base address of the window.
5.6 Extension Window Enable Register The decode of the extension windows is enabled through bits 0 and 1 of this register. See Table 5–4 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 Extension window enable Type R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Extension window enable Read-only, Read/Write 54h 00h Table 5–4.
5.8 Secondary Decode Control Register The secondary decode control register is used to enable/disable the secondary-bus negative decoding. Only through this register can an extension window be defined for positive decoding or excluded from negative decoding from the secondary bus to the primary bus. The window interface bits in the window control registers must be set for the extension window definitions in this register to have meaning.
5.9 Primary Decode Control Register This register is used to enable and disable the primary bus subtractive decoding and to select the primary bus subtractive decode speed. The bridge defaults to primary bus subtractive decoding enabled (bit 0 is set to 1b). Bit 0 of this register is aliased to bit 0 of the class code register (offset 09h, see Section 4.6) so that the class code register reflects whether or not subtractive decoding is enabled on the primary interface.
5.10 Port Decode Enable Register The port decode enable register is used to select which serial and parallel port addresses are positively decoded from the bridge primary bus to the secondary bus. See Table 5–8 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 Port decode enable Type R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Port decode enable Read-only, Read/Write 58h 00h Table 5–8.
5.11 Buffer Control Register The buffer control register allows software to enable/disable write posting and control memory read burst prefetching. The buffer control register also enables/disables the posted memory write reconnect feature. See Table 5–9 for a complete description of the register contents.
5.12 Port Decode Map Register The port decode map register is used to select whether the serial- and parallel-port address ranges positively decoded from the primary bridge interface to the secondary interface are included or excluded from the primary interface. For example, if bit 0 is set, then addresses in the range of 3F8h–3FFh are positively decoded on the primary bus.
5.13 Clock Run Control Register The clock run control register controls the PCI clock-run mode enable/disable. It is also used to enable the keep-clock-running feature. Bit 0 reflects the status of the secondary clock. There are two clock run modes supported on the secondary bus.
Table 5–12. Diagnostic Control Register BIT TYPE FUNCTION 15 R/W Arbiter performance enhancement feature. When enabled, this feature provides automatic tier operation for bus masters that have been retried or that have pending delayed transactions. In this case, the bus master gets promoted to the highest priority tier. 0 = Disabled (default) 1 = Enabled 14 R/W Parity mode.
5.15 Diagnostic Status Register The diagnostic status register is used to reflect the bridge diagnostic status. See Table 5–13 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Diagnostic status Type R R R R R/C/ U R/C/ U R R R/C/ U R R R R R R R/C/ U Default 0 0 0 0 X X 0 0 0 0 0 0 0 X X X Register: Type: Offset: Default: Diagnostic status Read-only, Read/Write 5Eh 0X0Xh Table 5–13.
5.16 Arbiter Request Mask Register The arbiter request mask register contains the SERR enable on arbiter timeouts and the request mask controls. See Table 5–14 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 Arbiter request mask Type R R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Arbiter request mask Read-only, Read/Write 62h 00h Table 5–14.
5.17 Arbiter Timeout Status Register The arbiter timeout status register contains the status of each request (request 5–0) timeout. The timeout status bit for the respective request is set if the device did not assert FRAME after 16 clocks. See Table 5–15 for a complete description of the register contents.
5.18 P_SERR Event Disable Register The P_SERR event disable register is used to enable/disable SERR event on the primary interface. All events are enabled by default. See Table 5–16 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 P_SERR event disable Type R R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: P_SERR event disable Read-only, Read/Write 64h 00h Table 5–16.
5.19 Secondary Clock Control Register The secondary clock control register is used to control the secondary clock outputs. See Table 5–17 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Secondary clock control Type R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Secondary clock control Read-only, Read/Write 68h 0000h Table 5–17.
5.20 P_SERR Status Register The P_SERR status register indicates what caused a SERR event on the primary interface. See Table 5–18 for a complete description of the register contents. Bit 7 6 5 4 Name 3 2 1 0 P_SERR status Type R R/C/U R/C/U R/C/U R/C/U R/C/U R/C/U R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: P_SERR status Read-only, Read/Clear/Update 6Ah 00h Table 5–18. P_SERR Status Register BIT TYPE FUNCTION 7 R 6 R/C/U Master delayed read time-out.
5.22 PM Next Item Pointer Register The next item pointer register is used to indicate the next item in the linked list of PCI power management capabilities. The next item pointer returns E4h in compact PCI mode, indicating that the PCI2250 supports more than one extended capability, but in all other modes returns 00h, indicating that only one extended capability is supported.
5.24 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI2250. The contents of this register are not affected by the internally generated reset caused by the transition from D3hot to D0 state. See Table 5–20 for a complete description of the register contents.
5.25 PMCSR Bridge Support Register The PMCSR bridge support register is required for all PCI bridges and supports PCI bridge specific functionality. See Table 5–21 for a complete description of the register contents. Bit 7 6 5 4 Type R R R R Default X X 0 0 Name 3 2 1 0 R R R R 0 0 0 0 PMCSR bridge support Register: Type: Offset: Default: PMCSR bridge support Read-only E2h X0h Table 5–21. PMCSR Bridge Support Register BIT TYPE 7 R 6 FUNCTION Bus power control enable.
5.27 HS Capability ID Register The HS capability ID register identifies the linked list item as the register for CPCI hot swap capabilities. The register returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and the value. Bit 7 6 5 Name 4 3 2 1 0 HS capability ID Type R R R R R R R R Default 0 0 0 0 0 1 1 0 Register: Type: Offset: Default: HS capability ID Read-only E4h 06h 5.
5.29 Hot Swap Control Status Register The hot swap control status register contains control and status information for CPCI hot swap resources. See Table 5–22 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 Hot swap control status Type Default Register: Type: Offset: Default: R/C/U R/C/U R R R/W R R/W R 0 0 0 0 0 0 0 0 Hot swap control status Read-only, Read/Write E6h 00h Table 5–22.
5–24
6 Electrical Characteristics 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges † Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.6 V : SVCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V : PVCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.
6.2 Recommended Operating Conditions (see Note 3) OPERATION VCC Supply voltage (core) Commercial PVCCP PCI primary bus I/O clamping rail voltage Commercial SVCCP PCI secondary bus I/O clamping rail voltage Commercial 3.3 V 3.3 V 5V 3.3 V 5V 3.3 V VIH† High-level High level in input ut voltage VO§ Output voltage tt Input transition time (tr and tf) TA TJ¶ Operating ambient temperature range 3.6 3 3.3 3.6 4.75 5 5.25 3 3.3 3.6 4.75 5 5.25 V V V 2.25 VCC 3.3 V 0 0.
6.4 Electrical Characteristics Over Recommended Operating Conditions PARAMETER TERMINALS 3.3 V VOH† High-level High le el output o tp t voltage oltage VOL IIH‡ OPERATION Low level output voltage Low-level 5V IOH = –2 mA 3.3 V IOL = 1.5 mA 5V Input terminals High-level High level in input ut current TEST CONDITIONS IOH = –0.5 mA MIN Low-level input Low level in ut current Input terminals 0.1 VCC 0.55 TTL§ PCI VI = VCCP 10 VI = VCCP 10 TTL§ PCI UNIT V 2.
6.
6.
6.7 Parameter Measurement Information LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL From Output Under Test Test Point VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.
6.8 PCI Bus Parameter Measurement Information twH twL 2V 2 V min Peak to Peak 0.8 V tf tr tc Figure 6–2. PCLK Timing Waveform PCLK tw RSTIN tsu Figure 6–3. RSTIN Timing Waveforms PCLK 1.5 V tpd PCI Output tpd 1.5 V Valid toff ton PCI Input Valid tsu th Figure 6–4.
6–8
7 Mechanical Data PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 132 89 88 133 0,27 0,17 0,08 M 0,50 0,13 NOM 176 45 1 44 Gage Plane 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 0,25 0,05 MIN 0°–ā7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040134 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PCM (S-PQFP-G***) PLASTIC QUAD FLATPACK 144 PINS SHOWN 108 73 109 NO. OF PINS*** A 144 22,75 TYP 160 25,35 TYP 72 0,38 0,22 0,13 M 0,65 144 37 0,16 NOM 1 36 A 28,20 SQ 27,80 31,45 SQ 30,95 3,60 3,20 Gage Plane 0,25 0,25 MIN 1,03 0,73 Seating Plane 4,10 MAX 0,10 4040024 / B 10/94 NOTES: A. B. C. D. 7–2 All linear dimensions are in millimeters. This drawing is subject to change without notice.
