Computer Hardware User Manual

System Features Selection

1-6

1.1.12.3 Asynchronous CSC Interrupt Generation

The ASYNC_CSC bit (diagnostic register, PCI offset 93h, bit 0) controls the

CSC interrupt signaling method. If this bit is set to 0, then CSC is generated

synchronously to PCLK (recommended). By default this bit is set to 1, which

is the asynchronous mode.

1.1.12.4 CardBus Reserved Terminal Signaling

The CardBus interface has reserved terminals. Usually the CardBus controller

drives these terminals low. If the CBRSVD bit (system control register, PCI

offset 80h, bit 22) is set to 0, then the CardBus reserved terminal signals are

in a high-impedance state when a CardBus card is inserted in the socket.

1.1.12.5 Memory Burst R/W Operation Control

Memory read bursting is controlled via the MRBURSTDN bit (system control

Card) and the MRBURSTUP bit (system control register, PCI offset 80h,

bit 14) for upstream burst transactions (PC Card-to-PCI). Memory write

bursting is controlled via the POSTEN bit (bridge control register, PCI offset

3Eh, bit 10). This bit enables write posting if disabled. No write data can be

accepted (including burst writes) until any previous write data has been

forwarded to its destination. By default, write posting and upstream read bursts

are disabled.

1.1.12.6 Power Savings Mode

The PCI445X device has a proprietary power-saving mode. It can be disabled

by changing the PWRSAVINGS bit (system control register, PCI offset 80h,

bit 6) to 0. When this bit is enabled (default), PCI CLOCK is internally gated

for a nonfunctioning circuit. For example, the CardBus interface does not

function when a 16-bit card is inserted. This power-saving mode will not

degrade performance; therefore, the default setting is recommended.

1.1.12.7 PME/RI_OUT Terminal Control Clarification

PME/RI_OUT terminal can be set up to signal a combination of these events.

The terminal is set up using the PME/RI_OUT bit (system control register, PCI

offset 80h, bit 0), the RIENB bit (card control register, PCI offset 91h, bit 7), and

PME enable bit (power management control/status, PCI offset A4h, bit 8). If

the terminal is set up as RI_OUT

and RIENB has ring indicate enabled, then

this signal follows the RI_OUT signal for 16-bit I/O cards. If RIENB has ring

indicate disabled but PME has PME enabled, then this line reflects the state

of the PMESTAT bit (power management control/status, PCI offset A4h,

bit 15). If both PME

and ring indicate are disabled, then the line remains high.

If the line is configured as PME and PME is enabled, then this line follows the

state of the PMESTAT bit; otherwise, the line remains high.

1.1.12.8 CLKRUN Control

PCLK can be kept running using CLKRUN protocol by setting the KEEPCLK

bit (system control register, PCI offset 80h, bit 1) to 1.