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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002

     

  

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FEATURES

24-Bit Resolution

D Analog Performance:

− Dynamic Range: 103 dB, Typical

− SNR: 103 dB, Typical

− THD+N: 0.004%, Typical

− Full-Scale Output: 3.1 Vp-p, Typical

D 8× Oversampling Interpolation Filter:

− Stopband Attenuation: –55 dB

− Passband Ripple: ±0.03 dB

D Sampling Frequency:

− 5 kHz to 200 kHz (Channels 1 and 2)

− 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)

D Accepts 16- and 24-Bit Audio Data

D Data Formats: Standard, I

S, and

Left-Justified, TDM

D System Clock: 128 f

, 192 f

, 256 f

, 384 f

512 f

, or 768 f

D Digital De-Emphasis for 32 kHz, 44.1 kHz,

48 kHz

D Power Supply: 5-V Single Supply

D 20-Lead SSOP Package

APPLICATIONS

Integrated A/V Receivers

D DVD Movie and Audio Players

D HDTV Receivers

D Car Audio Systems

D DVD Add-On Cards for High-End PCs

D Digital Audio Workstations

D Other Multichannel Audio Systems

DESCRIPTION

The PCM1606 is a CMOS monolithic integrated circuit

that features six 24-bit audio digital-to-analog

converters and support circuitry in a small 20-lead

SSOP package. The digital-to-analog converters utilize

Texas Instruments’ enhanced multilevel, delta-sigma

architecture, which employs 2

-order noise shaping

and 8-level amplitude quantization to achieve excellent

signal-to-noise performance and a high tolerance to

clock jitter.

The PCM1606 accepts industry-standard audio data

formats with 16- to 24-bit audio data. Sampling rates up

to 200 kHz are supported.

DATA1

DATA2

DATA3

FMT1

FMT0

ZEROA

AGND

OUT

SCKI

BCK

LRCK

DEMP1

DEMP0

COM

OUT

PCM1606

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (28 pages)

PAGE 1
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 FEATURES D 24-Bit Resolution D Analog Performance: D D D D D D D D DESCRIPTION − Dynamic Range: 103 dB, Typical − SNR: 103 dB, Typical − THD+N: 0.004%, Typical − Full-Scale Output: 3.1 Vp-p, Typical 8× Oversampling Interpolation Filter: − Stopband Attenuation: –55 dB − Passband Ripple: ±0.
PAGE 2
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1606E 20-Lead SSOP ZZ334-1 –25°C to 85°C PCM1606E ORDERING NUMBER† TRANSPORT MEDIA PCM1606E TUBE PCM1606E/2K Tape and Reel † Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel).
PAGE 3
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 Terminal Functions TERMINAL NAME PIN I/O DESCRIPTIONS AGND 7 — Analog and digital ground BCK 19 I Shift clock input for serial audio data (see Note 2) DATA1 1 I Serial audio data input for VOUT1 and VOUT2 (see Note 2) DATA2 2 I Serial audio data input for VOUT3 and VOUT4 (see Note 2) DATA3 3 I Serial audio data input for VOUT5 and VOUT6 (see Note 2) DEMP0 16 I De-emphasis control (see Note 1) DEMP1 17 I De-emphasis control
PAGE 4
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, fS = 44.
PAGE 5
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data (unless otherwise noted) (continued) PCM1606E PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS Passband ±0.03 dB 0.454 fS −3 dB 0.487 fS Stopband 0.546 fS ±0.03 Passband ripple Stopband attenuation Stopband = 0.546 fS −50 Stopband = 0.
PAGE 6
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) power-on reset functions The PCM1606 includes a power-on reset function. Figure 2 shows the operation of this function. With the system clock active and VCC > 3 V typical (2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VCC > 3 V. After the initialization period, the PCM1606 is set to its reset default state. Table 1.
PAGE 7
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) audio serial interface The audio serial interface for the PCM1606 comprises a 5-wire synchronous serial port. It includes LRCK (pin 18), BCK (pin 19), DATA1 (pin 1), DATA2 (pin 2) and DATA3 (pin 3). BCK is the serial audio bit clock and is used to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift registers. Serial data is clocked into the PCM1606 on the rising edge of BCK.
PAGE 8
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) 1.4 V LRCK t(BCH) t(BCL) t(LB) 1.4 V BCK t(BCY) t(BL) 1.
PAGE 9
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) t(BCKH) 2.0 V BCK 0.8 V t(BCKL) Bit Clock Pulse Cycle Time† PARAMETERS MIN t(BCKH) Bit clock pulse duration HIGH t(BCKL) Bit clock pulse duration LOW † 1/128 fS, 1/256 fS, and 1/512 fS. MAX UNIT 10 ns 10 ns Figure 4. Bit Clock Timing for TDM Format 1.4 V LRCK t(BCH) t(BCL) t(LB) 1.4 V BCK t(BCY) t(BL) 1.
PAGE 10
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK R−Channel L−Channel BCK (= 32 fS, 48 fS or 64 fS) 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 MSB 2 1 14 15 16 MSB 3 14 15 16 MSB LSB 3 2 1 LSB 2 LSB 3 14 15 16 MSB LSB (2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK
PAGE 11
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 timing requirements (continued) (4) TDM Data Format BCK = 256 fS Channel 1 1/fS Channel 3 Channel 2 Channel 6 LRCK 32 BCK 32 BCK BCK 1 2 3 22 23 24 LOW Fix 1 24 LOW Fix LOW Fix 64 Bit 1 2 LSB MSB BCK = 128 fS Channel 1 Channel 2 32 BCK 32 BCK 1/fS LRCK BCK 1 2 3 22 23 24 MSB LOW Fix LSB 24 LOW Fix 1 MSB LOW Fix 64 Bit 1 2 LSB BCK = 512 fS 1/fS Channel 1 Channel 2 64 BCK 64 BCK Channel 3 Channel 6 LRCK BCK
PAGE 12
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 functional description (continued) de-emphasis control The de-emphasis control can be selected by DEMP1 (pin 17) and DEMP0 (pin 16). See Table 5. Table 5. De-Emphasis Control DEMT1 (pin 17) DEMT0 (pin 16) AUDIO INTERFACE LOW LOW OFF LOW HIGH 48 kHz HIGH LOW 44.1 kHz HIGH HIGH 32 kHz analog outputs The PCM1606 includes six independent output channels, VOUT1 through VOUT6. These are unbalanced outputs, each capable of driving 3.
PAGE 13
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 functional description (continued) VCOM output One unbuffered common-mode voltage output pin, VCOM (pin 14) is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to VCC/2. If this pin is to be used to bias external circuitry, a voltage follower is required for buffering purposes. Figure 8 shows an example of using the VCOM pin for external biasing applications.
PAGE 14
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—DIGITAL FILTER AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 VCC = 5 V fS = 44.1 kHz TA = 25°C De-emphasis Off −20 0.03 −40 0.02 Amplitude − dB Amplitude − dB VCC = 5 V fS = 44.1 kHz TA = 25°C De-emphasis Off 0.04 −60 −80 0.01 0.00 −0.01 −0.02 −100 −0.03 −120 −0.04 −140 0 1 2 3 −0.05 0.0 4 0.1 0.2 f − Frequency [ fS] Figure 9 0.5 DE-EMPHASIS ERROR vs FREQUENCY 0.
PAGE 15
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—DIGITAL FILTER DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 VCC = 5 V fS = 44.1 kHz TA = 25°C −1 De-emphasis Level − dB −2 VCC = 5 V fS = 44.1 kHz TA = 25°C 0.4 0.3 De-emphasis Error − dB −3 −4 −5 −6 −7 0.2 0.1 −0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 0 2 4 6 8 10 12 14 16 18 −0.
PAGE 16
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE DYNAMIC RANGE vs SUPPLY VOLTAGE 106 100.00 10 VCC = 5 V fS = 44.1 kHz TA = 25°C 192 kHz 128 fS 96 kHz 256 fS 10.00 1 44.1 kHz 384 fS −60 dB 1.00 0.1 0.10 0.01 96 kHz 256 fS 192 kHz 128 fS 44.1 kHz 384 fS 4.5 192 kHz 128 fS 96 kHz 256 fS 100 98 5.0 5.5 96 4.0 6.0 Figure 17 5.0 5.5 6.
PAGE 17
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 106 100.00 10 VCC = 5 V fS = 44.1 kHz VCC = 5 V fS = 44.1 kHz 192 kHz 128 fS 96 kHz 256 fS 104 44.1 kHz 384 fS −60 dB 1.00 0.1 192 kHz 128 fS 0.10 0.01 44.1 kHz 384 fS 96 kHz 256 fS −25 0 102 192 kHz 128 fS 100 96 kHz 256 fS 98 0 dB 0.01 0.
PAGE 18
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE −90-dB OUTPUT SPECTRUM −90-dB OUTPUT SPECTRUM 0 0 VCC = 5 V fS = 44.1 kHz TA = 25°C −40 −40 −60 −60 −80 −100 −120 −80 −100 −120 −140 −140 −160 −160 −180 0.0 0.5 VCC = 5 V fS = 44.1 kHz TA = 25°C −20 Amplitude − dB Amplitude − dB −20 1.0 1.5 −180 0.0 2.0 0.1 0.2 f − Frequency − MHz f − Frequency − MHz Figure 26 Figure 25 DYNAMIC RANGE vs JITTER 106 VCC = 5 V fS = 44.
PAGE 19
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION connection diagrams A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling components. Texas Instruments recommends using the component values shown in Figure 28 for all designs. A typical application diagram is shown in Figure 29. Texas Instruments’ PLL1700 is used to generate the system clock input at SCKI, as well as generating the clock for the audio signal processor.
PAGE 20
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION DIGITAL SECTION ANALOG SECTION µC/µP{ RSw 1 DATA1 SCKI 20 2 DATA2 BCK 19 3 DATA3 LRCK 18 4 FMT1 DEMP1 17 5 FMT0 DEMP0 16 6 ZEROA VCC 15 7 AGND VCOM 14 RS Audio DSP or Decoder RS RS RS RS Buffer 8 PCM1606 VOUT5 VOUT4 13 PLL1700 9 VOUT6 VOUT3 12 SCKO3} 10 VOUT1 VOUT2 11 XT1 27-MHz Master Clock + 10 µF + 10 µF + 10 µF + 10 µF + 10 µF + 10 µF LS + 10 µF RS Down Mix L R
PAGE 21
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION D/A output filter circuits Delta-sigma D/A converters utilize noise shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering.
PAGE 22
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION PCB layout guidelines A typical PCB layout for the PCM1606 is shown in Figure 32. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board.
PAGE 23
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION PCB layout guidelines (continued) Power Supplies RF Choke or Ferrite Bead +5V AGND +VS −VS VCC VDD PCM1606 Output Circuits AGND Digital Section Analog Section Common Ground Figure 33. Single-Supply PCB Layout key performance parameters measurement This section provides information on how to measure key dynamic performance parameters for the PCM1606.
PAGE 24
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION total harmonic distortion + noise (continued) Evaluation Board DEM-DAI1606 S/PDIF Receiver PCM1606 2nd-Order Low-Pass Filter f−3 dB = 54 kHz S/PDIF Output Digital Generator 100% Full-Scale, 24-Bit, 1-kHz Sine Wave Analyzer and Display RMS Mode Band Limit Notch Filter HPF = 22 Hz† fc = 1 kHz LPF = 22 kHz† Option = 20-kHz Apogee Filter‡ † There is little difference in measured THD+N when using the various settings for thes
PAGE 25
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 APPLICATION INFORMATION idle channel signal-to-noise ratio (continued) Evaluation Board DEM-DAI1606 S/PDIF Receiver 2nd-Order Low-Pass Filter PCM1606 f−3 dB = 54 kHz S/PDIF Output Digital Generator 0% Full-Scale, Dither Off (SNR) −60 dB FS, 1 kHz Sine Wave (Dynamic Range) Analyzer and Display A-Weight Filter† Band Limit RMS Mode Notch Filter HPF = 22 Hz fc = 1 kHz LPF = 22 kHz Option = A-Weighting† † Results without A-Weighting will be approx
PAGE 26
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°−ā 8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /D 09/00 NOTES: A. B. C. D. 26 All linear dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.