Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 14

PCM1725

Stereo Audio

DIGITAL-TO-ANALOG CONVERTER

16 Bits, 96kHz Sampling

PCM1725

DESCRIPTION

The PCM1725 is a complete low cost stereo audio

digital-to-analog converter (DAC), operating off of a

256f

or 384f

system clock. The DAC contains a 3rd-

order ∆Σ modulator, a digital interpolation filter, and

an analog output amplifier. The PCM1725 accepts

16-bit input data in either normal or I

S formats.

The digital filter performs an 8X interpolation function

and includes de-emphasis at 44.1kHz. The PCM1725

can accept digital audio sampling frequencies from

16kHz to 96kHz, always at 8X oversampling.

The PCM1725 is ideal for low-cost, CD-quality con-

sumer audio applications.

FEATURES

● COMPLETE STEREO DAC: Includes Digital

Filter and Output Amp

● DYNAMIC RANGE: 95dB

● MULTIPLE SAMPLING FREQUENCIES:

16kHz to 96kHz

● 8X OVERSAMPLING DIGITAL FILTER

● SYSTEM CLOCK: 256f

/384f

● NORMAL OR I

S DATA INPUT FORMATS

● SMALL 14-PIN SOIC PACKAGE

PCM1725

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

Serial

Input

I/F

Mode

Control

I/F

8X Oversampling

Digital Filter

SCKI

256f

/384f

GND

Multi-level

Delta-Sigma

Modulator

OUT

CAP

DAC

Multi-level

Delta-Sigma

Modulator

Low-pass

Filter

Low-pass

Filter

OUT

DAC

FORMAT

LRCIN

DIN

BCKIN

Power Supply

SBAS067

Not Recommended For New Designs

Summary of content (14 pages)

PAGE 1
Not Recommended For New Designs ® PCM1725 PCM 172 5 Stereo Audio DIGITAL-TO-ANALOG CONVERTER 16 Bits, 96kHz Sampling TM FEATURES DESCRIPTION ● COMPLETE STEREO DAC: Includes Digital Filter and Output Amp The PCM1725 is a complete low cost stereo audio digital-to-analog converter (DAC), operating off of a 256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and an analog output amplifier.
PAGE 2
Not Recommended For New Designs SPECIFICATIONS All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PAGE 3
Not Recommended For New Designs PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SOIC PIN NAME I/O FUNCTION 1(1) LRCIN IN Sample Rate Clock Input 2(1) DIN IN Audio Data Input 3(1) BCKIN IN Bit Clock Input for Audio Data.
PAGE 4
Not Recommended For New Designs TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted. DYNAMIC PERFORMANCE SNR, DYNAMIC RANGE vs TEMPERATURE 3.1 3.0 2.9 0.006 2.8 0.005 2.7 –60dB 0.003 2.6 0.002 2.5 0.001 2.4 0 25 50 75 85 97 97 96 96 95 95 94 93 –25 2.3 0 –25 100 93 0 25 75 85 100 SNR, DYNAMIC RANGE vs POWER SUPPLY 0.009 3.2 0.008 3.1 99 99 0.006 2.9 0.005 2.8 0.004 2.7 0.003 2.6 0.002 2.
PAGE 5
Not Recommended For New Designs TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 –1 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS 0 0.1134fS DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0.3402fS 0.4535fS DE-EMPHASIS FREQUENCY ERROR (44.1kHz) 0 0.6 –2 0.4 –4 0.
PAGE 6
Not Recommended For New Designs 1/fs L_ch R_ch LRCIN (pin 1) BCKIN (pin 3) AUDIO DATA WORD = 16-BIT DIN (pin 2) 14 15 16 1 2 14 3 MSB 15 16 1 2 LSB 3 MSB 14 15 16 LSB FIGURE 1. “Normal” Data Input Timing. 1/fs L_ch LRCIN (pin 1) R_ch BCKIN (pin 3) AUDIO DATA WORD = 16-BIT DIN (pin 2) 1 2 14 3 MSB 15 16 1 LSB 2 3 MSB 14 1 15 16 2 LSB FIGURE 2. “I2S” Data Input Timing. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.
PAGE 7
Not Recommended For New Designs PCM1725 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The system clock should be synchronized with LRCIN (pin 1), but PCM1725 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization function.
PAGE 8
Not Recommended For New Designs APPLICATION CONSIDERATIONS INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) DELAY TIME 1.0 There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1725: dB 0.5 0 TD = 11.125 x 1/fS –0.5 For fS = 44.
PAGE 9
Not Recommended For New Designs + In + 8fS 18-Bit + Z–1 + + – + Z–1 Z–1 – + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 10. 5-Level ∆Σ Modulator Block Diagram. THEORY OF OPERATION 5-LEVEL ∆Σ MODULATOR The delta-sigma section of PCM1725 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 10.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1725DR SOIC D 14 2000 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PCM1725U/2K SOIC D 14 2000 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1725DR SOIC D 14 2000 367.0 367.0 38.0 PCM1725U/2K SOIC D 14 2000 367.0 367.0 38.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.