Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 16

+3.3V Single-Supply, 24-Bit, 96kHz Sampling

Enhanced Multilevel, Delta-Sigma, Audio

DIGITAL-TO-ANALOG CONVERTER

PCM1741

DESCRIPTION

The PCM1741 is a CMOS, monolithic, integrated circuit

which includes stereo Digital-to-Analog Converters

(DACs) and support circuitry in a small SSOP-16 package.

The data converters utilize Texas Instrument’s enhanced

multilevel delta-sigma architecture that employs fourth-

order noise shaping and 8-level amplitude quantization to

achieve excellent dynamic performance and improved toler-

ance to clock jitter. The PCM1741 accepts industry standard

audio data formats with 16- to 24-bit data, providing easy

interfacing to audio DSP and decoder chips. Sampling rates

up to 100kHz are supported. A full set of user-program-

mable functions are accessible through a 3-wire serial

control port that supports register write functions.

FEATURES

●

24-BIT RESOLUTION

●

ANALOG PERFORMANCE (V

= +3.3V):

Dynamic Range: 98dB typ

SNR: 98dB typ

THD+N: 0.005% typ

Full-Scale Output: 2.05Vp-p typ

●

8x OVERSAMPLING DIGITAL FILTER:

Stopband Attenuation: –55dB

Passband Ripple: ±0.03dB

●

SAMPLING FREQUENCY: 5kHz to 100kHz

●

SYSTEM CLOCK: 256, 384, 512, 768f

with

Auto Detect

●

ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO

DATA

●

DATA FORMATS: Standard, I

S, and Left-

Justified

● USER-PROGRAMMABLE MODE CONTROLS:

Digital Attenuation: 0dB to –63dB, 0.5dB/Step

Digital De-Emphasis

Digital Filter Roll-Off: Sharp or Slow

Soft Mute

Zero Flags for Each Output

●

3.3V SINGLE POWER SUPPLY

●

5V TOLERANT DIGITAL INPUTS

●

SMALL SSOP-16 PACKAGE

www.ti.com

APPLICATIONS

● AV RECEIVERS

● DVD MOVIE PLAYERS

● DVD ADD-ON CARDS FOR HIGH-END PCs

● HDTV RECEIVERS

● CAR AUDIO SYSTEMS

● OTHER APPLICATIONS REQUIRING 24-BIT

AUDIO

Summary of content (24 pages)

PAGE 1
PCM1741 PCM 174 1 www.ti.com +3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● 24-BIT RESOLUTION ● AV RECEIVERS ● ANALOG PERFORMANCE (VCC = +3.3V): Dynamic Range: 98dB typ SNR: 98dB typ THD+N: 0.005% typ Full-Scale Output: 2.
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SPECIFICATIONS All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, fS = 44.1kHz, system clock = 384fS, and 24-bit data, unless otherwise noted.
PAGE 3
SPECIFICATIONS (Cont.) All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted. PCM1741E PARAMETER CONDITIONS ANALOG FILTER PERFORMANCE Frequency Response TYP f = 20kHz f = 44kHz POWER SUPPLY REQUIREMENTS(4) Voltage Range, VDD VCC Supply Current, IDD +3.3 +3.0 6.0 13.0 7.0 7.0 43 66 fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz Power Dissipation MAX –0.03 –0.20 +2.7 +2.
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BLOCK DIAGRAM BCK Audio Serial Port LRCK 8x Oversampling Digital Filter with Function Controller DATA ML VOUTL Low-Pass Filter Enhanced Multilevel Delta-Sigma Modulator VCOM Serial Control Port MC Output Amp and DAC Output Amp and DAC Low-Pass Filter VOUTR MD System Clock VCC AGND PIN ASSIGNMENTS TOP VIEW SSOP BCK 1 16 SCK DATA 2 15 ML LRCK 3 14 MC 4 VDD ZEROR ZEROL PIN CONFIGURATION DGND Power Supply Zero Detect DGND System Clock Manager SCK 13 MD PCM1741 V
PAGE 5
TYPICAL PERFORMANCE CURVES All specifications at TA = +25°C, VCC = VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. DIGITAL FILTER Digital Filter (De-Emphasis Off FREQUENCY RESPONSE PASSBAND (Sharp Roll-Off) FREQUENCY RESPONSE (Sharp Roll-Off) 0 0.05 0.04 –20 0.03 0.02 Amplitude (dB) Amplitude (dB) –40 –60 –80 –100 0.01 0 –0.01 –0.02 –0.03 –120 –0.04 –0.05 –140 0 1 2 3 4 0 0.1 0.2 Frequency (x fS) 0.3 0.4 0.
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TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25°C, VCC = VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. De-Emphasis (Cont.) DE-EMPHASIS ERROR (fS = 44.1kHz) 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 Error (dB) Level (dB) DE-EMPHASIS (fS = 44.1kHz) 0.0 –5.0 –6.0 0.0 –0.1 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –0.5 –10.
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TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25°C, VCC = VDD = 3.3V, and 24-bit input data, unless otherwise noted. Supply-Voltage Characteristics (Cont.) SNR vs VCC 106 CHANNEL SEPARATION vs VCC 106 104 104 44.1kHz, 384fS 100 SNR (dB) Channel Separation (dB) 102 98 96 94 96kHz, 384fS 92 90 102 100 98 44.1kHz, 384fS 96 94 92 96kHz, 384fS 90 88 88 86 86 2.4 2.7 3 3.3 3.6 3.9 4.2 2.4 2.7 3 VCC (V) 3.3 3.6 3.
PAGE 8
SYSTEM CLOCK AND RESET FUNCTIONS POWER-ON RESET FUNCTIONS The PCM1741 includes a power-on reset function, as shown in Figure 2. With the system clock active, and VDD > 2.0V (typical 1.6V to 2.4V), the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2.0V. After the initialization period, the PCM1741 will be set to its reset default state, as described in the Mode Control Register section of this data sheet.
PAGE 9
AUDIO SERIAL INTERFACE The audio serial interface for the PCM1741 is comprised of a 3-wire synchronous serial port. It includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, and is used to clock the serial data present on DATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1741 on the rising edge of BCK. LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface’s internal registers.
PAGE 10
LRCK 50% of VDD tBCH tBCL tLB BCK 50% of VDD tBCY tBL 50% of VDD DATA tDS SYMBOL tBCY tBCH tBCL tBL tLB tDS tDH tDH PARAMETER MIN MAX UNITS 32, 48, or 64fS(1) BCK Pulse Cycle Time BCK High Level Time BCK Low Level Time BCK Rising Edge to LRCK Edge LRCK Falling Edge to BCK Rising Edge DATA Set Up Time DATA Hold Time 35 35 10 10 10 10 ns ns ns ns ns ns NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.) FIGURE 4. Audio Interface Timing.
PAGE 11
MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1741 includes a number of user-programmable functions that are accessed via control registers. The registers are programmed using the Serial Control Interface that was previously discussed in the “Serial Control Interface” section of this data sheet. Table II lists the available mode control functions, along with their reset default conditions and associated register index. Register Map The mode control register map is shown in Table III.
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REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 Register 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 ATx[7:0] Digital Attenuation Level Setting where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
PAGE 13
REGISTER 19 DACx B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV B1 B0 DAC2 DAC1 DAC Operation Control where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2). Default Value: 0 DACx = 0 DACx = 1 DAC Operation Enabled (default) DAC Operation Disabled The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR.
PAGE 14
Register 20 (Cont.) FLT Digital Filter Roll-Off Control Default Value: 0 FLT = 0 FLT = 1 Sharp Roll-Off (default) Slow Roll-Off The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll-off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet.
PAGE 15
ANALOG OUTPUTS ANALOG FILTER PERFORMANCE (100Hz-10MHz) The PCM1741 includes two independent output channels: VOUTL and VOUTR. These are unbalanced outputs, each capable of driving 2.05Vp-p typical into a 5kΩ AC-coupled load. The internal output amplifiers for VOUTL and VOUTR are biased to the DC common-mode (or bipolar zero) voltage, equal to VCC/2.
PAGE 16
ZERO FLAGS Zero Detect Condition Zero Detection for each output channel is independent from the other. If the data for a given channel remains at a “0” level for 1024 sample periods (or LRCK clock periods), a Zero Detect condition exists for that channel. Zero Output Flags Given that a Zero Detect condition exists for one or more channels, the Zero Flag pins for those channels will be set to a logic “1” state. There are Zero Flag pins for each channel: ZEROL (pin 12) and ZEROR (pin 11).
PAGE 17
using a Multiple FeedBack (MFB) circuit arrangement that reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, please refer to Burr-Brown Applications Bulletin #34 AB-034 (SBFA001), available from our web site at http://www.ti.com. Since the overall system performance is defined by the quality of the DACs and their associated analog output circuitry, high-quality audio op amps are recommended for the active filters.
PAGE 18
THEORY OF OPERATION Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM1741. In cases where a common +3.3V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital +3.
PAGE 19
QUANTIZATION NOISE SPECTRUM (128x Oversampling) 0 0 –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) QUANTIZATION NOISE SPECTRUM (64x Oversampling) –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 –180 –180 0 1 2 3 4 5 6 7 8 0 1 Frequency (fS) 2 3 4 5 6 7 8 Frequency (fS) FIGURE 15. Quantization Noise Spectrum. The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 15.
PAGE 20
data is transmitted via a coaxial cable to the digital audio receiver on the DEM-DAI1741 demo board. The receiver is then configured to output 24-bit data in either I2S or leftjustified data format. The DAC audio interface format is programmed to match the receiver output format. The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The analog input is band limited using filters resident in the analyzer.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1741E/2K Package Package Pins Type Drawing SSOP/ QSOP DBQ 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1741E/2K SSOP/QSOP DBQ 16 2000 346.0 346.0 29.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.