Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 16

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FEATURES APPLICATIONS

DESCRIPTION

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma,

Audio Digital-to-Analog Converter

• AV Receivers

• 24-Bit Resolution

• DVD Movie Players

• Analog Performance (V

= 5 V):

• DVD Add-On Cards for High-End PCs

– Dynamic Range:

• DVD Audio Players

• 106 dB, Typical (PCM1742KE)

• HDTV Receivers

• 100 dB, Typical (PCM1742E)

• Car Audio Systems

– SNR:

• Other Applications Requiring 24-Bit Audio

• 106 dB, Typical (PCM1742KE)

• 100 dB, Typical (PCM1742E)

– THD+N:

The PCM1742 is a CMOS, monolithic, integrated

• 0.002%, Typical (PCM1742KE)

circuit which includes stereo digital-to-analog con-

verters (DACs) and support circuitry in a small

• 0.003%, Typical (PCM1742E)

SSOP-16 package. The data converters use Texas

– Full-Scale Output: 3.1 V

p-p

, Typical

Instruments' enhanced multilevel delta-sigma archi-

• 4x/8x Oversampling Digital Filter:

tecture that employs fourth-order noise shaping and

Stop-Band Attenuation: –55 dB

8-level amplitude quantization to achieve excellent

Pass-Band Ripple: ±0.03 dB

dynamic performance and improved tolerance to

clock jitter. The PCM1742 accepts industry-standard

• Sampling Frequency: 5 kHz to 200 kHz

audio data formats with 16- to 24-bit data, providing

• System Clock: 128 f

, 192 f

, 256 f

, 384 f

easy interfacing to audio DSP and decoder chips.

512 f

, 768 f

With Autodetect

Sampling rates up to 200 kHz are supported. A full

• Accepts 16-, 18-, 20-, and 24-Bit Audio Data

set of user-programmable functions is accessible

through a 3-wire serial control port that supports

• Data Formats: Standard, I

S, and

Left-Justified

• User-Programmable Mode Controls:

Digital Attenuation: 0 dB to –63 dB, 0.5

dB/Step

Digital De-Emphasis

Digital Filter Rolloff: Sharp or Slow

Soft Mute

Zero Flags for Each Output

• Dual-Supply Operation: 5-V Analog, 3.3-V

Digital

• 5-V Tolerant Digital Inputs

• Small SSOP-16 Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FilterPro is a trademark of Texas Instruments.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 24-Bit Resolution Analog Performance (VCC = 5 V): – Dynamic Range: • 106 dB, Typical (PCM1742KE) • 100 dB, Typical (PCM1742E) – SNR: • 106 dB, Typical (PCM1742KE) • 100 dB, Typical (PCM1742E) – THD+N: • 0.002%, Typical (PCM1742KE) • 0.003%, Typical (PCM1742E) – Full-Scale Output: 3.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Power supply voltage, VDD –0.3 V to 4 V Power supply voltage, VCC –0.3 V to 6.5 V Supply voltage difference, VCC, VDD VCC – VDD < 3 V Ground voltage differences ±0.1 V Digital input voltage –0.3 V to 6.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VOUT = 0 dB, fS = 44.1 kHz 0.002% 0.006% VOUT = 0 dB, fS = 96 kHz 0.003% VOUT = 0 dB, fS = 192 kHz 0.004% UNIT PCM1742KE THD+N Total harmonic distortion + noise VOUT = –60 dB, fS = 44.1 kHz 0.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS POWER SUPPLY REQUIREMENTS VDD VCC MIN TYP MAX 3 3.3 3.6 4.5 5 5.5 Voltage range 6 10 fS = 44.1 kHz IDD ICC UNIT (6) Supply current Supply current Power dissipation fS = 96 kHz 13 fS = 192 kHz 16 fS = 44.1 kHz 8.
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PCM1742 www.ti.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless otherwise noted Digital Filter (De-Emphasis Off) FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF) 0.05 0 0.04 −20 0.03 0.02 Amplitude (dB) Amplitude (dB) −40 −60 −80 −100 0.01 0 −0.01 −0.02 −0.03 −120 −0.04 −0.05 −140 0 1 2 3 0 4 0.1 0.2 0.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless otherwise noted Digital Filter (De-Emphasis) DE-EMPHASIS ERROR (fS = 32 kHz) 0.5 −1.0 0.4 −2.0 0.3 −3.0 0.2 −4.0 0.1 Error (dB) Level (dB) DE-EMPHASIS (fS = 32 kHz) 0.0 −5.0 −6.0 0.0 −0.1 −7.0 −0.2 −8.0 −0.3 −9.0 −0.4 −10.0 −0.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 TYPICAL PERFORMANCE CURVES (continued) ANALOG DYNAMIC PERFORMANCE All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS (under register control). Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs VCC (VDD = 3.3 V) DYNAMIC RANGE vs VCC (VDD = 3.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 TYPICAL PERFORMANCE CURVES (continued) ANALOG DYNAMIC PERFORMANCE (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS (under register control).
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 SYSTEM CLOCK AND RESET FUNCTIONS SYSTEM CLOCK INPUT The PCM1742 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 19 shows the timing requirements for the system clock input.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 POWER-ON RESET FUNCTIONS The PCM1742 includes a power-on-reset function, as shown in Figure 20. With the system clock active and VDD > 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After the initialization period, the PCM1742 is set to its reset default state, as described in the Mode Control Registers section of this data sheet.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 AUDIO DATA FORMATS AND TIMING The PCM1742 supports industry-standard audio data formats, including standard, I2S, and left-justified, as shown in Figure 21. Data formats are selected using the format bits, FMT[2:0], in control register 20. The default data format is 24-bit, left-justified. All formats require binary 2s complement, MSB-first audio data. See Figure 22 for a detailed timing diagram of the serial audio interface.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 LRCK 50% of VDD tBCH tBCL t LB BCK 50% of VDD tBCY tBL 50% of VDD DATA tDS SYMBOL t DH DESCRIPTION MIN MAX UNIT 1/(64 fS)(1) tBCY BCK pulse cycle time tBCH BCK high-level time 35 ns tBCL BCK low-level time 35 ns tBL BCK rising edge to LRCK edge 10 ns tLB LRCK falling edge to BCK rising edge 10 ns tDS DATA setup time 10 ns tDH DATA hold time 10 ns (1) fS is the sampling frequency (e.g., 44.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 SERIAL CONTROL INTERFACE The serial control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial control interface is used to program the on-chip mode registers. The serial control interface includes MD (pin 13), MC (pin 14), and ML (pin 15).
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 CONTROL INTERFACE TIMING REQUIREMENTS See Figure 25 for a detailed timing diagram of the serial control interface. These timing parameters are critical for proper control port operation.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 Register Map The mode control register map is shown in Table 3. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 3.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 B15 REGISTER 18 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 RSV OVER RSV RSV RSV RSV MUT2 MUT1 MUTx – Soft Mute Control where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 B15 REGISTER 19 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1 DACx – DAC Operation Control where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 B15 REGISTER 20 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0 FMT[2:0] – Audio Interface Data Format Default value: 101 The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows the available format options.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 B15 REGISTER 22 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 B6 B5 B4 B3 B2 B1 B0 RSV RSV RSV RSV RSV AZRO ZREV DREV DREV – Output Phase Select Default value: 0 DREV = 0 Normal output (default) DREV = 1 Inverted output The DREV bit is used to set the output phase of VOUTL and VOUTR.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 ANALOG OUTPUTS The PCM1742 includes two independent output channels: VOUTL and VOUTR. These are unbalanced outputs, each capable of driving 3.1 Vp-p typical into a 5-kΩ ac-coupled load. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to VCC/2.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 VCOM OUTPUT One unbuffered common-mode voltage output pin, VCOM (pin 10), is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to VCC/2. This pin can be used to bias external circuits. An example of using the VCOM pin for external biasing applications is shown in Figure 27.
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PCM1742 SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 www.ti.com ZERO FLAGS Zero-Detect Condition Zero detection for each output channel is independent from the other. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel. Zero Output Flags Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set to a logic-1 state.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 APPLICATION INFORMATION Connection Diagram A basic connection diagram is shown in Figure 28, with the necessary power-supply bypassing and decoupling components. Texas Instruments recommends using the component values shown in Figure 28 for all designs. + +3.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 APPLICATION INFORMATION (continued) AV ≈ − R2 R1 C1 R3 VIN 2 3 R1 R4 1 C2 R2 VOUT OP A2 134 Figure 29. Dual-Supply Filter Circuit Because the overall system performance is defined by the quality of the DACs and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 APPLICATION INFORMATION (continued) Power Supplies RF Choke or Ferrite Bead +5V AGND +VS −VS REG VCC VDD VDD Digital Logic and Audio Processor Output Circuits DGND PCM1742 AGND Common Ground DIGITAL SECTION ANALOG SECTION Figure 31. Single-Supply PCB Layout THEORY OF OPERATION The delta-sigma section of the PCM1742 is based on an 8-level amplitude quantizer and a fourth-order noise shaper.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 THEORY OF OPERATION (continued) QUANTIZATION NOISE SPECTRUM (128x Oversampling) 0 0 − 20 − 20 − 40 − 40 Amplitude (dB) Amplitude (dB) QUANTIZATION NOISE SPECTRUM (64x Oversampling) − 60 − 80 − 100 − 120 − 60 − 80 − 100 − 120 − 140 − 140 − 160 − 160 − 180 − 180 0 1 2 3 4 5 6 7 8 0 1 2 3 Frequency (fS) Figure 33.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 KEY PERFORMANCE PARAMETERS AND MEASUREMENT This section provides information on how to measure key dynamic performance parameters for the PCM1742. In all cases, a System Two™ Cascade audio measurement system by Audio Precision™ or equivalent audio measurement system is used to perform the testing.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued) Evaluation Board DEM−DAI1742 S/PDIF Receiver PCM1742(1) 2nd−Order Low−Pass Filter f− 3dB = 54kHz or 108kHz S/PDIF Output Digital Generator 0% Full−Scale, Dither Off (SNR) − 60dBFS, 1kHz Sine Wave (Dynamic Range) Analyzer and Display A−Weight Filter(2) rms Mode (1) Infinite-zero-detect mute disabled (2) Results without A-weighting are approximately 3 dB worse.
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PCM1742 www.ti.com SBAS176A – DECEMBER 2000 – REVISED APRIL 2005 REVISION HISTORY DATE REV PAGE Apr 2005 A – Global Changed to new format 2 Absolute Maximum Ratings Changed values for power supply voltage, digital input voltage, lead temperature, and package temperature. Added supply voltage difference, VCC – VDD < 3 V. 2 Electrical Characteristics Corrected maximum sampling frequency from 100 kHz to 200 kHz. Added new values of 128 fS and 192 fS for system clock frequency.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1742E/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PCM1742KE/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1742E/2K SSOP DBQ 16 2000 367.0 367.0 35.0 PCM1742KE/2K SSOP DBQ 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.