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PCM1753

PCM1754

PCM1755

SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009

24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA,

AUDIO DIGITAL-TO-ANALOG CONVERTER

FEATURES

D 24-Bit Resolution

D Analog Performance (V

= 5 V):

− Dynamic Range: 106 dB

− SNR: 106 dB, Typical

− THD+N: 0.002%, Typical

− Full-Scale Output: 4 V

, Typical

D 4×/8× Oversampling Digital Filter:

− Stop-Band Attenuation: –50 dB

− Pass-Band Ripple: ±0.04 dB

D Sampling Frequency: 5 kHz to 200 kHz

D System Clock: 128 f

, 192 f

, 256 f

, 384 f

512 f

, 768 f

, 1152 f

with Auto Detect

D Software Control (PCM1753, PCM1755):

− Accepts 16-, 18-, 20-, and 24-Bit Audio

Formats: Standard, I

S, and Left-Justified

− Digital Attenuation: 0 dB to –63 dB,

0.5 dB/Step

− Digital De-Emphasis

− Digital Filter Rolloff: Sharp or Slow

− Soft Mute

− Zero Flags for Each Output

− Open-Drain Output Zero Flag (PCM1755)

D Hardware Control (PCM1754):

− I

S and 16-Bit Word, Right-Justified

− 44.1 kHz Digital De-Emphasis

− Soft Mute

− Zero Flag for L-, R-Channel Common

Output

D Power Supply: 5-V Single Supply

D Small 16-Lead SSOP Package, Lead-Free

APPLICATIONS

D A/V Receivers

D DVD Movie Players

D DVD Add-On Cards for High-End PCs

D DVD Audio Players

D HDTV Receivers

D Car Audio Systems

D Other Applications Requiring 24-Bit Audio

DESCRIPTION

The PCM1753/54/55 is a CMOS, monolithic, integrated

circuit, which includes stereo digital-to-analog converters

and support circuitry in a small 16-lead SSOP package.

The data converters use TI’s enhanced multilevel

delta-sigma architecture, which employs 4th-order noise

shaping and 8-level amplitude quantization to achieve

excellent dynamic performance and improved tolerance to

clock jitter. The PCM1753/54/55 accepts industry-

standard audio data formats with 16- to 24-bit data,

providing easy interfacing to audio DSP and decoder

chips. Sampling rates up to 200 kHz are supported. A full

set of user-programmable functions is accessible through

a three-wire serial control port, which supports register

write functions.

The PCM1753/55 is pin-compatible with the PCM1748,

PCM1742, and PCM1741, except for pin 5.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

Audio Precision and System Two are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Burr-Brown Audio

Summary of content (39 pages)

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PCM1753 PCM1754 PCM1755 Burr-Brown Audio SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER FEATURES D 24-Bit Resolution D Analog Performance (VCC = 5 V): − − − − Dynamic Range: 106 dB SNR: 106 dB, Typical THD+N: 0.002%, Typical Full-Scale Output: 4 VPP, Typical D 4×/8× Oversampling Digital Filter: − Stop-Band Attenuation: –50 dB − Pass-Band Ripple: ±0.
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PCM1753 PCM1754 PCM1755 www.ti.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ELECTRICAL CHARACTERISTICS (CONTINUED) All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. PARAMETER TEST CONDITIONS PCM1753DBQ, PCM1754DBQ, PCM1755DBQ MIN TYP UNIT MAX DIGITAL INPUT/OUTPUT Logic family VIH VIL Input logic level IIH(1) IIL(1) IIH(2) IIL(2) VOH(3) VOL(4) TTL compatible 2 0.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ELECTRICAL CHARACTERISTICS (CONTINUED) All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted. PARAMETER TEST CONDITIONS PCM1753DBQ, PCM1754DBQ, PCM1755DBQ MIN TYP UNIT MAX FILTER CHARACTERISTICS (SLOW ROLLOFF, PCM1753/PCM1755) Pass band ±0.5 dB Stop band 0.198 fs 0.884 fs Pass-band ripple ±0.5 Stop-band attenuation Stop band = 0.
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PCM1753 PCM1754 PCM1755 www.ti.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Terminal Functions TERMINAL NAME NO.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 TYPICAL PERFORMANCE CURVES DIGITAL FILTER (DE-EMPHASIS OFF) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 0.04 −20 0.03 0.02 Amplitude – dB Amplitude – dB −40 −60 −80 0.01 0.00 −0.01 −0.02 −100 −0.03 −120 −140 −0.04 0 1 2 3 −0.05 0.0 4 0.1 0.2 0.3 0.4 0.5 Frequency [× fS] Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 DE-EMPHASIS CURVES DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 32 kHz −1 0.3 De-emphasis Error – dB De-emphasis Level – dB −2 −3 −4 −5 −6 −7 0.1 0.0 −0.1 −0.2 −0.3 −9 −0.4 0 2 4 6 8 10 12 −0.5 14 2 4 6 8 Figure 5 Figure 6 DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 12 14 0.5 fS = 44.1 kHz fS = 44.1 kHz 0.4 0.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 DE-EMPHASIS CURVES (CONTINUED) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 48 kHz −1 0.3 De-emphasis Error – dB De-emphasis Level – dB −2 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 fS = 48 kHz 0.4 0 2 4 6 8 10 12 14 16 18 20 22 −0.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ANALOG DYNAMIC PERFORMANCE (SUPPLY VOLTAGE CHARACTERISTICS) TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 110 192 kHz, 128 fS 96 kHz, 384 fS 1 108 –60 dB 44.1 kHz, 384 fS Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 10 44.1 kHz, 384 fS 0.1 96 kHz, 384 fS 192 kHz, 128 fS 0.01 0 dB 0.001 0.0001 4.0 44.1 kHz, 384 fS 4.5 5.0 5.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ANALOG DYNAMIC PERFORMANCE (TEMPERATURE CHARACTERISTICS) TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 110 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS 44.1 kHz, 384 fS 0.1 192 kHz, 128 fS 96 kHz, 384 fS 0.01 0.001 0.0001 −50 108 –60 dB 1 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 10 0 dB 44.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1753/54/55 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 19 shows the timing requirements for the system clock input.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Power-On Reset Functions The PCM1753/54/55 includes a power-on reset function. Figure 20 shows the operation of this function. With the system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V).
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 AUDIO SERIAL INTERFACE The audio serial interface for the PCM1753/54/55 consists of a 3-wire synchronous serial port. It includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1753/54/55 on the rising edge of BCK.
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PCM1753 PCM1754 PCM1755 www.ti.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ZERO FLAGS (PCM1753/55) Zero-Detect Condition Zero detection for either output channel is independent from the other channel. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel. Zero Flag Outputs If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic 1 state.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 SOFTWARE CONTROL (PCM1753/55) The PCM1753/55 has many programmable functions which can be controlled in the software control mode. The functions are controlled by programming the internal registers using ML, MC, and MD. The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface. The serial control interface is used to program the on-chip mode registers.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Control Interface Timing Requirements Figure 25 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 MODE CONTROL REGISTERS (PCM1753/55) User-Programmable Mode Controls The PCM1753/55 includes a number of user programmable functions, which are accessed via control registers. The registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 5 lists the available mode control functions, along with their reset default conditions and associated register index.
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PCM1753 PCM1754 PCM1755 www.ti.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed attenuation level.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function Default value: 00 The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. DMF[1:0] Register 20 De-Emphasis Sample Rate Selection 00 44.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 ZREV: Zero Flag Polarity Select Default value: 01h ZREV = 0 High on zero flag pins indicates a zero detect (default) ZREV = 1 Low on zero flag pins indicates a zero detect The ZREV bit allows the user to select the polarity of zero flag pins.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 VCOM Output One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to 0.5 VCC. This pin can be used to bias external circuits. Figure 27 shows an example of using the VCOM pin for external biasing applications.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 APPLICATION INFORMATION CONNECTION DIAGRAMS A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling components. TI recommends using the component values shown in Figure 28 for all designs. The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 POWER SUPPLIES AND GROUNDING The PCM1753/54/55 requires 5 V for VCC. Proper power supply bypassing is shown in Figure 28. The 10-μF capacitors should be tantalum or aluminum electrolytic. D/A OUTPUT FILTER CIRCUITS Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Digital Power +VD Analog Power DGND AGND +5VA +VS –VS VCC Digital Logic and Audio Processor Output Circuits DGND PCM1753/54/55 Digital Ground AGND Digital Section Analog Ground Analog Section Return Path for Digital Signals Figure 30. Recommended PCB Layout Separate power supplies are recommended for the digital and analog sections of the board.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 THEORY OF OPERATION The delta-sigma section of the PCM1753/54/55 is based on an 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 32.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 AMPLITUDE vs FREQUENCY 0 −20 −20 −40 −40 −60 −60 Amplitude – dB 0 −80 −100 −120 −80 −100 −120 −140 −140 −160 −160 −180 0 1 2 3 4 5 6 7 −180 8 0 1 2 Frequency [ fS] 3 4 5 6 7 8 Frequency [ fS] Figure 33. Quantization Noise Spectrum ( 64 Oversampling) Figure 34.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Dynamic Range Dynamic range is specified as A-weighted THD+N measured with a –60-dB full-scale, 1-kHz digital sine wave stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the DAC performs given a low-level input signal. The measurement setup for the dynamic range measurement is shown in Figure 37, and is similar to the THD+N test setup discussed previously.
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PCM1753 PCM1754 PCM1755 www.ti.com SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009 Evaluation Board DEM-DAI1753 S/PDIF Receiver 2nd-Order Low-Pass Filter PCM1753/54/55 f–3 dB = 54 kHz or 108 kHz Audio Precision System Two S/PDIF Output Digital Generator 0% Full-Scale, Dither Off (SNR) or –60 dB FS, 1 kHz Sine Wave (Dynamic Range) (1) Results Analyzer and Display Averaging Mode A-Weighting Filter(1) AES17 Filter Band Limit HPF = 400 Hz LPF = 30 kHz f–3 dB = 20.
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Revision History DATE REV 2/09 C PAGE SECTION 12 System Clock and Reset Functions 14 Audio Serial Interface DESCRIPTION Changed value of 192 kHz at 256 fS from “49.1520” to note “(1)” in Table 1. Changed text. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1753DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PCM1754DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PCM1755DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1753DBQR SSOP DBQ 16 2000 367.0 367.0 35.0 PCM1754DBQR SSOP DBQ 16 2000 367.0 367.0 35.0 PCM1755DBQR SSOP DBQ 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.